CN114364167B - Double-layer packaging substrate alignment method suitable for laser through holes - Google Patents
Double-layer packaging substrate alignment method suitable for laser through holes Download PDFInfo
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- CN114364167B CN114364167B CN202111593301.6A CN202111593301A CN114364167B CN 114364167 B CN114364167 B CN 114364167B CN 202111593301 A CN202111593301 A CN 202111593301A CN 114364167 B CN114364167 B CN 114364167B
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- 239000000758 substrate Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 83
- 229910052802 copper Inorganic materials 0.000 claims abstract description 60
- 239000010949 copper Substances 0.000 claims abstract description 60
- 239000010410 layer Substances 0.000 claims abstract description 58
- 238000005553 drilling Methods 0.000 claims abstract description 25
- 239000000126 substance Substances 0.000 claims abstract description 20
- 238000009713 electroplating Methods 0.000 claims abstract description 17
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 238000013461 design Methods 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 230000008021 deposition Effects 0.000 claims abstract description 8
- 238000005520 cutting process Methods 0.000 claims abstract description 7
- 239000002131 composite material Substances 0.000 claims abstract description 4
- 239000011889 copper foil Substances 0.000 claims description 23
- 239000003814 drug Substances 0.000 claims description 12
- 239000007788 liquid Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 238000006243 chemical reaction Methods 0.000 claims description 10
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 9
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 7
- 239000012792 core layer Substances 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 7
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- 238000003825 pressing Methods 0.000 claims description 6
- 238000005507 spraying Methods 0.000 claims description 6
- 239000002355 dual-layer Substances 0.000 claims description 5
- 239000003292 glue Substances 0.000 claims description 5
- 238000011161 development Methods 0.000 claims description 4
- 238000007731 hot pressing Methods 0.000 claims description 4
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 claims description 3
- 230000000379 polymerizing effect Effects 0.000 claims description 3
- 238000007127 saponification reaction Methods 0.000 claims description 3
- 239000002893 slag Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical compound [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- 101001134276 Homo sapiens S-methyl-5'-thioadenosine phosphorylase Proteins 0.000 description 1
- 102100022050 Protein canopy homolog 2 Human genes 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 125000003178 carboxy group Chemical group [H]OC(*)=O 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910001431 copper ion Inorganic materials 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000011780 sodium chloride Substances 0.000 description 1
- SUKJFIGYRHOWBL-UHFFFAOYSA-N sodium hypochlorite Chemical compound [Na+].Cl[O-] SUKJFIGYRHOWBL-UHFFFAOYSA-N 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000033772 system development Effects 0.000 description 1
- 230000026676 system process Effects 0.000 description 1
Abstract
A double-layer packaging substrate alignment method suitable for laser through holes comprises the following steps: cutting: cutting a substrate with a certain size; mechanical drilling: manufacturing a laser front line alignment reference A and a graph line alignment reference D; laser front line: manufacturing a laser drilling alignment reference B, a laser hole windowing and a line alignment reference C windowing; laser drilling: manufacturing laser via holes in the effective area for interlayer conduction and line alignment references C; copper deposition electroplating: performing desmear, chemical copper and electroplating copper treatment on the laser via hole for interlayer conduction and the via hole of the reference C, so that the inner wall of the hole is plated with copper to conduct the layers mutually; graphic circuit: when the graph line is manufactured, the composite hole fitted by the reference C and the reference D is used as an alignment reference. The application relates to a multiple alignment standard, which meets the design requirement that the interlayer alignment degree is less than or equal to 25um on the premise of ensuring the alignment degree of the patterns on the same layer and the empty.
Description
Technical Field
The application relates to a packaging substrate, in particular to a double-layer packaging substrate alignment method suitable for laser through holes.
Background
Currently, the main flow of packaging substrates has three processing technologies, namely a Tenting masking method technology, an MSAP technology and an SAP technology, which are three different technological systems. In the Tenting process, the conventional double-sided board is basically aligned by taking a drilled hole as a reference, and the alignment degree of the hole and the pattern is slightly poor; according to the conventional alignment system design, the design of the hole ring more than 60um can be met, and the high-precision wiring design can not be met.
Along with the trend of electronic products becoming smaller, the precision requirement of the packaging substrate is also higher, the introduction of higher-precision equipment can increase the fixed assets of enterprises, so that the cash flow of the enterprises is reduced intangibly, and the operation burden of the enterprises is increased. Therefore, a new set of alignment system development is required to be developed, so that the product design requirement is met, and large investment is not required.
Disclosure of Invention
In order to overcome the defects, the application provides a double-layer packaging substrate alignment method suitable for laser through holes, wherein multiple alignment references are involved in the alignment method, and the design requirement that the interlayer alignment is less than or equal to 25um is met on the premise of ensuring the alignment degree of the patterns on the same layer and the empty.
The technical scheme adopted by the application for solving the technical problems is as follows:
a double-layer packaging substrate alignment method suitable for laser through holes comprises the following steps:
step 1: cutting: cutting a substrate with a certain size, wherein the substrate is provided with a core layer, and a first inner copper foil layer and a second inner copper foil layer which are respectively arranged on the front side and the back side of the core layer;
step 2: mechanical drilling: manufacturing a laser front line alignment reference A and a graphic line alignment reference D on the edge of the substrate by utilizing mechanical drilling;
step 3: laser front line: b, using the A as a reference, manufacturing a laser drilling alignment reference B, a laser hole windowing and a line alignment reference C windowing;
step 4: laser drilling: b is taken as a reference, laser via holes in the effective area are manufactured for interlayer conduction, and a circuit alignment reference C is manufactured;
step 5: copper deposition electroplating: performing desmear, chemical copper and electroplating copper treatment on the laser via hole for interlayer conduction and the via hole of the reference C, so that the inner wall of the hole is plated with copper to conduct the layers mutually;
step 6: graphic circuit: and carrying out line pretreatment, dry film pressing, exposure, development, etching and film stripping treatment on the first copper foil layer and the second copper foil layer of the substrate to form a pattern line, wherein when the pattern line is manufactured, a composite hole fitted by a reference C and a reference D is used as an alignment reference.
Preferably, in step 2, the fiducial a and the fiducial D are mechanical through holes, and the aperture of the fiducial a and the fiducial D is 0.1 to 5.0mm.
Preferably, in step 3, the reference B is an etched PAD, and the shape may be circular, square or triangular.
Preferably, in step 4, the datum C is composed of a circle of laser through holes surrounding the datum D, and the aperture of the through hole of the datum C is 0.2-0.5 mm.
Preferably, in the step 6, during graph alignment, a circle of virtual circular holes of the through hole center of the reference C are grasped, meanwhile, a circle of circular holes of the reference D are grasped, the virtual circular holes and the reference D are calculated in proportion to obtain a final fitting alignment reference, and the outer layer graph circuit is manufactured according to the fitting alignment reference.
Preferably, the graphic circuit in the step 6 specifically includes the following steps:
(1) Pretreatment: cleaning the surface of the plate by using a cleaning solution containing hydrogen peroxide, and coarsening the surface of the copper foil layer by using a sulfuric acid solution;
(2) Pressing dry film: adhering a photosensitive dry film on the surface of the copper foil layer in a hot pressing mode;
(3) Exposure: polymerizing the photosensitive substance in the photosensitive dry film by using an LDI exposure machine, so that the designed pattern is transferred to the photosensitive dry film;
(4) Developing: saponification reaction of the developing solution and the unexposed dry film is utilized to remove the film;
(5) Etching: spraying copper chloride liquid medicine on the copper surface through an etching machine, and etching the copper surface which is not protected by the dry film by utilizing chemical reaction of the liquid medicine and copper to form a circuit;
(6) Film stripping: spraying NaOH or KOH liquid medicine on the board surface through a film removing machine, and removing the dry film by utilizing the chemical reaction of the liquid medicine and the dry film to finish the manufacture of the circuit;
(7) AOI: the AOI system checks the lines on the copper surface against the differences between the etched lines and the original design lines.
Preferably, the step 5 copper deposition electroplating specifically includes the following steps:
(1) Removing glue residues: removing the gumming slag generated during drilling by using a plasma method;
(2) Chemical copper: depositing a thin uniform chemical copper layer with conductivity in the hole through chemical action;
(3) Electroplating copper: plating a layer of electroplated copper layer on the surface of the chemical copper layer in an electroplating mode.
The beneficial effects of the application are as follows:
1) According to the application, the reference C manufactured by using laser windowing and laser drilling is used as an alignment reference of a graph line, so that the alignment deviation of the graph line and the laser drilling is only the deviation of line exposure, the design requirement that the minimum aperture ring is 20 mu m can be realized, the alignment reference C is designed into a circle of small holes, and the circle of small holes are used as the reference, so that the alignment deviation problem caused by poor manufacturing of one of the small holes can be solved;
2) According to the application, the reference D formed by mechanical drilling is added into the pattern line alignment reference, so that the interlayer alignment degree of the 2-layer plates can be ensured, the design requirement that the interlayer alignment degree is less than or equal to 25um is met on the premise of ensuring the alignment degree of the patterns and holes on the same layer, and the leakage of the interlayer alignment degree, which is sacrificed due to the simple pursuit of the alignment degree of the single-layer patterns and the holes, can be avoided; the application only improves the alignment degree in design, the related processes are mature processes, equipment with higher precision is not needed to be input, the input cost is greatly reduced, and the design requirement of high-precision products is met on the premise of not obviously improving the enterprise cost.
Drawings
FIG. 1 is a schematic view of a substrate according to the present application;
FIG. 2 is a schematic view of the reference A after mechanical drilling in the present application;
FIG. 3 is a schematic view of the reference D after mechanical drilling in the present application;
FIG. 4 is a schematic diagram of the structure of the front and rear circuits of the substrate according to the present application;
FIG. 5 is a top view of the front and rear laser traces of the substrate of the present application;
FIG. 6 is a schematic diagram of reference B in the present application;
FIG. 7 is a schematic diagram of a laser drilling structure of a substrate according to the present application;
FIG. 8 is a top view of the substrate of the present application after laser drilling;
FIG. 9 is a schematic diagram of a substrate after copper deposition plating according to the present application;
FIG. 10 is a schematic diagram of the structure of the circuit of the substrate pattern according to the present application;
FIG. 11 is a schematic diagram of references C and D in the present application;
in the figure: 10-base plate, 11-core layer, 12-first inner copper foil layer, 13-second inner copper foil layer.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the application described herein may be capable of being practiced otherwise than as specifically shown or described. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Examples: as shown in fig. 1-11, a dual-layer package substrate alignment method suitable for laser vias includes the following steps:
step 1: cutting: as shown in fig. 1, a substrate 10 having a core layer 11 and first and second inner copper foil layers 12 and 13 respectively provided on both front and back sides of the core layer is cut to a certain size;
step 2: mechanical drilling: as shown in fig. 2 and 3, a laser front line alignment reference a and a graphic line alignment reference D are manufactured on the edge of the substrate by mechanical drilling;
step 3: laser front line: b, using the A as a reference, manufacturing a laser drilling alignment reference B, a laser hole windowing and a line alignment reference C windowing; fig. 4 and 5 show windowing of the line alignment reference C, and fig. 6 shows the alignment reference B;
step 4: laser drilling: b is taken as a reference, laser via holes in the effective area are manufactured for interlayer conduction, and a circuit alignment reference C is manufactured; the step completes the manufacture of the via hole of the effective area for the layer conduction, wherein the via hole is manufactured by taking B as a reference and B is taken A as a reference, so that the alignment degree of the laser via hole and the line on the same layer is high, as shown in fig. 7 and 8, and the reference C is irradiated at the same time; the hole in the effective area needs to be controlled in hole pattern during laser, and the size of the waist aperture is controlled to be 40% -70% of the upper/lower aperture; reference C aperture, waist aperture > 70%. Upper/lower aperture;
step 5: copper deposition electroplating: as shown in fig. 9, desmear, electroless copper and electrolytic copper plating are performed on laser via holes for interlayer conduction and via holes of reference C, so that the inner walls of the holes are plated with copper to conduct the layers to each other; the inner hole of the effective area is beneficial to hole filling due to small hole diameter and hole type, can be filled with copper, only the side wall of the reference C is plated with a layer of copper, is not filled with copper, and is beneficial to line alignment and grabbing;
step 6: graphic circuit: the first copper foil layer 12 and the second copper foil layer 13 of the substrate are subjected to line pretreatment, dry film pressing, exposure, development, etching and film stripping treatment to form a pattern line, wherein when the pattern line is manufactured, a composite hole fitted by a reference C and a reference D is used as an alignment reference. As shown in fig. 10-11, because the reference D and the reference C are used as alignment references and the reference C is used as reference B for manufacturing when the circuit is manufactured, the alignment degree of the same-layer pattern and the via hole is ensured, and the design requirement that the alignment degree of the interlayer circuit is less than or equal to 25um is met; all the alignment references are arranged at the edge of the substrate without affecting the effective area on the substrate.
In the step 2, the datum A and the datum D are mechanical through holes, and the aperture of the datum A and the aperture of the datum D are 0.1-5.0 mm. Fig. 2 shows the alignment reference a, and fig. 3 shows the alignment reference D.
In step 3, the reference B is an etched PAD, and the shape may be circular, square or triangular. As shown in fig. 6, the reference B in this embodiment is a circular PAD.
In the step 4, the datum C consists of a circle of laser through holes surrounding the datum D, and the aperture of the through hole of the datum C is 0.2-0.5 mm. As shown in fig. 7-8, the datum C is formed by a circle of laser through holes, and the circle of through holes surrounds the circumference of the datum D.
In the step 6, as shown in fig. 10 and 11, during graph alignment, a circle of virtual circular holes of the through hole center of the reference C is grasped, meanwhile, a circular hole of the reference D is grasped, the virtual circular holes and the reference D are calculated in proportion to obtain a final fitting alignment reference, and the outer layer graph circuit is manufactured according to the fitting alignment reference. Illustrating: fitting a final alignment reference by using the ratio of the round hole virtually formed by the reference C to 60% and the ratio of the reference D to 40%, wherein the alignment degree between the pattern circuit manufactured by the alignment reference and the via hole for interlayer conduction is higher; the round hole (shown in figure 11) formed by the virtual circle of small holes of the alignment reference C is taken as a reference, so that the problem of alignment deviation caused by poor manufacture of one hole can be solved; when the pattern circuit is manufactured, the reference C and the reference D are used as alignment references, so that the high alignment degree of the patterns on the same layer and the through holes is ensured, and the requirement of the high alignment degree of the interlayer circuit is met.
The graphic circuit in the step 6 specifically comprises the following steps:
(1) Pretreatment: cleaning the surface of the plate by using a cleaning solution containing hydrogen peroxide, and coarsening the surface of the copper foil layer by using a sulfuric acid solution; cleaning the plate surface to remove attachments such as stains, oxides and the like; the copper surface can be roughened by microetching with sulfuric acid solution, the adhesive force with the dry film is increased, and the main chemical reaction is as follows: cu+H 2 O 2 →CuO+H 2 O；CuO+H 2 SO 4 →CuSO 4 +H 2 O; the copper foil layer can be an inner copper foil layer, a secondary outer copper foil layer and an outer copper foil layer, which are the same as below;
(2) Pressing dry film: adhering a photosensitive dry film on the surface of the copper foil layer in a hot pressing mode; a photosensitive dry film is pressed on the copper surface layer and used for subsequent image transfer, and after the dry film is heated, the dry film has fluidity and a certain filling property, and is attached to the surface of the board in a hot pressing mode by utilizing the characteristic;
(3) Exposure: polymerizing the photosensitive substance in the photosensitive dry film by using an LDI exposure machine, so that the designed pattern is transferred to the photosensitive dry film; an LDI exposure machine (Laser Direcl Imaging laser direct imaging) utilizes Ultraviolet (UV) energy to complete pattern transfer;
(4) Developing: saponification reaction of the developing solution and the unexposed dry film is utilized to remove the film; the exposed dry film does not react with the developer, and the development main chemical reaction: R-COOH+Na 2 CO 3 →R-COO-Na + +2NaHCO 3 ；
(5) Etching: spraying copper chloride liquid medicine on the copper surface by an etching machine, and carrying out chemical reaction on the copper surface which is not protected by the dry film by utilizing the chemical reaction of the liquid medicine and copperEtching to form a circuit; the main chemical reaction: 3Cu+NaClO 3 +6HCl→3CuCl 2 +3H 2 O+NaCl；
(6) Film stripping: spraying NaOH or KOH liquid medicine on the board surface through a film removing machine, and removing the dry film by utilizing the chemical reaction of the liquid medicine and the dry film to finish the manufacture of the circuit;
(7) AOI: the AOI system checks the lines on the copper surface against the differences between the etched lines and the original design lines. AOI is Automatic Optical Inspection automated optical inspection), the Genesis system processes the CAM data of the original design line into reference data for inspection and outputs to the AOI system. The AOI system uses the optical principle to judge defects such as short circuit, circuit break, notch and the like by comparing the difference between the etched circuit and the designed circuit.
The step 5 copper deposition electroplating specifically comprises the following steps:
(1) Removing glue residues: removing the gumming slag generated during drilling by using a plasma method; in the high temperature of laser, when the temperature exceeds the Tg point of the resin, the resin is in a softened or even gasified state, the formed fluid can be coated on the hole wall, and after cooling, glue residue paste (smooth) is formed, so that a gap is formed between copper walls of an inner copper hole ring which is subsequently manufactured, and therefore, before chemical copper (PTH), formed glue residues are required to be removed, so that smooth adhesion of the chemical copper which is subsequently manufactured Cheng Kongna is facilitated;
(2) Chemical copper: depositing a thin uniform chemical copper layer with conductivity in the hole through chemical action; namely, the original non-metallized hole wall is metallized, so that the subsequent smooth plating of electrochemical copper is facilitated;
(3) Electroplating copper: plating a layer of electroplated copper layer on the surface of the chemical copper layer in an electroplating mode. In the electroplating bath, the copper ion components in the solution are uniformly reduced on the copper surface and in the holes by using a mode of applying alternating current (cathode to obtain electronic copper plating and anode to lose electronic dissolved copper), so that the thickness of the copper layer is required by specifications.
It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (5)
1. A double-layer packaging substrate alignment method suitable for laser through holes is characterized in that: the method comprises the following steps:
step 1: cutting: cutting a substrate (10) with a certain size, wherein the substrate is provided with a core layer (11), a first inner copper foil layer (12) and a second inner copper foil layer (13) which are respectively arranged on the front side and the back side of the core layer;
step 2: mechanical drilling: manufacturing a laser front line alignment reference A and a graphic line alignment reference D on the edge of the substrate by utilizing mechanical drilling;
step 3: laser front line: b, using the A as a reference, manufacturing a laser drilling alignment reference B, a laser hole windowing and a line alignment reference C windowing;
step 4: laser drilling: b is taken as a reference, laser via holes in the effective area are manufactured for interlayer conduction, and a circuit alignment reference C is manufactured;
step 5: copper deposition electroplating: performing desmear, chemical copper and electroplating copper treatment on the laser via hole for interlayer conduction and the via hole of the reference C, so that the inner wall of the hole is plated with copper to conduct the layers mutually;
step 6: graphic circuit: performing line pretreatment, dry film pressing, exposure, development, etching and film stripping treatment on a first inner copper foil layer (12) and a second inner copper foil layer (13) of the substrate to form a graph line, wherein when the graph line is manufactured, a composite hole fitted by a reference C and a reference D is used as an alignment reference;
in the step 4, the datum C consists of a circle of laser through holes surrounding the datum D, and the aperture of the through hole of the datum C is 0.2-0.5 mm;
in the step 6, during graph alignment, a circle of virtual round holes of the through hole center of the reference C are grabbed, meanwhile, round holes of the reference D are grabbed, the virtual round holes and the reference D are calculated according to proportion to obtain a final fitting alignment reference, and the outer layer graph line is manufactured according to the fitting alignment reference.
2. The dual-layer package substrate alignment method for laser vias of claim 1, wherein: in the step 2, the datum A and the datum D are mechanical through holes, and the aperture of the datum A and the aperture of the datum D are 0.1-5.0 mm.
3. The dual-layer package substrate alignment method for laser vias of claim 1, wherein: in step 3, the reference B is an etched PAD, and the shape may be circular, square or triangular.
4. The dual-layer package substrate alignment method for laser vias of claim 1, wherein: the graphic circuit in the step 6 specifically comprises the following steps:
(1) Pretreatment: cleaning the surface of the plate by using a cleaning solution containing hydrogen peroxide, and coarsening the surface of the copper foil layer by using a sulfuric acid solution;
(2) Pressing dry film: adhering a photosensitive dry film on the surface of the copper foil layer in a hot pressing mode;
(3) Exposure: polymerizing the photosensitive substance in the photosensitive dry film by using an LDI exposure machine, so that the designed pattern is transferred to the photosensitive dry film;
(4) Developing: saponification reaction of the developing solution and the unexposed dry film is utilized to remove the film;
(5) Etching: spraying copper chloride liquid medicine on the copper surface through an etching machine, and etching the copper surface which is not protected by the dry film by utilizing chemical reaction of the liquid medicine and copper to form a circuit;
(6) Film stripping: spraying NaOH or KOH liquid medicine on the board surface through a film removing machine, and removing the dry film by utilizing the chemical reaction of the liquid medicine and the dry film to finish the manufacture of the circuit;
(7) AOI: the AOI system checks the lines on the copper surface against the differences between the etched lines and the original design lines.
5. The dual-layer package substrate alignment method for laser vias of claim 1, wherein: the step 5 copper deposition electroplating specifically comprises the following steps:
(1) Removing glue residues: removing the gumming slag generated during drilling by using a plasma method;
(2) Chemical copper: depositing a thin uniform chemical copper layer with conductivity in the hole through chemical action;
(3) Electroplating copper: plating a layer of electroplated copper layer on the surface of the chemical copper layer in an electroplating mode.
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| CN202111593301.6A CN114364167B (en) | 2021-12-23 | 2021-12-23 | Double-layer packaging substrate alignment method suitable for laser through holes |
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| CN202111593301.6A CN114364167B (en) | 2021-12-23 | 2021-12-23 | Double-layer packaging substrate alignment method suitable for laser through holes |
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