CN112040677A - Novel circuit board lamination method - Google Patents

Abstract

The invention relates to a novel circuit board laminating method, which comprises the following steps of S1: cutting and drilling the ultrathin core plate; s2: depositing copper to form a thin copper layer; s3: carrying out first pattern electroplating on the ultrathin core plate to form a boss; s4: pasting a dry film on the ultrathin core plate, wherein the thickness of the dry film is larger than the height of the boss; s5: carrying out secondary pattern electroplating on the ultrathin core plate, and plating tin on the top of the boss; s6: etching away the thin copper layer outside the boss; s7: removing tin on the top of the boss to form a copper column; s8: the ultrathin core plate is browned and then pressed, and the flowing pp is filled at the periphery of the copper column; s9: polishing the top of the copper column to expose the top of the copper column; s10: microetching the pressed board surface and roughening the surface; s11: and depositing copper on the PP at the top and the periphery of the copper column to manufacture an outer layer circuit. S12: repeating the steps S3 to S11 to form the multi-layer board. The laminated board generated by the novel circuit board laminating method has good reliability and high production efficiency.

Description

Novel circuit board lamination method

Technical Field

The invention relates to the technical field of circuit board manufacturing, in particular to a novel circuit board lamination method.

Background

With the vigorous development of the electronic industry, electronic products have entered the development stage of functionalization and intellectualization, and in order to meet the development requirements of high integration, miniaturization and miniaturization of electronic products, printed circuit boards or semiconductor integrated circuit package substrates are also developed towards the design trend of light, thin, short and small on the premise of meeting the good electrical and thermal properties of electronic products, so as to reduce the size and the overall thickness of the printed circuit boards or semiconductor integrated circuit package substrates and meet the development requirements of miniaturization of electronic products.

The Build-up method Multilayer Board (BUM) is characterized in that on an insulating substrate or a traditional double-sided board or Multilayer board, an insulating medium is coated, and then conducting wires and connecting holes are formed through electroless copper plating and electrolytic copper plating, and the conducting wires and the connecting holes are overlapped for multiple times to form the Multilayer printed board with the required number of layers in an accumulated mode. The multi-layer plates of the lamination method need to be conducted, the copper column is a common conduction mode, the existing copper column generation method generally adopts a through hole pulse plating method, the time consumption for forming the copper column is long, the shape of the copper column is single, and the formation of the special-shaped copper column is not facilitated.

Disclosure of Invention

The invention aims to provide a novel circuit board laminating method, which aims to solve the problem of connection among layers of a high-precision printed circuit board.

In order to achieve the above purpose, the following technical solutions are provided.

A novel circuit board lamination method comprises the following steps,

s1: providing an ultrathin core plate, and cutting and drilling the ultrathin core plate;

s2: depositing copper, and forming a thin copper layer on the surface of the ultrathin core plate;

s3: carrying out first-time pattern electroplating on the ultrathin core plate, and thickening a copper layer at a specified position to form a boss;

s4: carrying out dry film pasting operation on the ultrathin core plate, wherein the thickness of a dry film is larger than the height of the boss;

s5: carrying out secondary pattern electroplating on the ultrathin core plate, and plating a tin layer on the top of the boss;

s6: etching away the thin copper layer outside the boss;

s7: removing the tin layer on the top of the boss to form a copper column;

s8: the ultrathin core plate is browned and then pressed, and the flowing pp is filled at the periphery of the copper column;

s9: exposing the top of the copper pillar by polishing;

s10: microetching the pressed board surface and roughening the surface;

s11: and depositing copper on the PP at the top and the periphery of the copper column to manufacture an outer layer circuit.

S12: repeating the steps S3 to S11 to form the multi-layer board.

Further, in step S6, an etching solution is placed to bite the copper layer from the side surface of the copper pillar, thereby forming the copper pillar into a predetermined shape.

Further, the first pattern plating in step S3 is performed by 12ASF for 60 minutes, the thickness of the copper plating is less than or equal to 18 μm, and the overall copper plating tolerance is less than or equal to 4 μm.

Further, the second pattern plating in step S5 is 12ASF × 18 minutes.

Further, the thickness of the dry film in the step S4 is 80 μm to 100 μm.

Further, in step S4, a vacuum laminator is used to attach the dry film to the ultrathin core board.

Further, the thickness of the PP in the step S8 is 80 μm to 100. mu.m.

Further, the step S9 includes:

s91: grinding the top of the copper pillar by adopting a ceramic grinding brush and non-woven fabric;

s92: and performing AOI scanning to detect whether the grinding is complete or not.

Compared with the prior art, the invention has the beneficial effects that: the lamination method of the invention deposits copper on the surface of the ultrathin core board, generates a boss at the designated position by a pattern electroplating mode, plates a solder-resisting tin layer on the top of the boss, etches away the copper outside the boss by etching, then removes the tin layer on the top of the boss to form a copper column, polishes the surface after pressing to expose the top of the copper column, finally deposits copper and manufactures an outer layer circuit, and thus repeatedly forms the lamination board. The lamination method is efficient and reasonable, the copper columns can be rapidly generated, effective conduction among layers is realized, the shape of the copper columns can be controlled through etching, the required special-shaped copper columns can be formed, the reliability of the laminated plate is good, and the production efficiency is high.

Drawings

FIG. 1 is a flow chart of a novel circuit board laminating method of the present invention.

Fig. 2 is a schematic structural diagram of the ultrathin core plate after copper deposition.

FIG. 3 is a schematic structural diagram of a first pattern plating.

Fig. 4 is a schematic structural view of the dry film pasting.

FIG. 5 is a schematic structural diagram of the second pattern plating.

Fig. 6 is a schematic diagram of the structure after etching.

FIG. 7 is a schematic view of the structure after stripping tin.

Fig. 8 is a schematic view of a press-fit structure.

Fig. 9 is a schematic structural diagram after copper deposition.

Figure 10 is a schematic view of the structure of the final multilayer laminate.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

As shown in fig. 1 to 10, in a preferred embodiment, the novel circuit board laminating method of the present invention comprises:

s1: providing an ultrathin core plate 1, cutting the ultrathin core plate 1 according to the design size, and drilling by using a numerical control drilling machine according to engineering data. In the specific implementation, the thickness of the ultrathin core plate 1 is preferably 0.05mm-0.1mm, the thickness of the copper foil is less than or equal to 5 microns, a drill with the thickness of 0.1mm is adopted for drilling, more than 30 thousands of drills are selected, the number of stacked plates is less than or equal to 2, the ultrathin rough-surface aluminum sheet is cut off, and the quick drill is closed.

S2: and (3) copper deposition, wherein a thin copper layer 2 is formed on the surface of the ultrathin core plate 1 by adopting a chemical copper deposition method.

S3: and carrying out primary pattern electroplating on the ultrathin core plate 1, and thickening the copper layer at the designated position to form a boss 3. Wherein, the first pattern plating adopts 12ASF for 60 minutes, the thickness of copper plating is less than or equal to 18 mu m, and the integral copper plating range is less than or equal to 4 mu m. After the pattern electroplating, the photosensitive material is removed by using strong alkaline chemical liquid, and the copper layer 2 is exposed.

S4: and (4) pasting a dry film 4 on the ultrathin core plate 1, wherein the thickness of the dry film 4 is greater than the height of the boss 3. In practice, it is preferable to apply the dry film 4 by a vacuum laminator to prevent the gap between the dry film 4 and the circuit from being too large to cause slight diffusion. The thickness of the dry film 4 is preferably 80 μm to 100 μm, which is advantageous for controlling the thickness of the subsequent pattern plating layer.

S5: and carrying out secondary pattern electroplating on the ultrathin core plate 1, and plating a tin layer 5 on the top of the boss 3. The second pattern electroplating is 12ASF for 18 minutes, and the electroplating time is set to be 18 minutes, so that the thickness of tin plating can be increased, the protection of tin to copper is enhanced, and the tin layer 5 and the copper are prevented from being damaged during subsequent film stripping.

S6: the thin copper layer outside the lands 3 is etched away. During etching, etching liquid can be placed to bite the copper layer from the side surface of the copper column 6, and the copper column 6 can be formed into a preset shape by controlling the using amount of the etching liquid and the etching angle, so that the special-shaped copper column 6 is formed. In practical implementation, the compensation of the copper pillar 6 can be increased according to the etching capability, such as a single side increase of 0.5 mil.

S7: the tin layer 5 on top of the boss 3 is removed to form the copper pillar 6. It should be noted that the tin stripping speed is reduced to two thirds of the ordinary tin stripping speed.

S8: and (3) performing browning and pressing on the ultrathin core plate 1, and filling the flowing pp at the periphery of the copper column 6. Wherein, the thickness of PP is preferably 80-100 μm according to engineering setting.

S9: the top of the copper pillar 6 is exposed by grinding. The method specifically comprises the following steps:

s91: grinding the top of the copper pillar 6 by adopting a ceramic grinding brush and non-woven fabric;

s92: and performing AOI scanning to detect whether the grinding is complete or not.

S10: and the pressed board surface is subjected to microetching, the surface is roughened, subsequent copper deposition is facilitated, and the binding force between the board surface and the copper deposition layer is enhanced.

S11: and depositing copper on the PP at the top and the periphery of the copper column 6 to manufacture an outer layer circuit.

S12: repeating the steps S3 to S11 to form the multi-layer board.

In the description of the present invention, it is to be understood that terms such as "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate orientations or positional relationships, are used based on the orientations or positional relationships shown in the drawings only for the convenience of describing the present invention and for the simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

While the invention has been described in conjunction with the specific embodiments set forth above, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the spirit and scope of the appended claims.

Claims (8)

1. A novel circuit board lamination method is characterized by comprising the following steps,

s1: providing an ultrathin core plate, and cutting and drilling the ultrathin core plate;

s2: depositing copper, and forming a thin copper layer on the surface of the ultrathin core plate;

s3: carrying out first-time pattern electroplating on the ultrathin core plate, and thickening a copper layer at a specified position to form a boss;

s4: carrying out dry film pasting operation on the ultrathin core plate, wherein the thickness of a dry film is larger than the height of the boss;

s5: carrying out secondary pattern electroplating on the ultrathin core plate, and plating a tin layer on the top of the boss;

s6: etching away the thin copper layer outside the boss;

s7: removing the tin layer on the top of the boss to form a copper column;

s8: the ultrathin core plate is browned and then pressed, and the flowing pp is filled at the periphery of the copper column;

s9: exposing the top of the copper pillar by polishing;

s10: microetching the pressed board surface and roughening the surface;

s11: depositing copper on the PP at the top and the periphery of the copper column to manufacture an outer layer circuit;

s12: repeating the steps S3 to S11 to form the multi-layer board.

2. The method of claim 1, wherein the etching solution is disposed in step S6 to bite the copper layer from the side of the copper pillar, thereby forming the copper pillar into a predetermined shape.

3. The method of claim 1, wherein the first pattern plating in step S3 is performed by 12ASF for 60 minutes, the thickness of the copper plating is less than or equal to 18 μm, and the total copper plating tolerance is less than or equal to 4 μm.

4. The method of claim 1, wherein the second pattern plating in step S5 is 12ASF for 18 minutes.

5. The method of claim 1, wherein the thickness of the dry film in step S4 is 80 μm-100 μm.

6. The method of claim 1, wherein step S4 is performed by using a vacuum laminator to attach the dry film to the ultra-thin core board.

7. The method of claim 1, wherein the thickness of PP in step S8 is 80 μm-100 μm.

8. The method of claim 1, wherein the step S9 includes:

s91: grinding the top of the copper pillar by adopting a ceramic grinding brush and non-woven fabric;

s92: and performing AOI scanning to detect whether the grinding is complete or not.

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