JP2016225443A - Manufacturing method of printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a printed wiring board which achieves high productivity.SOLUTION: In a manufacturing method of a printed wiring board according to an embodiment, a peeling layer 40 is provided on a first surface F of a core substrate 30 and then a build-up layer 55F, which is formed by laminating a resin insulation layer and a conductor layer, is formed on the first surface of the core substrate and the peeling layer. A cavity 26 which exposes a copper foil 48 is formed from a second surface side of the core substrate. The manufacturing method enables easy formation of the cavity, achieves high productivity, and reduces the production cost.SELECTED DRAWING: Figure 1

Description

The present invention relates to a printed wiring board having a cavity for exposing a mounting area.

Patent Document 1 discloses an electronic component built-in substrate in FIG. The electronic component built-in substrate of Patent Document 1 includes a coreless substrate and a resin layer. A through hole and a through via for accommodating the semiconductor chip are formed in the resin layer.

JP 2007-123524 A

The electronic component built-in substrate disclosed in Patent Document 1 is formed of a resin layer having a coreless substrate and a housing portion for housing a semiconductor chip. Therefore, it is considered that the strength and rigidity of the electronic component built-in substrate is low. When the electronic component built-in substrate becomes hot due to reflow or the like, the warpage is expected to be large.

Here, it is conceivable to provide an opening in a core substrate having a core material and having a high rigidity to accommodate an electronic component. However, after forming the build-up layer, it is difficult to process the opening, which may increase the manufacturing cost.

The method for manufacturing a printed wiring board according to the present invention includes preparing a core substrate having a first surface and a second surface opposite to the first surface and including a core material; and a first surface of the core substrate. Providing a release layer, temporarily bonding the second surface of the core substrate toward the surface of the resin film, a resin insulating layer and a conductor layer on the first surface of the core substrate and the release layer, Forming a buildup layer formed by laminating, separating the core substrate from the resin film, and forming a cavity exposing the release layer from the second surface side of the core substrate; Removing the release layer.

In the printed wiring board manufacturing method of the embodiment, since a core substrate having a core material and high rigidity is used, the warpage of the printed wiring board can be reduced. Also, a release layer is provided on the first surface of the core substrate, and a buildup layer formed by laminating a resin insulating layer and a conductor layer on the first surface and the release layer of the core substrate is formed. A cavity exposing the release layer is formed from the second surface side of the core substrate. Since the release layer is formed in advance, the formation of the cavity is easy, the productivity is high, and the production cost can be suppressed.

In a preferred embodiment, a metal film serving as a stopper for forming a cavity is formed on the first surface of the core substrate on the outer periphery of the release layer forming position. By applying a laser along the metal film, the cavity can be easily formed.

In a preferred embodiment, a notch for forming a cavity is formed in advance from the second surface side of the core substrate. And after separating a core substrate from the said resin film, the cavity which exposes a peeling layer from the 2nd surface side of a core substrate is formed by penetrating the said notch to the 2nd surface. A cavity can be easily formed.

FIG. 1A is a cross-sectional view of a printed wiring board according to an embodiment of the present invention, and FIG. 1B is a plan view showing a first circuit board and a mounting area exposed from the opening of the first circuit board. . Sectional drawing of the application example of the printed wiring board which concerns on embodiment. Process drawing which shows the manufacturing method of the printed wiring board of 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board of 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board of 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board of 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board of 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board of 2nd Embodiment. Process drawing which shows the manufacturing method of the printed wiring board of 2nd Embodiment.

[First embodiment]
FIG. 1A shows a printed wiring board 10 of the first embodiment. The printed wiring board 10 of the first embodiment includes a first circuit board 130 having a first surface S and a second surface F opposite to the first surface, a third surface V, and a fourth surface opposite to the third surface. A second circuit board 155 having a surface W;

The second circuit board 155 shown in FIG. 1A is formed of a buildup layer 55F composed of conductor layers 58F and 158F and resin insulating layers 50F and 150F that are alternately stacked. The second circuit board 155 is stacked on the second surface F of the first circuit board 130. The third surface V of the second circuit board is in contact with the second surface F of the first circuit board.
The resin insulating layer of the second circuit board is made of resin and inorganic particles. Further, the resin insulating layers 50F and 150F may include a reinforcing member such as a glass cloth. Since the resin insulating layers 50F and 150F include the reinforcing member, cracks in the second circuit board are suppressed.
Each resin insulation layer has openings 68F and 168F for via conductors, and each opening is tapered from the fourth surface W side to the third surface V side.
Via conductors 60F and 160F are formed in the openings 68F and 168F of the respective resin insulation layers. The side wall of each via conductor is tapered from the fourth surface W side toward the third surface V side. Adjacent conductor layers are connected by via conductors.
The second circuit board 155 has a mounting area SMF shown in FIG. An X1-X1 cross section in FIG. 1B corresponds to FIG. The mounting area is exposed through the opening 26 of the first circuit board. An electronic component such as an IC chip is mounted on the mounting area.

A first circuit board 130 shown in FIG. 1A has a core board 30. The core substrate is formed of an insulating substrate 20z including a resin and a core material (reinforcing member), a first conductor layer 34S, a second conductor layer 34F, and a through-hole conductor 36. The insulating substrate has a first surface S and a second surface F opposite to the first surface S. The first surface of the insulating substrate and the first surface of the core substrate are the same surface, and the second surface of the insulating substrate and the second surface of the core substrate are the same surface. The insulating substrate may further contain inorganic particles. The first conductor layer 34S is formed on the first surface, and the second conductor layer 34F is formed on the second surface. The first conductor layer and the second conductor layer are connected by a through-hole conductor. The first circuit board further has an opening 26 for exposing the mounting area SMF of the second circuit board. In FIG. 1A, the printed wiring board does not have a conductor layer on the first conductor layer. In that case, the first conductor layer is the uppermost conductor layer.

As shown in FIG. 1A, a first resin insulating layer 50F is formed on the second surface F of the first circuit board 130 and the second conductor layer 34F. Openings 68F (68FI, 68FO) for via conductors 60F (60FI, 60FO) penetrating the resin insulating layer 50F are formed in the first resin insulating layer 50F.
A conductor layer 58F in the second circuit board is formed on the first resin insulation layer 50F.
A via conductor 60F is formed in the opening 68F for the via conductor 60F. The via conductor 60F includes a connection via conductor 60FO connecting the conductor layer (conductor layer in the second circuit board) 58F and the second conductor layer 34F, and a mounting via conductor 60FI for mounting electronic components. The connecting via conductor 60FO is preferably connected directly to the land 36L of the through-hole conductor in the first circuit board. The land 36L is formed of a conductor covering the through-hole conductor and a conductor around the through-hole conductor, and is included in the second conductor layer 34F.
The mounting via conductor is formed in the mounting area SMF. The mounting via conductor 60FI is formed in the opening 68FI for the via conductor of the first resin insulating layer 50F. The bottom (C4 pad) 73SI of the mounting via conductor 60FI is exposed through the opening 68FI. The C4 pad 73SI is exposed through the opening 26 of the first circuit board. The bottom (C4 pad) of the mounting via conductor is exposed through the opening 26 and the opening 68FI.
The connection via conductor 60FO is formed in the opening 68FO of the first resin insulation layer 50F. The bottom 60FB of the connection via conductor 60FO is directly connected to the land 36L of the through-hole conductor.

As shown in FIG. 1A, the bottom of the mounting via conductor 60FI that penetrates the resin insulating layer (first resin insulating layer) 50F is exposed and functions as the first pad (C4 pad) 73SI. . The first pad is formed in the mounting area of the second circuit board. Solder bumps 76SI (see FIG. 2A) for connecting to electronic components can be formed on the first pads 73SI.

In the printed wiring board of the first embodiment, the via conductor opening tapers from the lower surface of the resin insulating layer toward the upper surface of the resin insulating layer. Therefore, the pad size can be further reduced. The pitch of the first pad can be further reduced. The size of the printed wiring board is reduced. High-performance electronic components can be mounted on a printed wiring board.

As shown in FIG. 1A, a second resin insulation layer 150F is formed on the first resin insulation layer 50F and the conductor layer 58F. An opening 168F for the second via conductor 160F that penetrates the resin insulating layer 150F is formed in the second resin insulating layer 150F.
A second conductor layer 158F in the second circuit board is formed on the second resin insulation layer 150F.
A second via conductor 160F is formed in the opening 168F for the second via conductor 160F. The second via conductor 160F connects the conductor layer (second conductor layer in the second circuit board) 158F and the conductor layer 58F.

The printed wiring board can have a solder resist layer 70F on the buildup layer on the resin insulating layer (lowermost resin insulating layer) 150F and the conductor layer (lowermost conductor layer) 158F of the second circuit board. An opening 71F that exposes the conductor layer (lowermost conductor layer) 158F is formed in the solder resist layer 70F on the buildup layer. The conductor layer 158F exposed through the opening 71F functions as a pad 73F connected to the motherboard.
A protective film 72 can be formed on the pad 73F. The protective film is a film for preventing the pad from being oxidized. The protective film is formed of, for example, Ni / Au, Ni / Pd / Au, Pd / Au, or OSP (Organic Solderability Preservative) film.
A protective film can be formed on the bottom (C4 pad) of the mounting via conductor 60FI.

As shown in FIG. 3B, the through hole 28 has a first opening 28S having a first opening 28SO on the first surface S of the insulating substrate 20z and a second opening having a second opening 28FO on the second surface F. A portion 28F is formed. The first opening 28S is preferably tapered from the first surface toward the second surface. The second opening 28F is preferably tapered from the second surface toward the first surface. A through-hole conductor 36 is formed in the through hole 28 having such a shape. The through-hole conductor 36 shown in FIG. 1 (A) may be manufactured by the method disclosed in US77786390, for example.

The insulating substrate 20z is formed of a reinforcing member and resin. The insulating substrate 20z may further contain inorganic particles. Examples of the reinforcing member are glass fiber, glass cloth, and aramid fiber. Examples of inorganic particles are silica and alumina.

The printed wiring board may have a solder resist layer 70S on the first surface S of the first circuit board 130 and the first conductor layer 34S. An opening 71S that exposes the first conductor layer 34S is formed in the upper solder resist layer 70S. The first conductor layer 34S exposed through the opening 71S functions as a pad (second pad) 73S for mounting the second package substrate 230. A protective film 72 can be formed on the second pad. The second package substrate 230 is shown in FIG.

FIG. 2A shows a first application example 120 of the printed wiring board 10 of the first embodiment. The first application example 120 is a package substrate (first package substrate).
In the package substrate 120, an electronic component 90 such as an IC chip is accommodated in the opening 26 of the first circuit substrate 130. The IC chip 90 is mounted on the C4 pad 73SI exposed from the opening 26 by solder bumps 76SI.

FIG. 2B shows a second application example (POP substrate) 200 of the printed wiring board 10 of the first embodiment. In the second application example, the second package substrate 230 is mounted on the first package substrate 120 via the connecting body 76SO. The second package substrate 230 includes an upper substrate 210 and an electronic component 190 such as a memory mounted on the upper substrate. The connecting body 76SO is formed on the second conductor layer (second pad) 73S exposed through the opening 71S of the upper solder resist layer 70S. In FIG. 2B, the connecting body 76SO is a solder bump 76SO. An example of the connection body other than the solder bump is a metal post (not shown) such as a plating post or a pin. The shape of the plating posts and pins is a cylinder. A right circular cylinder is preferable.
A mold resin 102 for sealing the IC chip is formed in the cavity 26 of the first package substrate 120. A mold resin 202 for sealing the electronic component 190 is formed on the upper substrate 210.

The first circuit board can have a resin insulating layer and a conductor layer alternately stacked on the first surface of the insulating substrate 20z and the first conductor layer. In that case, the upper solder resist layer 70S is formed on the resin insulating layer and the conductor layer. In that case, the conductor layer directly below the upper solder resist layer 70S is the uppermost conductor layer.

The printed wiring board 10 may have solder bumps 76F for connecting to the mother board on the pads 73F exposed from the openings 71F of the solder resist layer 70F on the buildup layer.

In the printed wiring board of the embodiment, an opening 26 for accommodating electronic components is formed in the insulating substrate 20z. If the second circuit board is formed on both surfaces of the first circuit board, a symmetrical structure is obtained with the first circuit board as the center. Therefore, the stress acting on the contact CM is small. However, in the printed wiring board of the embodiment, the second circuit board is formed only on the second surface of the first circuit board. Therefore, in order to avoid stress concentration, the recess 55Ff can be formed in the printed wiring board of the embodiment. The recess 55Ff is a space formed between the first circuit board 130 and the second circuit board 155 and is connected to the opening 26. The upper surface of the recess is the second surface of the first circuit board. The lower surface of the recess is the third surface of the second circuit board. The side wall 55fw of the recess is a side surface of the first resin insulating layer 50F in contact with the first circuit board. The side wall 55fw of the recess 55Ff is set back from the side wall 26W of the insulating substrate 20z exposed by the opening 26. Due to the recess 55Ff, the corner portion 26E of the first circuit board 130 having high rigidity does not contact the second circuit board. Even if the stress caused by the thermal contraction is concentrated on the corner portion 26E, the stress does not reach the second circuit board from the corner portion. Cracks are unlikely to occur in the second circuit board. The reliability of the printed wiring board having the recess 55Ff does not deteriorate. In the printed wiring board of the first embodiment, the third surface V of the second circuit board exposed from the opening 26 may be recessed from the second surface of the first circuit board. In that case, the surface (mounting area) SMF exposed from the opening 26 is located below the second surface of the first circuit board. The lower surface of the recess 55Ff (the upper surface of the first resin insulating layer 50F in the recess) is connected to the surface (mounting area) SMF exposed from the opening 26.

The insulating substrate 20z constituting the first circuit board 130 is formed by laminating a prepreg in which a core material is impregnated with a resin. Examples of the core material are glass cloth, glass fiber, and aramid fiber. Examples of the resin are an epoxy resin and a BT (bismaleimide triazine) resin. The resin insulating layers 50F and 150F constituting the buildup layer 55F do not contain a core material but are made of a resin containing an inorganic filler. Examples of the resin are resins mainly composed of an epoxy resin or a BT (bismaleimide triazine) resin. Examples of the inorganic filler include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds. Further, silica, alumina, dolomite and the like can be mentioned.

Since the printed wiring board of the first embodiment includes the core material and uses the highly rigid insulating substrate 20z, the warp of the printed wiring board can be reduced.

[Method for Manufacturing Printed Wiring Board of First Embodiment]
The manufacturing method of the printed wiring board 10 of 1st Embodiment is shown by FIGS.
A double-sided copper-clad laminate as a starting substrate is prepared. The starting substrate is formed of copper foils 22S and 22F laminated on both surfaces of the insulating substrate 20z and the insulating substrate 20z (FIG. 3A). The insulating substrate includes a reinforcing member, a resin, and inorganic particles. Examples of the reinforcing member are glass cloth, glass fiber, and aramid fiber. Examples of the resin are an epoxy resin and a BT (bismaleimide triazine) resin.
The insulating substrate has a first surface S and a second surface F opposite to the first surface. The copper foil 22S laminated on the first surface S of the insulating substrate is a first copper foil, and the copper foil 22F laminated on the second surface F of the insulating substrate is a second copper foil.

The first copper foil 22S of the starting substrate is irradiated with a CO2 laser. A first opening 28S is formed on the first surface S side of the insulating substrate 20z. Further, the second copper foil 22F is irradiated with a CO2 laser. A second opening 28F connected to the first opening 28S is formed on the second surface F side. A connecting portion 28M is formed at the intersection of the side wall of the first opening and the side wall of the second opening. The laser is irradiated so that the axis LL1 of the first opening coincides with the axis LL2 of the second opening. A through hole 28 for the through hole conductor is formed (FIG. 3B). The first opening is tapered from the first surface S toward the second surface F. The second opening is tapered from the second surface F toward the first surface S. The first opening has a first opening 28SO on the first surface, and the second opening has a second opening 28FO on the second surface.

An electroless plating film is formed on the side walls of the first copper foil, the second copper foil, and the through hole 28. A plating resist film is formed on the electroless plating film, and then a through-hole conductor 36 and a pattern are formed in the through hole 28 by electrolytic plating. Strip the plating resist film. The electroless plating film below the plating resist film and the copper foils 22F and 22S are removed with an etching solution. Thereby, the first conductor layer 34S is formed on the first surface of the insulating substrate. A second conductor layer 34F is formed on the second surface of the insulating substrate. The second conductor layer 34F includes a dummy pattern 34FI for forming the opening 26. A through-hole conductor 36 that connects the first conductor layer and the second conductor layer is formed in the through hole 28. The through-hole conductor has the thinnest portion in the through hole connecting portion 28M. An insulating substrate having a through hole 28, a through hole conductor 36 formed in the through hole 28, a first conductor layer 34S formed on the first surface of the insulating substrate, and a second surface of the insulating substrate. The intermediate body 300 having the second conductor layer 34F is obtained (FIG. 3C).

A plan view of the intermediate body 300 is shown in FIG. FIG. 1C is a plan view obtained by observing the intermediate from the second conductor layer side. FIG. 1C shows the second conductor layer and the second surface F of the insulating substrate 20z exposed from the second conductor layer. A dummy pattern 34FI, which is an example of the metal film of the present invention, is formed at substantially the center of the second surface of the insulating substrate. The dummy pattern 34FI covers a predetermined region on the second surface of the insulating substrate 20z. The dummy pattern 34FI is a rectangular frame-shaped solid pattern. A land 36L of the through-hole conductor 36 is shown around the dummy pattern. FIG. 1D shows the positional relationship between the opening 26 and the dummy pattern 34FI and the size of both. The outer periphery of the dummy pattern 34FI is indicated by a solid line, and the outer periphery of the opening 26 is indicated by a dotted line. The dotted line indicates the outer periphery of the opening 26 formed on the dummy pattern. As shown in FIG. 1D, the outer periphery of the dummy pattern 34FI is located outside the opening 26, and the inner periphery of the dummy pattern 34FI is located inside the opening 26.

On the second surface F of the intermediate body 300, the peeling layer 40 and the copper foil 48 are provided in the frame-like dummy pattern 34FI. The release layer 40 is formed by laminating release films 44 and 44 on both sides of a polyimide film 42 (FIG. 3D).

The intermediate body 300 is temporarily bonded to both surfaces of the temporary bonding resin film 80 so that the first surface S side of the intermediate body 300 faces the surface of the temporary bonding resin film 80 (FIG. 4A). The temporary adhesion resin film 80 is formed by laminating a polyimide layer 84 on both sides of a polypropylene layer 82.

A resin insulation layer (first resin insulation layer) 50F is formed on the second surface F of the intermediate body, and the second intermediate body 400 is completed (FIG. 4B). The upper solder resist layer 70S and the first resin insulating layer 50F are of a thermosetting type. The resin insulating layer 50F includes a resin such as epoxy and inorganic particles such as silica.

Next, via conductor openings 68F (68FI, 68FO) reaching the second conductor layer 34F are formed in the first resin insulation layer 50F (FIG. 4C). The via conductor opening 68F has an opening 68FI reaching the copper foil 48 and an opening 68FO reaching the second conductor layer other than the dummy pattern. The opening 68FI is an opening for forming a mounting via conductor. The opening 68FO is an opening for forming a connection via conductor. The opening 68FO reaches, for example, a land 36L of a through-hole conductor. The land of the through-hole conductor is formed by a conductor formed immediately above the through-hole conductor and a conductor formed around the through-hole conductor.

The conductor layer 58F is formed on the first resin insulation layer 50F by a semi-additive method. At the same time, a via conductor 60F is formed in the opening 68F (FIG. 5A). A via conductor (connection via conductor) 60FO connected to the through-hole conductor is formed in the opening 68FO. A via conductor (mounting via conductor) 60FI for forming a C4 pad is formed in the opening 68FI. The via conductor 60F has a bottom. The bottom of the connection via conductor is in contact with the land 36L of the through-hole conductor.
The bottom of the mounting via conductor is formed on the copper foil 48. The bottom of the mounting via conductor is in contact with the copper foil 48.

A metal film can be formed on the copper foil 48 exposed from the opening 68FI. The metal film functions as a C4 pad. The metal film is formed of a metal other than copper, and the metal film prevents oxidation of the C4 pad (first pad). Examples of metal films are gold, palladium, and tin. Nickel can be formed between the metal film and the C4 pad.

A second resin insulation layer 150F is formed on the first resin insulation layer 50F and the conductor layer 58F by a hot press. An opening 168F for the second via conductor is formed in the second resin insulation layer 150F. The second resin insulation layer 150F is a thermosetting type.
Conductive layer (158F) is formed on second resin insulation layer (150F). At the same time, the second via conductor 160F is formed in the opening for the second via conductor. The conductor layer 158F and the via conductor 160F are formed by a semi-additive method.

A solder resist layer 70F on the build-up layer is formed on the second resin insulating layer 150F and the conductor layer 158F (FIG. 5B). The solder resist layer 70F on the buildup layer is a thermosetting type.

It peels from the resin film 80 for temporary adhesion, and is divided | segmented into the separate 3rd intermediate body 500 (FIG. 6 (A)). A solder resist layer 70S on the insulating substrate is formed on the first surface S on the first surface S side of the insulating substrate 20z (FIG. 6B).

The slit 88 reaching the frame-shaped dummy pattern 34FI described above with reference to FIG. 1D is formed by laser so as to penetrate the solder resist layer 70S and the insulating substrate 20z (FIG. 6C).

The solder resist layer 70S and the insulating substrate 20z separated by the slit 88 are separated together with the release layer 40, and the copper foil 48 is exposed (FIG. 7A).

The copper foil 48 and the dummy pattern 34FI exposed from the opening 26 are removed by etching. The bottom of the via conductor 60FI forming the C4 pad is exposed through the opening 26 (FIG. 7B).

In the embodiment, the size of the dummy pattern 34FI is larger than the size of the opening 26. Then, the dummy pattern between the first circuit board 130 and the second circuit board 155 is removed. Therefore, as shown in FIG. 7C, the mounting area is recessed from the second surface of the first circuit board. Further, a space (concave portion) 55Ff is formed between the first circuit board and the second circuit board.

An opening 71S exposing the pad 73S is formed in the upper solder resist layer 70S by the laser.
An opening 71F exposing the pad 73F is formed in the solder resist layer 70F on the lower buildup layer by a laser (FIG. 7C).

A protective film 72 is formed on the pads 73F and 73S and the C4 pad 73SI (FIG. 1). The protective film is a film for preventing the pad from being oxidized. The protective film is formed of, for example, Ni / Au, Ni / Pd / Au, Pd / Au, or OSP (Organic Solderability Preservative) film. The protective film on the C4 pad is not drawn.

Solder bumps 76F, 76SI, and 76SO may be formed on the pads 73F, 73SI, and 73S.

Each of the resin insulating layers 50F and 150F has an upper surface and a lower surface opposite to the upper surface. The upper surface of each resin insulating layer is a surface close to the first circuit board 130, and the lower surface of each resin insulating layer is a surface close to the solder resist layer 70F on the lower buildup layer. The via conductor openings 68F and 168F formed in each resin insulating layer taper from the lower surface to the upper surface. The side walls of the via conductors 60F and 160F formed in the via conductor openings are also tapered from the lower surface to the upper surface.

Each of the conductor layers 58F and 158F and the via conductors 60F and 160F are formed of the electroless copper plating film 52 and the electrolytic copper plating film 56 on the electroless copper plating film (see FIG. 5A).

IC chip 90 is mounted on the printed wiring board via solder bumps 76SI on C4 pad 73SI. A first package substrate (first application example) is completed (FIG. 2A). The IC chip is accommodated in the opening. The IC chip does not protrude from the opening 26. The second package substrate 230 is mounted on the first package substrate 120 through the solder bumps 76SO (FIG. 2B). The POP substrate (second application example) 200 is completed.

A mounting via conductor formed of seed layer 52 and electrolytic copper plating film 56 is formed on copper foil 48 exposed from opening 68FI. A metal film can be formed between the copper foil 48 and the seed layer. By removing only the copper foil 48, the bottom of the mounting via conductor 60FI is exposed. The bottom of the mounting via conductor formed of the seed layer and the third surface of the first resin insulating layer 50F are located on the same plane. The bottom of the mounting via conductor formed of the metal film and the third surface of the first resin insulating layer 50F are located on the same plane.

In the first embodiment, a release layer 40 is provided on the second surface F of the core substrate 30, and a buildup layer 55F formed by laminating a resin insulating layer and a conductor layer on the second surface of the core substrate and the release layer is formed. Is done. A cavity that exposes the copper foil 48 is formed from the second surface side of the core substrate. Since the release layer is formed in advance, the formation of the cavity is easy, the productivity is high, and the production cost can be suppressed.

In the first embodiment, a metal film frame (dummy pattern) 34FI serving as a stopper at the time of forming a cavity is formed on the first surface of the core substrate on the outer periphery of the position where the release layer 40 is formed. By applying a laser along the metal film, the cavity can be easily formed.

[Method for Manufacturing Printed Wiring Board of Second Embodiment]
8 and 9 show a method for manufacturing a printed wiring board according to the second embodiment.
An intermediate 300 is obtained through the same steps as those in the first embodiment (FIG. 8A). A rectangular slit 86 is formed by a laser from the first surface S side of the insulating substrate 20z (FIG. 8B). The slit is formed so as not to penetrate the insulating substrate.

The peeling layer 40 and the copper foil 48 are provided at positions corresponding to the slits 86 on the second surface F of the insulating substrate 20z, and the intermediate body 300 is completed. The release layer 40 is formed by laminating release films 44 and 44 on both sides of a polyimide film 42 (FIG. 8C).

Similarly to the first embodiment, the intermediate body 300 is temporarily bonded to both surfaces of the temporary adhesion resin film to form the buildup layer 55F, and then peeled off from the temporary adhesion resin film (FIG. 9A). .

A mechanical impact is applied to the insulating substrate 20z by the trim puncher 85 having a shape corresponding to the rectangular slit 86 (FIG. 9B), and the solder resist layer 70S and the insulating substrate 20z separated by the slit 86 are peeled off. Separated with the layer 40, the copper foil 48 is exposed (FIG. 9C).

The copper foil 48 exposed from the opening 26 is removed by etching. The bottom of the via conductor 60FI forming the C4 pad is exposed through the opening 26 (FIG. 9D). The subsequent steps are the same as in the first embodiment.

In the second embodiment, a notch (slit) 86 for forming a cavity is formed in advance from the second surface S side of the core substrate 30. An impact is applied from the cut, and the cavity 26 is formed to expose the copper foil 48 from the second surface side of the core substrate 30. A cavity can be easily formed. The second embodiment has an advantage that it is easier to manufacture than the first embodiment.

DESCRIPTION OF SYMBOLS 10 Printed wiring board 26 Opening 34FI Dummy pattern 36 Through-hole conductor 40 Peeling layer 48 Copper foil 50F Resin insulating layer 58F Conductor layer 60F Via conductor 80 Temporary adhesion resin film 90 IC chip 130 1st circuit board 155 2nd circuit board

Claims (6)

A method of manufacturing a printed wiring board,
Preparing a core substrate having a first surface and a second surface opposite to the first surface, and comprising a core;
Providing a release layer on the second surface of the core substrate;
Temporarily adhering the first surface of the core substrate toward the surface of the resin film;
Forming a buildup layer formed by laminating a resin insulation layer and a conductor layer on the second surface of the core substrate and the release layer;
Separating the core substrate from the resin film;
Forming a cavity exposing the release layer from the first surface side of the core substrate;
Removing the release layer. The method for manufacturing a printed wiring board according to claim 1, further comprising:
Forming a metal film on the second surface of the core substrate as a stopper when forming a cavity on the outer periphery of the formation position of the release layer;
Forming the cavity includes forming a break from the first surface side of the core substrate to the metal film with a laser. The method for manufacturing a printed wiring board according to claim 1, further comprising:
Forming the cavity includes forming a cut from the first surface side of the core substrate between the first surface and the second surface before separating the core substrate from the resin film; and Penetrating the notch to the second surface after separating the substrate from the resin film. The method for manufacturing a printed wiring board according to claim 1, further comprising:
Laminating a metal foil on the release layer; and removing the metal foil exposed from the cavity after removing the release film. The method of manufacturing a printed wiring board according to claim 4, further comprising:
Forming a via conductor connecting the conductor layer in the build-up layer and the metal foil, and forming a mounting pad by exposing a bottom portion of the via conductor from the cavity. It is a manufacturing method of the printed wiring board of Claim 3, Comprising:
Penetrating the notch to the second surface is performed by punching.

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