JP2010021274A - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
JP2010021274A
JP2010021274A JP2008179207A JP2008179207A JP2010021274A JP 2010021274 A JP2010021274 A JP 2010021274A JP 2008179207 A JP2008179207 A JP 2008179207A JP 2008179207 A JP2008179207 A JP 2008179207A JP 2010021274 A JP2010021274 A JP 2010021274A
Authority
JP
Japan
Prior art keywords
type gaas
gaas
chip
layer
metal electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008179207A
Other languages
English (en)
Inventor
Satoshi Suzuki
敏 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2008179207A priority Critical patent/JP2010021274A/ja
Priority to US12/260,494 priority patent/US7719087B2/en
Publication of JP2010021274A publication Critical patent/JP2010021274A/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3185Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/564Details not otherwise provided for, e.g. protection against moisture
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10329Gallium arsenide [GaAs]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12036PN diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

【課題】GaAsチップの耐湿性を向上させることができる半導体装置を得る。
【解決手段】GaAsチップ14は樹脂26で封止されている。GaAsチップ14は、p型GaAsベース層34(p型GaAs層)と、その上に形成されたn型GaAsエミッタ層36(n型GaAs層)を有する。GaAsチップ14の外周部においてn型GaAsエミッタ層36上に金属電極18が形成されている。この金属電極18には正電圧が印加される。GaAsチップ14の中央部に形成された素子領域20と金属電極18との間において、p型GaAsベース層34とn型GaAsエミッタ層36に半絶縁性領域38が形成されている。半絶縁性領域38よりも外側において、p型GaAsベース層34と金属電極18は接続部40により電気的に接続されている。
【選択図】図3

Description

本発明は、GaAsチップを樹脂で封止した半導体装置に関し、特にGaAsチップの耐湿性を向上させることができる半導体装置に関するものである。
半導体チップを樹脂で封止した樹脂封止型の半導体装置が提案されている(例えば、特許文献1参照)。例えば、半導体チップとしてGaAsチップが用いられ、GaAsチップの外周部に電極が形成され、GaAsチップの中央部に素子領域が形成される。
特開昭60−167432号公報
このような樹脂封止型の半導体装置は、高温多湿の環境下において、樹脂の表面や、GaAsチップが実装されたプリント回路基板と樹脂の境界から水分が浸入しやすい。この水分が原因となって、正電圧が印加される金属電極や素子領域の周辺においてGaAsチップの表面が酸化され、素子が劣化故障するという問題があった。
本発明は、上述のような課題を解決するためになされたもので、その目的は、GaAsチップの耐湿性を向上させることができる半導体装置を得るものである。
本発明は、GaAsチップを樹脂で封止した半導体装置であって、前記GaAsチップは、p型GaAs層と、前記p型GaAs層上に形成されたn型GaAs層と、前記GaAsチップの外周部において前記n型GaAs層上に形成され、正電圧が印加される金属電極と、前記GaAsチップの中央部に形成された素子領域と、前記金属電極と前記素子領域との間において前記p型GaAs層と前記n型GaAs層に形成された半絶縁性領域と、前記半絶縁性領域よりも外側において、前記p型GaAs層と前記金属電極とを電気的に接続する接続部とを有することを特徴とする半導体装置である。
本発明により、GaAsチップの耐湿性を向上させることができる。
実施の形態1.
図1は本発明の実施の形態1に係る半導体装置の内部を示す平面図であり、図2は図1のA−A´における断面図である。
樹脂製又はセラミック製のプリント回路基板10上に、接地されたダイパッド12が設けられている。増幅器などが形成されたGaAsチップ14が、導電性の接着剤16によりダイパッド12上に実装されている。GaAsチップ14の外周部に金属電極18が形成され、GaAsチップ14の中央部に、配線や半導体素子などを有する素子領域20が形成されている。
プリント回路基板10の表層に設けられた電気回路22とGaAsチップ14の金属電極18は金属ワイヤ24により接続されている。GaAsチップ14は樹脂26で封止されている。なお、チップ面積を削減するため、チップ外周部まで金属電極18や素子領域20を配置している。領域28は、GaAsチップ14表面の酸化を防ぎたい領域である。
図3は図2のチップ端部を示す拡大断面図である。GaAsチップ14は、半絶縁性GaAs基板30上に、n型GaAsコレクタ層32、p型GaAsベース層34(p型GaAs層)及びn型GaAsエミッタ層36(n型GaAs層)が順番に形成されたnpn型バイポーラトランジスタを有する。なお、n型GaAsコレクタ層32、p型GaAsベース層34及びn型GaAsエミッタ層36は、エピタキシャル成長により形成してもよいし、イオン注入により形成してもよい。
GaAsチップ14の外周部においてn型GaAsエミッタ層36上に金属電極18が形成されている。この金属電極18には金属ワイヤ24を介して正電圧が印加される。GaAsチップ14の中央部に形成された素子領域20と金属電極18との間において、イオン注入によりn型GaAsコレクタ層32とp型GaAsベース層34とn型GaAsエミッタ層36に半絶縁性領域38が形成されている。
本実施の形態では、半絶縁性領域38よりも外側において、p型GaAsベース層34と金属電極18は、n型GaAsエミッタ層36を貫通する接続部40により電気的に接続されている。
次に、本実施の形態に係る半導体装置の効果について、図4に示す比較例と比較しながら説明する。比較例には、本実施の形態のような接続部40は設けられていない。
高温多湿の環境下において、樹脂26の表面や、樹脂26とプリント回路基板10の境界から浸入した水分は、不純物を含んだ溶媒となる。このため、接地されたダイパッド12では、水分の電離による以下の陰極反応が起こると考えられる。
+2HO+4e → 4OH
また、金属電極18や素子領域20内の配線に用いられるAuなどの金属材料に比べ、GaAsの方が電位的に卑である。このため、比較例の場合、正電圧を印加された金属電極18や素子領域20付近のGaAsチップ14表面で、以下の陽極反応が起こると考えられる。
GaAs+6h → Ga3++As3+
そして、ダイパッド12で発生したOHは、金属電極18付近のGaAs表面に容易に到達し、陽極反応で生成されたGa3+やAs3+と反応して酸化物42(又は水酸化物)になる。これにより、比較例では、体積膨張による素子構造の破壊や、電流リークパスの形成などの劣化現象が発生する。
一方、本実施の形態では、半絶縁性領域38よりも外側において、p型GaAsベース層34と金属電極18は接続部40により電気的に接続されている。そして、正電圧が印加されたp型GaAsベース層34は、溶媒との間の電位障壁は引き下げられて陽極反応が容易に進む。しかし、正電圧が印加されたn型GaAsエミッタ層36は、溶媒との間の電位障壁が引き上げられて陽極反応が容易には進まない。このため、ダイパッド12を接地し、金属電極18に正電圧を印加した場合、GaAsチップ14の側面のp型GaAsベース層34において陽極反応、ダイパッド12において陰極反応が起こる。このようにGaAsチップ14の側面が優先的に酸化されるため、正電圧が印加される金属電極18や素子領域20の周辺においてGaAsチップ14の表面が酸化されるのを防ぐことができる。よって、素子の劣化故障を抑制して、GaAsチップの耐湿性を向上させることができる。
実施の形態2.
図5は本発明の実施の形態2に係る半導体装置の内部を示す平面図である。そして、図6は図5のB−B´における断面図、図7は図6のチップ端部を示す拡大断面図である。実施の形態1と同じ構成要素には同じ番号を付し、説明を省略する。
半絶縁性領域38よりも外側においてn型GaAsエミッタ層36がエッチング除去され、p型GaAsベース層34上にn型GaAsエミッタ層36が存在しない切り欠き部44が形成されている。これにより、p型GaAsベース層34の露出面積が広がってp型GaAsベース層34における陽極反応をより起こり易くすることができるため、GaAsチップ14の表面が酸化されるのを更に効果的に防ぐことができる。
なお、実施の形態1,2では、陽極反応を発生させるp型GaAs層として、npn型バイポーラトランジスタのp型GaAsベース層34を用いた。これに限らず、n型電界効果トランジスタの場合は、n型GaAsチャネル層の下に設けたp型GaAs層を用いてもよい。また、pn接合発光ダイオードやレーザーの場合は、p型GaAsコンタクト層やp型GaAsクラッド層を用いてもよい。
本発明の実施の形態1に係る半導体装置の内部を示す平面図である。 図1のA−A´における断面図である。 図2のチップ端部を示す拡大断面図である。 半導体装置の比較例を示す拡大断面図である。 本発明の実施の形態2に係る半導体装置の内部を示す平面図である。 図5のB−B´における断面図である。 図6のチップ端部を示す拡大断面図である。
符号の説明
14 GaAsチップ
18 金属電極
20 素子領域
26 樹脂
34 p型GaAsベース層(p型GaAs層)
36 n型GaAsエミッタ層(n型GaAs層)
38 半絶縁性領域
40 接続部
44 切り欠き部

Claims (2)

  1. GaAsチップを樹脂で封止した半導体装置であって、
    前記GaAsチップは、
    p型GaAs層と、
    前記p型GaAs層上に形成されたn型GaAs層と、
    前記GaAsチップの外周部において前記n型GaAs層上に形成され、正電圧が印加される金属電極と、
    前記GaAsチップの中央部に形成された素子領域と、
    前記金属電極と前記素子領域との間において前記p型GaAs層と前記n型GaAs層に形成された半絶縁性領域と、
    前記半絶縁性領域よりも外側において、前記p型GaAs層と前記金属電極とを電気的に接続する接続部とを有することを特徴とする半導体装置。
  2. 前記半絶縁性領域よりも外側において、前記p型GaAs層上に前記n型GaAs層が存在しない切り欠き部が形成されていることを特徴とする請求項1に記載の半導体装置。
JP2008179207A 2008-07-09 2008-07-09 半導体装置 Pending JP2010021274A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008179207A JP2010021274A (ja) 2008-07-09 2008-07-09 半導体装置
US12/260,494 US7719087B2 (en) 2008-07-09 2008-10-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008179207A JP2010021274A (ja) 2008-07-09 2008-07-09 半導体装置

Publications (1)

Publication Number Publication Date
JP2010021274A true JP2010021274A (ja) 2010-01-28

Family

ID=41504421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008179207A Pending JP2010021274A (ja) 2008-07-09 2008-07-09 半導体装置

Country Status (2)

Country Link
US (1) US7719087B2 (ja)
JP (1) JP2010021274A (ja)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60167432A (ja) 1984-02-10 1985-08-30 Matsushita Electronics Corp 半導体装置
JP3507828B2 (ja) * 2001-09-11 2004-03-15 シャープ株式会社 ヘテロ接合バイポーラトランジスタ及びその製造方法
KR100568567B1 (ko) * 2003-12-19 2006-04-07 한국전자통신연구원 이종 접합 쌍극자 트랜지스터 및 그 제조 방법

Also Published As

Publication number Publication date
US7719087B2 (en) 2010-05-18
US20100007003A1 (en) 2010-01-14

Similar Documents

Publication Publication Date Title
TWI414082B (zh) 具有過電壓保護之發光二極體晶片
JP2012028567A (ja) 半導体装置
JP5962522B2 (ja) 半導体レーザ装置
JP3663281B2 (ja) 半導体発光素子
JPH10242516A (ja) 窒化ガリウム系化合物半導体発光素子及びその製造方法
US20150270240A1 (en) Power semiconductor device
JP2013229547A (ja) 半導体装置および半導体モジュール
CN104934398A (zh) 电子部件和引线框架
JP2008108886A (ja) 樹脂封止半導体装置
US9685396B2 (en) Semiconductor die arrangement
JP2010021274A (ja) 半導体装置
US20100084684A1 (en) Insulated gate bipolar transistor
JP2000216442A (ja) 半導体発光装置
JP2020043200A (ja) 半導体装置
JP2002094121A (ja) 半導体発光装置
KR100747642B1 (ko) 측면 발광형 led 패키지
JP2007059867A (ja) 半導体装置
JPH10117018A (ja) チップ型発光ダイオード
JP2010199149A (ja) 半導体装置
JP2005012092A (ja) 光ファイバ用ledおよびその製造方法
JP5369396B2 (ja) 半導体装置
JP6760518B2 (ja) 半導体モジュール
KR20100101771A (ko) 발광소자 패키지 및 그 제조방법
US8729572B2 (en) Light emitting diode package having a voltage stabilizing module consisting of two doping layers
JP7412246B2 (ja) 半導体装置