JP2009508339A - チップモジュール及びその形成方法 - Google Patents
チップモジュール及びその形成方法 Download PDFInfo
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Abstract
【解決手段】基板(13)上に内側接点および外側接点(17,18)を備えるチップキャリア(11)を有する非接触スマートカードを形成するためのチップモジュール(10)であって、内側接点(17)がチップキャリア上に配置されるチップユニット(12)のパッドに対して接触接続され、外側接点(18)がアンテナに対する接触接続に役立つチップモジュールにおいて、チップユニット(12)が基板(13)と繊維強化カバー層(23)との間にサンドイッチ状で収容され、それにより、カバー層が、チップユニット(12)の少なくとも2つの対向する側縁に隣接して基板(13)に接続されるチップモジュール、および、チップモジュールを形成するための方法。
【選択図】図1
Description
Claims (17)
- 基板上に複数の内側接点および複数の外側接点を備えるチップキャリアを有する非接触チップカードを形成するためのチップモジュールであって、複数の前記内側接点が、チップキャリア上に配置されるチップユニットの複数の端子領域に結合され、そして、複数の前記外側接点が、アンテナに結合されるのに役立つところのチップモジュールにおいて、
前記チップユニット(12)が、前記基板(13)と繊維強化カバー層(23)との間にサンドイッチ状で収容され、それにより、前記カバー層が、チップユニット(12)の少なくとも2つの対向する側縁に隣接して、前記基板(13)に接続されることを特徴とするチップモジュール。 - 前記カバー層(23)が、前記チップユニット(12)の外周(24)に沿って、前記基板(13)に接続されることを特徴とする、請求項1に記載のチップモジュール。
- 前記カバー層(23)が、チップ表面(22,33)に接続されることを特徴とする、請求項1または2に記載のチップモジュール。
- 前記チップユニット(12)が、特定の相対移動度を伴って、前記基板(13)または前記カバー層(23)に接続されることを特徴とする、請求項1ないし3のいずれか1項に記載のチップモジュール。
- 前記チップユニット(12)が、前記基板(13)と前記カバー層(23)との間の積層接続体(35)内に収容されることを特徴とする、請求項1ないし4のいずれか1項に記載のチップモジュール。
- 前記カバー層(23)が、エポキシ樹脂を主成分として形成されることを特徴とする、請求項5に記載のチップモジュール。
- 前記カバー層(23)および前記基板(13)が、エポキシ樹脂を主成分として形成されることを特徴とする、請求項5に記載のチップモジュール。
- 端子領域(19,20)を有する前記チップユニット(12)が、チップキャリア(11)の内側接点(17)に結合されることを特徴とする、請求項1ないし7のいずれか1項に記載のチップモジュール。
- 前記チップユニット(12)が減少された厚さを有していることを特徴とする、請求項8に記載のチップモジュール。
- 基板上に複数の内側接点および複数の外側接点を備えるチップキャリアと、前記内側接点に結合されるチップユニットとを有するチップモジュールを製造するための方法であって、
第1のプロセスステップにおいて、前記チップユニット(12)の端子領域(19,20)を前記チップキャリア(11)の内側接点(17)に結合し、
次いで、繊維強化カバー層(23)を前記チップユニット(12)上に設けて、前記チップユニット(12)を、前記基板(13)と繊維強化カバー層(23)との間にサンドイッチ状で配置し、
次いで、前記カバー層(23)を、前記チップユニット(12)の少なくとも2つの対向する側縁に隣接して、前記基板(13)に接続する
ことを特徴とする方法。 - 前記カバー層(23)を、更に、チップ表面(22,33)に接続することを特徴とする、請求項10に記載の方法。
- カバー層(23)と基板(13)との間の接続体を、積層プロセスによって形成することを特徴とする、請求項10または11に記載の方法。
- 前記カバー層(23)と前記チップ表面(22,33)との間の接続体、および、前記カバー層(23)と前記基板(13)との間の接続体を、積層プロセスによって形成することを特徴とする、請求項10ないし12のいずれか1項に記載の方法。
- 前記カバー層(23)と前記基板(13)との間の連続する接続体を、積層プロセス中に、前記チップユニット(12)の外周(24)に沿って形成することを特徴とする、請求項12または13に記載の方法。
- 前記積層プロセスを、所定の形状を有するチップ封入体(25)を形成するために金型(31)によって行なうことを特徴とする、請求項12ないし14のいずれか1項に記載の方法。
- 前記チップユニット(12)の端子領域(19,20)の、前記チップキャリア(11)の内側接点(17)への結合を、前記チップキャリア(11)の接点に面する端子領域(19,20)を有するチップキャリア(11)の接点に、前記チップユニット(12)を結合するように行なうことを特徴とする、請求項10ないし15のいずれか1項に記載の方法。
- 前記チップユニット(12)を前記チップキャリア(11)に結合した後、前記カバー層(23)をチップユニット(12)上に設ける前に、前記チップユニット(12)の厚さを、研磨材処理方法によって減少することを特徴とする請求項16に記載の方法。
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Application Number | Priority Date | Filing Date | Title |
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DE102005044216A DE102005044216A1 (de) | 2005-09-15 | 2005-09-15 | Chipmodul sowie Verfahren zur Herstellung eines Chipmoduls |
DE102005044216.1 | 2005-09-15 | ||
PCT/DE2006/001494 WO2007031050A1 (de) | 2005-09-15 | 2006-08-28 | Chipmodul sowie verfahren zur herstellung eines chipmoduls |
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JP2009508339A true JP2009508339A (ja) | 2009-02-26 |
JP2009508339A5 JP2009508339A5 (ja) | 2009-04-23 |
JP5383194B2 JP5383194B2 (ja) | 2014-01-08 |
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US (1) | US20080259583A1 (ja) |
EP (1) | EP1924960B1 (ja) |
JP (1) | JP5383194B2 (ja) |
KR (1) | KR100998686B1 (ja) |
DE (1) | DE102005044216A1 (ja) |
WO (1) | WO2007031050A1 (ja) |
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US8906749B2 (en) * | 2012-03-28 | 2014-12-09 | Infineon Technologies Ag | Method for fabricating a semiconductor device |
DE102018209818A1 (de) * | 2018-06-18 | 2019-12-19 | Bundesdruckerei Gmbh | Verfahren zum Herstellen eines Wert- oder Sicherheitsdokumentenrohlings mit einer elektronischen Schaltung, ein Wert- oder Sicherheitsdokumentenrohling und ein Sicherheits- und Wertdokument |
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US6972480B2 (en) * | 2003-06-16 | 2005-12-06 | Shellcase Ltd. | Methods and apparatus for packaging integrated circuit devices |
WO2005004195A2 (en) * | 2003-07-03 | 2005-01-13 | Shellcase Ltd. | Method and apparatus for packaging integrated circuit devices |
DE10342295B4 (de) * | 2003-09-12 | 2012-02-02 | Infineon Technologies Ag | Anordnung eines elektrischen Bauelements mit einer elektrischen Isolationsfolie auf einem Substrat und Verfahren zum Herstellen der Anordnung |
-
2005
- 2005-09-15 DE DE102005044216A patent/DE102005044216A1/de not_active Withdrawn
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2006
- 2006-08-28 KR KR1020087008869A patent/KR100998686B1/ko active IP Right Grant
- 2006-08-28 JP JP2008530315A patent/JP5383194B2/ja active Active
- 2006-08-28 US US12/066,741 patent/US20080259583A1/en not_active Abandoned
- 2006-08-28 WO PCT/DE2006/001494 patent/WO2007031050A1/de active Application Filing
- 2006-08-28 EP EP06775912A patent/EP1924960B1/de active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS59172253A (ja) * | 1983-03-18 | 1984-09-28 | Mitsubishi Electric Corp | 半導体装置 |
JPH10125825A (ja) * | 1996-10-23 | 1998-05-15 | Nec Corp | チップ型デバイスの封止構造およびその封止方法 |
JP2002373323A (ja) * | 2001-06-18 | 2002-12-26 | Dainippon Printing Co Ltd | 非接触icチップ付きカード一体型フォーム |
JP2003273571A (ja) * | 2002-03-18 | 2003-09-26 | Fujitsu Ltd | 素子間干渉電波シールド型高周波モジュール |
JP2004158537A (ja) * | 2002-11-05 | 2004-06-03 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
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JP5383194B2 (ja) | 2014-01-08 |
DE102005044216A1 (de) | 2007-03-29 |
KR100998686B1 (ko) | 2010-12-07 |
US20080259583A1 (en) | 2008-10-23 |
EP1924960B1 (de) | 2012-08-15 |
WO2007031050A1 (de) | 2007-03-22 |
EP1924960A1 (de) | 2008-05-28 |
KR20080048066A (ko) | 2008-05-30 |
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