JP2009170744A - Manufacturing method and substrate, of semiconductor device - Google Patents

Manufacturing method and substrate, of semiconductor device Download PDF

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JP2009170744A
JP2009170744A JP2008008752A JP2008008752A JP2009170744A JP 2009170744 A JP2009170744 A JP 2009170744A JP 2008008752 A JP2008008752 A JP 2008008752A JP 2008008752 A JP2008008752 A JP 2008008752A JP 2009170744 A JP2009170744 A JP 2009170744A
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mold
substrate
resin
region
hole
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JP5233288B2 (en
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Shinya Nakaseko
進也 中世古
Yoshiaki Narusawa
良明 成▲沢▼
Hiroshi Aoki
広志 青木
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device, and a substrate, in which wire distortion or mold resin omitting is avoided by inhibiting warping or bending of the substrate. <P>SOLUTION: The manufacturing method of a semiconductor device includes processes of: preparing a substrate having a product region 2 in which a plurality of semiconductor devices are mounted, and a perimeter region 3 which is arranged in the perimeter of the product region 2 and in which a plurality of hole portions 4 are formed whose inner wall surface has first thermoplastic resin 5; arranging the substrate between a first die and a second die constituting a mold, and inserting a plurality of pins 6 provided in the first die or the second die into the plurality of hole portions 4; clamping the perimeter region 3 with the first die and the second die; filling with a molten second resin 7 a cavity formed by the first die and the second die, and sealing a plurality of semiconductor devices; and hardening the molten second resin 7 and thereafter cutting the substrate and the second resin 7 for each semiconductor device. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は半導体装置の製造方法及び基板に関するものであり、特に、大判モールドにおける基板の撓みを解消して不良製品の発生を抑制するための構成に特徴のある半導体装置の製造方法及び基板に関するものである。   The present invention relates to a method for manufacturing a semiconductor device and a substrate, and more particularly to a method for manufacturing a semiconductor device and a substrate characterized by a configuration for eliminating the deflection of the substrate in a large format mold and suppressing the occurrence of defective products. It is.

一般に、半導体集積回路装置の製造工程においては、シリコンウェーハに多数の集積回路装置を形成したのち、まず、ウェーハ状態で各半導体集積回路装置について基本的な電気特性試験を行って良品／不良品の選別を行い、次いで、ウェーハを半導体チップにダイシングし、良品チップのみを取り出してパッケージ化している。   In general, in the manufacturing process of a semiconductor integrated circuit device, after a large number of integrated circuit devices are formed on a silicon wafer, first, basic electrical characteristic tests are performed on each semiconductor integrated circuit device in the wafer state to determine whether the product is good or defective. Then, the wafer is diced into semiconductor chips, and only non-defective chips are taken out and packaged.

このパッケージ化に際して大判基板上に複数の半導体チップを搭載して、一括で樹脂封止したのち、各半導体パッケージに切断・分割している。
このような一括封止型半導体パッケージの製造方法としてはトランスファモールド方法が知られており、そのなかでも、実装基板の側面側から樹脂を注入するサイドゲート方式のトランスファモールド方法（例えば、特許文献１参照）が知られている。 At the time of packaging, a plurality of semiconductor chips are mounted on a large-sized substrate, resin-sealed at once, and then cut and divided into semiconductor packages.
A transfer mold method is known as a manufacturing method of such a batch-sealed semiconductor package, and among them, a side gate type transfer mold method in which resin is injected from the side surface side of the mounting substrate (for example, Patent Document 1). See).

ここで、図６乃至図１１を参照して、従来のサイドゲート方式のトランスファモールド方法を説明する。
図６参照
図６はトランスファモールド装置の概略的断面図であり、まず、モールド装置本体部５０に下金型５１1 と上金型５１2 とからなる金型５１を収容して、例えば、１６０℃〜１８０℃の温度に金型５１を昇温する。 Here, a conventional side gate type transfer molding method will be described with reference to FIGS.
See FIG.
FIG. 6 is a schematic cross-sectional view of the transfer mold apparatus. First, a mold 51 composed of a lower mold 51 1 and an upper mold 51 2 is accommodated in the mold apparatus main body 50, for example, 160 ° C. to 180 ° C. The mold 51 is heated to a temperature of ° C.

この場合の金型５１は、例えば、超鋼材により形成され、下金型５１1 の端部には、実装基板を位置決めするための超鋼材製の位置決めピン５２が設けられており、一方、上金型５１2 には位置決めピン５２と対向する位置に位置決めピン５２を収容する収容孔５３が設けられているとともに、エアベント５４が設けられている。 Mold 51 in this case is, for example, be formed by ultrasonic steel, the end portion of the lower mold 51 1, super steel material made of the positioning pin 52 is provided for positioning the mounting substrate, while the upper with housing hole 53 in the mold 51 2 housing the positioning pin 52 at a position opposite to the positioning pins 52 are provided, air vent 54 is provided.

また、下金型５１1 の他方の端部にはモールド樹脂６０を送り込むプランジャー６１を通させるための複数の通過孔５５が形成されており、また、上金型５１2 には通過孔５５と対向する位置にカル５６が設けられており、このカル５６とプランジャー６１との間にポット６２が形成される。 Moreover, with a plurality of passage holes 55 for letting through the plunger 61 for feeding the molding resin 60 at the other end portion of the lower mold 51 1 is formed and also the upper mold 51 2 passing holes 55 A cull 56 is provided at a position opposite to, and a pot 62 is formed between the cull 56 and the plunger 61.

また、この上金型５１2 に設けたカル５６との接続部に溶融したモールド樹脂を上金型５１2 に設けたキャビティ５８に送り込むランナー５７が設けられている。
たとえば、キャビティ５８の高さは、モールドする半導体チップの厚さが０．２５ｍｍの場合、約０．６ｍｍ程度になる。 Also, runners 57 for feeding the molding resin which is melted in the connection of the cull 56 provided on the upper mold 51 2 into a cavity 58 provided in the upper die 51 2 is provided.
For example, the height of the cavity 58 is about 0.6 mm when the thickness of the semiconductor chip to be molded is 0.25 mm.

図７参照
図７は、下方から見た上金型の概略的平面図であり、ここでは、例えば、各５個のカル５６及びランナー５７を設け、また、各ランナー５７には各２つの分岐路５９を設け、合計１０個の分岐路５９からキャビティ５８に溶融したモールド樹脂が注入される。 See FIG.
FIG. 7 is a schematic plan view of the upper mold as viewed from below. Here, for example, five culls 56 and runners 57 are provided, and each runner 57 is provided with two branch paths 59. The molten mold resin is injected into the cavity 58 from a total of ten branch paths 59.

次いで、１６０℃〜１８０℃に昇温した金型５１内に、半導体チップ７２をマウントするとともに金ワイヤ７３で基板に設けたパッドとの接続を終えた大判実装基板７０を搬入して、大判実装基板７０の端部に設けた位置合わせ穴７１を下金型５１1 の端部に設けた位置決めピン５２が挿入するように位置合わせする。
なお、この場合の大判実装基板７０は、例えば、ＦＲ−４からなり、厚さは０．３４ｍｍとする。 Next, the large-sized mounting board 70 in which the semiconductor chip 72 is mounted and the connection with the pad provided on the board with the gold wire 73 is loaded into the mold 51 heated to 160 ° C. to 180 ° C. positioning pins 52 which alignment holes 71 provided in the end portion provided at an end portion of the lower mold 51 the first substrate 70 is aligned for insertion.
In this case, the large-sized mounting board 70 is made of, for example, FR-4 and has a thickness of 0.34 mm.

図８参照
図８は、上方から見た位置合わせした状態における下金型の概略的平面図であり、ここでは、一例として、モールド樹脂の流れる方向に４個、長さ方向に８個の半導体チップ７２が実装された構成として示している。 See FIG.
FIG. 8 is a schematic plan view of the lower mold in the aligned state as viewed from above. Here, as an example, four semiconductor chips 72 are provided in the mold resin flow direction and eight in the length direction. Shown as implemented configuration.

図９参照
次いで、プランジャー６１上に固体状のモールド樹脂６０をセットする。 See FIG.
Next, a solid mold resin 60 is set on the plunger 61.

図１０参照
次いで、モールド装置本体部５０を駆動して上金型５１2 を降下させて上金型５１2 の両端部が大判実装基板７０を押さえ込むようにクランプする。
この段階で、大判実装基板７０及びモールド樹脂６０が金型の温度まで昇温しており、大判実装基板７０は充分延びた状態となり、また、モールド樹脂６０は溶融して溶融モールド樹脂となる。 See FIG.
Then, by driving the mold apparatus body 50 is lowered the upper mold 51 2 at both ends of the upper die 51 2 is clamped so hold down the large-sized mounting board 70.
At this stage, the large-sized mounting substrate 70 and the mold resin 60 are heated to the mold temperature, the large-sized mounting substrate 70 is in a sufficiently extended state, and the mold resin 60 is melted to become a molten mold resin.

図１１参照
次いで、プランジャー６１を上昇させて、溶融モールド樹脂６３をカル５６→ランナー５７（→分岐路５９）を介してキャビティ５８の内部に注入する。
この時の樹脂注入圧力、即ち、トランスファ圧力は、モールド樹脂が金型から漏れるのを防止するために、クランブ圧力と同じか若干弱めに設定する。 See FIG.
Next, the plunger 61 is raised, and the molten mold resin 63 is injected into the cavity 58 via the cal 56 → runner 57 (→ branch path 59).
The resin injection pressure at this time, that is, the transfer pressure is set to be the same as or slightly weaker than the clamping pressure in order to prevent the mold resin from leaking from the mold.

注入された溶融モールド樹脂６３はランナー５７側からエアベント５４に向かって流動して、ランナー５７側に位置する半導体チップ７２からエアベント５４側に位置する半導体チップ７２を順次モールドしていく。
以降は、所定の温度まで降温した状態で、樹脂モールドの完了した大判実装基板７０を金型５１から取り出したのち、各半導体パッケージへと切断・分離することになる。 The injected molten mold resin 63 flows from the runner 57 side toward the air vent 54 and sequentially molds the semiconductor chip 72 located on the air vent 54 side from the semiconductor chip 72 located on the runner 57 side.
Thereafter, the large-sized mounting substrate 70 in which the resin molding is completed is taken out from the mold 51 in a state where the temperature is lowered to a predetermined temperature, and then cut and separated into each semiconductor package.

近年の半導体チップの高集積化の進展により、半導体チップを搭載する実装基板の層数が増加するため、実装基板として上述のように厚さが０．３ｍｍ以上の厚い実装基板を用いている。
一方、半導体パッケージの薄型化への要求も高まり、厚い実装基板を用いて半導体パッケージを薄型化するためには、キャビティを薄くする必要があり、そのために、０．６ｍｍ以下の薄いキャビティのモールドを行うケースが増えている。
特開２００６−３３９４２８号公報 Due to the recent progress in high integration of semiconductor chips, the number of layers of the mounting substrate on which the semiconductor chip is mounted is increased. Therefore, as described above, a thick mounting substrate having a thickness of 0.3 mm or more is used.
On the other hand, there is an increasing demand for thinning of a semiconductor package, and in order to thin the semiconductor package using a thick mounting substrate, it is necessary to make the cavity thin. For this reason, a mold having a thin cavity of 0.6 mm or less is required. More cases to do.
JP 2006-339428 A

しかし、キャビティが薄くなるにしたがって、モールド樹脂の未充填やワイヤ変形が発生するという問題がある。
即ち、モールド工程の熱の影響により、実装基板が熱膨張するが、その際に基板に反りや撓みが発生する。 However, as the cavity becomes thinner, there is a problem that mold resin is not filled or wire deformation occurs.
That is, the mounting substrate thermally expands due to the influence of heat in the molding process, but warping or bending occurs at that time.

例えば、半導体チップを実装した側は半導体チップの熱膨張係数が基板の熱膨張係数に比べて小さいので実装側が凸に反ることになる。
この時、実装基板は金型によりクランプされているので、金型のキャビティ内で反りや撓みが残ったままモールドされてしまう。 For example, since the thermal expansion coefficient of the semiconductor chip is smaller than the thermal expansion coefficient of the substrate on the side where the semiconductor chip is mounted, the mounting side is warped convexly.
At this time, since the mounting substrate is clamped by the mold, it is molded while warping or bending remains in the cavity of the mold.

そうすると、半導体チップのチップ厚が厚い、Ａｕワイヤのループの高さが高い等の条件によりモールド前にＡｕワイヤはキャビティの天井に当接してワイヤ変形が発生したり、或いは、キャビティが低くＡｕワイヤが密集している場合にはモールド樹脂の未充填が発生したりする。   Then, the Au wire abuts against the ceiling of the cavity before molding due to the condition that the chip thickness of the semiconductor chip is thick, the height of the loop of the Au wire is high, etc. In the case of densely packed, mold resin is not filled.

このような実装基板の撓みを解消させるためには、トランスファ圧力を利用して実装基板をスライドさせて実装基板の撓みを解消させることも考えられるが、下金型に設けた位置決めピンと実装基板とが接触して基板が延びきらないという問題が発生するので、この様子を図１２を参照して説明する。   In order to eliminate such bending of the mounting board, it may be possible to eliminate the bending of the mounting board by sliding the mounting board using transfer pressure, but the positioning pins provided on the lower mold and the mounting board This causes a problem that the substrate cannot be extended due to contact with each other, and this state will be described with reference to FIG.

図１２参照
図１２は、トランスファ圧力を利用した場合の問題点の説明図であり、まず、上図に示すように、大判実装基板７０は溶融モールド樹脂６３のトランスファ圧力によりエアベント側に延伸する。
なお、金型でクランプされた状態で、位置決めピン５３と大判実装基板７０に設けた位置合わせ穴７１とはある程度の間隙を有している。 See FIG.
FIG. 12 is an explanatory diagram of problems in the case where the transfer pressure is used. First, as shown in the upper drawing, the large-sized mounting substrate 70 is stretched to the air vent side by the transfer pressure of the molten mold resin 63.
In addition, the positioning pin 53 and the alignment hole 71 provided in the large-sized mounting substrate 70 have a certain amount of gap in a state of being clamped by the mold.

しかし、溶融モールド樹脂６３が逐次注入されてくると、大判実装基板７０の延伸は位置決めピン５３で阻まれ、それ以上のトランスファ圧力が加わると撓み７４が発生することになる。   However, when the molten mold resin 63 is sequentially injected, the extension of the large-sized mounting substrate 70 is blocked by the positioning pins 53, and when a transfer pressure higher than that is applied, the deflection 74 occurs.

したがって、本発明は、基板の反りや撓みを解消して、ワイヤ変形やモールド樹脂の未充填を回避することを目的とする。   Accordingly, an object of the present invention is to eliminate the warping and bending of the substrate and avoid wire deformation and unfilling of the mold resin.

本発明の一観点によれば、複数の半導体素子が搭載された製品領域と、前記製品領域の周辺に配置され、内周壁面に熱可塑性の第１の樹脂が配設された複数の孔部が形成された周辺領域とを有する基板を用意する工程と、金型を構成する第１の型と第２の型との間に前記基板を配置するとともに、前記複数の孔部に前記第１の型又は前記第２の型に配設された複数のピンを挿入する工程と、前記第１の型と前記第２の型により前記周辺領域をクランプする工程と、前記第１の型と前記第２の型により形成されるキャビティに、溶融した第２の樹脂を充填して、前記複数の半導体素子を封止する工程と、前記溶融した第２の樹脂が硬化した後、前記基板及び前記第２の樹脂を前記半導体素子毎に切断する工程とを含む半導体装置の製造方法が提供される。   According to one aspect of the present invention, a product region in which a plurality of semiconductor elements are mounted, and a plurality of holes that are disposed around the product region and in which a thermoplastic first resin is disposed on an inner peripheral wall surface And a step of preparing a substrate having a peripheral region in which the substrate is formed, and the substrate is disposed between a first mold and a second mold constituting a mold, and the first holes are disposed in the plurality of holes. Inserting a plurality of pins arranged in the mold or the second mold, clamping the peripheral region with the first mold and the second mold, the first mold and the Filling the cavity formed by the second mold with a melted second resin to seal the plurality of semiconductor elements; and after the melted second resin is cured, the substrate and the substrate A method of manufacturing a semiconductor device including a step of cutting a second resin for each of the semiconductor elements. It is.

また、別の観点によれば、複数の半導体素子が搭載される製品領域と、前記製品領域の周辺に配置される周辺領域とを有する基板本体と、前記周辺領域に形成される複数の孔部と、前記複数の孔部の内周壁面に形成される熱可塑性の樹脂とを備える基板が提供される。   According to another aspect, a substrate body having a product region on which a plurality of semiconductor elements are mounted, a peripheral region disposed around the product region, and a plurality of holes formed in the peripheral region And a thermoplastic resin formed on the inner peripheral wall surface of the plurality of holes.

本発明によれば、トランスファモールド工程において、金型に設けたピンと基板とが接触して基板が延びきらないという事態を回避することができ、それによって、基板の製品領域に搭載された半導体素子のワイヤの変形や、第２の樹脂の未充填という問題が発生することがないので、製造歩留りの向上に寄与するところが大きい。   According to the present invention, in the transfer molding process, it is possible to avoid a situation in which the pins provided on the mold are in contact with the substrate and the substrate cannot be extended, and thereby the semiconductor element mounted in the product area of the substrate. There is no problem of deformation of the wire or unfilling of the second resin, which greatly contributes to the improvement of the manufacturing yield.

ここで図１を参照して、本発明の実施の形態を説明する。
図１は、本発明の実施の形態の構成説明図であり、製品領域２と、製品領域２の周辺に配置され、内周壁面に熱可塑性樹脂等の第１の樹脂５が配設された複数の位置決め用の孔部４が形成された周辺領域３とを有する基板の製品領域２に複数の半導体素子を搭載したのち、複数の位置決め用の孔部４に金型を構成する第１の型又は第２の型に設けた複数の位置決め用のピン６を挿入して基板をモールド温度まで昇温した金型内に配置して、第１の型と第２の型により周辺領域３をクランプし、次いで、第１の型と第２の型により形成されるキャビティに、溶融したモールド樹脂である第２の樹脂７を充填して複数の半導体素子を封止し、次いで、溶融したモールド樹脂が硬化したのち、基板を金型から取り出して基板及びモールド樹脂を半導体素子毎に切断するものである。 An embodiment of the present invention will now be described with reference to FIG.
FIG. 1 is an explanatory diagram of a configuration of an embodiment of the present invention, which is arranged around a product region 2 and the product region 2, and a first resin 5 such as a thermoplastic resin is arranged on an inner peripheral wall surface. After mounting a plurality of semiconductor elements on the product region 2 of the substrate having a peripheral region 3 in which a plurality of positioning holes 4 are formed, a first mold is formed in the plurality of positioning holes 4. A plurality of positioning pins 6 provided on the mold or the second mold are inserted, the substrate is placed in a mold heated to the mold temperature, and the peripheral region 3 is defined by the first mold and the second mold. Clamping is then performed, and a cavity formed by the first mold and the second mold is filled with a second resin 7 that is a molten mold resin to seal a plurality of semiconductor elements. After the resin has hardened, remove the board from the mold and make the board and mold resin semiconductive. It is intended to cut into elements.

このように、内周壁面に熱可塑性の第１の樹脂５が配設された複数の孔部４が形成された周辺領域３とを有する基板を用いることによって、トランスファ圧力を利用して基板の撓みを解消させる際に、内周壁面に設けた熱可塑性の第１の樹脂５がバッファとなるので、金型に設けたピン６と基板とが接触して基板が延びきらないという事態を回避することができる。
また、それによって、基板の製品領域２に搭載された半導体素子のワイヤの変形や、第２の樹脂７の未充填という問題が発生することがない。 In this way, by using a substrate having a peripheral region 3 in which a plurality of holes 4 in which a thermoplastic first resin 5 is disposed on the inner peripheral wall surface is used, transfer pressure is used for the substrate. When the bending is eliminated, the thermoplastic first resin 5 provided on the inner peripheral wall surface serves as a buffer, so that it is possible to avoid the situation where the pin 6 provided on the mold contacts the substrate and the substrate does not extend completely. can do.
This also prevents the problem of deformation of the wires of the semiconductor element mounted on the product region 2 of the substrate and the unfilling of the second resin 7.

また、基板本体１の周辺部分をクランプする前に、第１の型と第２の型が第２の樹脂７の溶融温度に達していることが望ましく、それによって、基板が第２の樹脂７の溶融温度に達するまでの時間を短縮することができ、トランスファモールド工程に要する時間を短縮することができる。   Further, it is desirable that the first mold and the second mold reach the melting temperature of the second resin 7 before the peripheral portion of the substrate body 1 is clamped. The time required to reach the melting temperature can be shortened, and the time required for the transfer molding process can be shortened.

なお、この場合の位置決め孔部４の形状は円状でも長孔状でも良く、基板本体１は矩形状である場合、複数の位置決め孔部４のうち、基板本体１の角部近傍に形成される位置決め孔部４を基板本体１の縁部に傾斜して延在する長孔としても良い。   In this case, the positioning hole 4 may be circular or elongated. When the substrate body 1 is rectangular, the positioning hole 4 is formed near the corner of the substrate body 1 among the plurality of positioning holes 4. The positioning hole 4 may be a long hole that is inclined and extends to the edge of the substrate body 1.

また、位置決め孔部４の形状の内周壁面に配設する熱可塑性樹脂は、位置決め孔部４の内周壁面のうち、製品領域２に近い部分に形成しても良いし、位置決め孔部４の内周壁面の全体に形成しても良い。   Further, the thermoplastic resin disposed on the inner peripheral wall surface of the positioning hole 4 may be formed in a portion of the inner peripheral wall surface of the positioning hole 4 close to the product region 2, or the positioning hole 4 You may form in the whole inner peripheral wall surface.

この場合の熱可塑性樹脂の充填方法としては、まず、大きなサイズに形成した位置決め用の孔部４を熱可塑性樹脂で埋め込んだのち、位置決めピン６の面積の１．１倍以上の面積の開口部を熱可塑性樹脂中に形成しても良い。   As a filling method of the thermoplastic resin in this case, first, the positioning hole 4 formed in a large size is filled with the thermoplastic resin, and then an opening having an area of 1.1 times or more the area of the positioning pin 6 is provided. May be formed in a thermoplastic resin.

或いは、まず、大きなサイズに位置決め用の孔部４を形成したのち、位置決め用のピン６の面積の１．１倍以上の面積の開口部を覆うようにマスクを設け、スクリーン印刷で残部に熱可塑性樹脂を埋め込んでも良い。   Alternatively, first, after forming the positioning hole 4 in a large size, a mask is provided so as to cover an opening having an area of 1.1 times or more the area of the positioning pin 6, and the remaining part is heated by screen printing. A plastic resin may be embedded.

次に、図２及び図３を参照して、本発明の実施例１の実装基板を説明する。
図２参照
図２は、本発明の実施例１の実装基板の概略的平面図であり、例えば、厚さが０．３４ｍｍのＦＲ−４からなる実装基板１１のサイドゲート方式のトランスファモールド方法におけるサイドゲートに対応する辺と反対側の周辺部に、位置合わせ穴１２を設けるとともに、位置合わせ穴１２の内側壁に、例えば、エポキシ系の熱可塑性樹脂１３を充填する。 Next, with reference to FIG.2 and FIG.3, the mounting substrate of Example 1 of this invention is demonstrated.
See Figure 2
FIG. 2 is a schematic plan view of the mounting substrate according to the first embodiment of the present invention. For example, the side substrate in the side gate type transfer molding method of the mounting substrate 11 made of FR-4 having a thickness of 0.34 mm is used. An alignment hole 12 is provided in the peripheral portion opposite to the corresponding side, and an inner wall of the alignment hole 12 is filled with, for example, an epoxy-based thermoplastic resin 13.

この場合の位置合わせ穴１２の開口部１４のサイズは、実装基板１１のサイズや、金型に設けた位置決めピンの大きさに依存するが、位置決めピンの面積の１．０倍以上の面積、例えば、１．１倍の面積とする。
即ち、残りの０．１倍以上の面積が、位置決めピンに対するゆとりとなる。 In this case, the size of the opening 14 of the alignment hole 12 depends on the size of the mounting substrate 11 and the size of the positioning pin provided on the mold, but the area of 1.0 or more times the area of the positioning pin, For example, the area is 1.1 times.
That is, the remaining area of 0.1 times or more is a space for the positioning pins.

また、ここでは、位置合わせ穴１２の長径Ｌを例えば３．０ｍｍとし、短径Ｈを１．５ｍｍとし、Ｌ−Ｈの範囲を熱可塑性樹脂１３で充填する。
また、この場合の実装基板１１の熱線膨張係数は１０〜１５ｐｐｍであり、また、熱可塑性樹脂１３の熱線膨張係数は５０〜１００ｐｐｍである。
この実装基板を用いて半導体装置を製造する際には、上述の従来例と全く同様のモールド装置を用いて、全く同様の工程でトランスファモールドを行うものである。 Here, the major axis L of the alignment hole 12 is set to 3.0 mm, the minor axis H is set to 1.5 mm, and the range of LH is filled with the thermoplastic resin 13.
In this case, the thermal expansion coefficient of the mounting substrate 11 is 10 to 15 ppm, and the thermal linear expansion coefficient of the thermoplastic resin 13 is 50 to 100 ppm.
When a semiconductor device is manufactured using this mounting substrate, transfer molding is performed in exactly the same process using a molding device that is exactly the same as the above-described conventional example.

図３参照
図３は、本発明の実施例１の実装基板を用いたトランスファモールド工程における撓み解消効果の説明図である。
左図に示すように、溶融したモールド樹脂１５が位置決めピン１６側に流れ込んでくると、左図の中段図に示すように元々発生していた実装基板１１の撓みがトランスファ圧力によって位置決めピン１６側に押し寄せることになる。 See Figure 3
FIG. 3 is an explanatory diagram of the bending elimination effect in the transfer molding process using the mounting substrate of Example 1 of the present invention.
As shown in the left figure, when the molten mold resin 15 flows into the positioning pin 16 side, the bending of the mounting substrate 11 originally generated as shown in the middle figure of the left figure is caused by the transfer pressure to the positioning pin 16 side. Will rush to.

この時、位置合わせ穴１２の内側壁に設けた熱可塑性樹脂１３は柔らかくなっているので、実装基板１１の撓みが柔らかくなった熱可塑性樹脂１３の変形によって吸収されるので、実装基板１１が位置決めピン１６に接触することなく、実装基板１１の撓みが解消されることになる。   At this time, since the thermoplastic resin 13 provided on the inner wall of the alignment hole 12 is soft, the bending of the mounting substrate 11 is absorbed by the deformation of the thermoplastic resin 13 that has been softened, so that the mounting substrate 11 is positioned. The bending of the mounting substrate 11 is eliminated without contacting the pins 16.

本発明の実施例１においては、位置合わせ穴を従来より大きく形成して、サイドゲート側の内側壁に熱可塑性樹脂を充填し、この熱可塑性樹脂をバッファとしているので、トランスファ圧力を利用して実装基板の撓みを確実に解消することができ、それによって、相殺する半導体素子のワイヤ変形やモールド樹脂の未充填が発生することがない。   In Embodiment 1 of the present invention, the alignment hole is formed larger than before, and the inner wall on the side gate side is filled with a thermoplastic resin, and this thermoplastic resin is used as a buffer, so transfer pressure is used. The bending of the mounting substrate can be surely eliminated, so that the wire deformation of the semiconductor element to be canceled and the unfilling of the mold resin do not occur.

次に、図４を参照して、本発明の実施例２の実装基板を説明する。
図４参照
図４は、本発明の実施例２の実装基板の概略的平面図であり、例えば、厚さが０．３４ｍｍのＦＲ−４からなる実装基板２１のサイドゲート方式のトランスファモールド方法におけるサイドゲートに対応する辺と反対側の周辺部に、位置合わせ穴２２を設けるとともに、位置合わせ穴２２の内側壁に、例えば、エポキシ系の熱可塑性樹脂２３を充填する。 Next, with reference to FIG. 4, the mounting substrate of Example 2 of this invention is demonstrated.
See Figure 4
FIG. 4 is a schematic plan view of a mounting substrate according to the second embodiment of the present invention. For example, the side gate in the side gate type transfer molding method of the mounting substrate 21 made of FR-4 having a thickness of 0.34 mm is used. An alignment hole 22 is provided in the peripheral portion opposite to the corresponding side, and an inner wall of the alignment hole 22 is filled with, for example, an epoxy-based thermoplastic resin 23.

この場合も、位置合わせ穴２２（２２1 ，２２2 ）の開口部２４のサイズは、実装基板２１のサイズや、金型に設けた位置決めピンの大きさに依存するが、位置決めピンの面積の１．１倍以上の面積とする。
即ち、残りの０．１倍以上の面積が、位置決めピンに対するゆとりとなる。
また、ここでも、位置合わせ穴２２の長径Ｌを例えば３．０ｍｍとし、短径Ｈを１．５ｍｍとし、Ｌ−Ｈの範囲を熱可塑性樹脂２３で充填する。 Also in this case, the size of the opening 24 of the alignment hole 22 (22 1 , 22 2 ) depends on the size of the mounting substrate 21 and the size of the positioning pin provided on the mold, but the area of the positioning pin The area is 1.1 times or more.
That is, the remaining area of 0.1 times or more is a space for the positioning pins.
Also in this case, the long diameter L of the alignment hole 22 is set to, for example, 3.0 mm, the short diameter H is set to 1.5 mm, and the range of LH is filled with the thermoplastic resin 23.

但し、この実施例２においては、実装基板２１のサイドゲートに対応する辺と反対側の周辺部の両端部に設ける位置合わせ穴２２2 は、その長軸が基板が伸長する方向に向くように形成する。
即ち、実装基板は、１０〜１５ｐｐｍの熱線膨張係数で縦方向及び横方向に伸びるので、その角部においては、斜め方向に伸びることになり、したがって、位置合わせ穴２２2 を斜め方向に設ける。
なお、中央よりの位置合わせ穴２２1 は、実施例１と同様に長軸がモールド樹脂が流れ込む方向とする。 However, in the second embodiment, the alignment holes 22 2 provided at both ends of the peripheral portion on the opposite side to the side corresponding to the side gate of the mounting substrate 21 have their long axes oriented in the direction in which the substrate extends. Form.
That is, the mounting substrate, because the longitudinally extending and laterally linear thermal expansion coefficient of 10 to 15 ppm, at its corners, will be extended in an oblique direction, therefore, providing the alignment holes 22 2 in the oblique direction.
The alignment hole 22 1 from the center has a long axis in the direction in which the mold resin flows, as in the first embodiment.

この実施例２においては、実装基板２１のサイドゲートに対応する辺と反対側の周辺部の両端部に設ける位置合わせ穴２２2 をその長軸が基板が伸長する方向に向くように形成しているので、熱可塑性樹脂２３によるバッファ効果を充分に発揮することができる。 In the second embodiment, alignment holes 22 2 provided at both ends of the peripheral portion opposite to the side corresponding to the side gate of the mounting substrate 21 are formed so that the major axis thereof is directed in the direction in which the substrate extends. Therefore, the buffer effect by the thermoplastic resin 23 can be sufficiently exhibited.

次に、図５を参照して、本発明の実施例３の実装基板を説明する。
図５参照
図５は、本発明の実施例３の実装基板の概略的平面図であり、例えば、厚さが０．３４ｍｍのＦＲ−４からなる実装基板３１のサイドゲート方式のトランスファモールド方法におけるサイドゲートに対応する辺と反対側の周辺部に、位置合わせ穴３２を設けるとともに、位置合わせ穴３２の内側壁に、例えば、エポキシ系の熱可塑性樹脂３３を充填する。 Next, with reference to FIG. 5, the mounting substrate of Example 3 of this invention is demonstrated.
See Figure 5
FIG. 5 is a schematic plan view of a mounting substrate according to a third embodiment of the present invention. For example, the side gate in the side gate type transfer molding method of the mounting substrate 31 made of FR-4 having a thickness of 0.34 mm is used. An alignment hole 32 is provided in the peripheral portion opposite to the corresponding side, and an inner wall of the alignment hole 32 is filled with, for example, an epoxy-based thermoplastic resin 33.

この場合も、位置合わせ穴３２の開口部３４のサイズは、実装基板３１のサイズや、金型に設けた位置決めピンの大きさに依存するが、位置決めピンの面積の１．１倍以上の面積とする。
即ち、残りの０．１倍以上の面積が、位置決めピンに対するゆとりとなる。 In this case as well, the size of the opening 34 of the alignment hole 32 depends on the size of the mounting substrate 31 and the size of the positioning pin provided on the mold, but the area is 1.1 times or more the area of the positioning pin. And
That is, the remaining area of 0.1 times or more is a space for the positioning pins.

但し、この実施例においては、位置合わせ穴３２を例えば直径Ｒが１．５ｍｍの円形とし、直径ｒが３．０ｍｍの開口部３４との間を熱可塑性樹脂３３で充填する。   However, in this embodiment, the alignment hole 32 is, for example, a circle having a diameter R of 1.5 mm, and the space between the opening portion 34 having a diameter r of 3.0 mm is filled with the thermoplastic resin 33.

この実施例３においては、位置合わせ穴３２の内側壁全体に熱可塑性樹脂３３を充填しているので、実装基板が予測した方向と異なった方向に偏寄して伸長した場合にも、熱可塑性樹脂３３によるバッファ効果を効果的に発揮することができる。   In the third embodiment, since the entire inner wall of the alignment hole 32 is filled with the thermoplastic resin 33, the thermoplastic resin can be used even when the mounting board extends and deviates in a direction different from the predicted direction. The buffer effect by the resin 33 can be exhibited effectively.

以上、本発明の各実施例を説明してきたが、本発明は各実施例に記載された構成・条件等に限られるものではなく各種の変更が可能であり、例えば、上記の各実施例においては、実装基板の素材としてＦＲ−４を用いているが、ＦＲ−４に限られるものではなく、ＦＲ−５、ＢＴ基板、Ｅ−６７９等の他の基材を用いても良いものである。   The embodiments of the present invention have been described above. However, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications are possible. For example, in the above embodiments, Uses FR-4 as a material for the mounting substrate, but is not limited to FR-4, and other base materials such as FR-5, BT substrate, E-679 may be used. .

また、上記の各実施例においては、位置合わせ穴を便宜上４個としているが、４個に限られるものではなく、基板のサイズに応じて適宜変更されるものである。
また、上記の実施例２においては位置合わせ穴を便宜上４個としているため、両端の２個のみを傾斜させて設けているが、５個以上設ける場合には、中央に向かって傾斜が順に小さくなるように形成しても良いものである。 In each of the above embodiments, the number of alignment holes is four for convenience, but the number is not limited to four, and may be changed as appropriate according to the size of the substrate.
In the second embodiment, four alignment holes are provided for convenience, so that only two at both ends are inclined. However, when five or more are provided, the inclination gradually decreases toward the center. It may be formed as follows.

以上の実施例１乃至実施例３を含む実施の形態に関し、さらに、以下の付記を開示する。
（付記１） 複数の半導体素子が搭載された製品領域と、前記製品領域の周辺に配置され、内周壁面に熱可塑性の第１の樹脂が配設された複数の孔部が形成された周辺領域とを有する基板を用意する工程と、金型を構成する第１の型と第２の型との間に前記基板を配置するとともに、前記複数の孔部に前記第１の型又は前記第２の型に配設された複数のピンを挿入する工程と、前記第１の型と前記第２の型により前記周辺領域をクランプする工程と、前記第１の型と前記第２の型により形成されるキャビティに、溶融した第２の樹脂を充填して、前記複数の半導体素子を封止する工程と、前記溶融した第２の樹脂が硬化した後、前記基板及び前記第２の樹脂を前記半導体素子毎に切断する工程とを含むことを特徴とする半導体装置の製造方法。
（付記２） 前記複数の孔部は、前記基板における、前記第２の樹脂の流動方向の下流側に形成されていることを特徴とする付記１記載の半導体装置の製造方法。
（付記３） 前記孔部の内周壁面のうち、少なくとも前記製品領域に近い部分に前記第１の樹脂が配設されていることを特徴とする付記２記載の半導体装置の製造方法。
（付記４） 前記孔部の内周壁面の全体に前記第１の樹脂が配設されていることを特徴とする付記１または２に記載の半導体装置の製造方法。
（付記５） 前記周辺部分をクランプする前に、前記第１の型と前記第２の型が前記第２の樹脂の溶融温度に達していることを特徴とする付記１乃至４のいずれか１に記載の半導体装置の製造方法。
（付記６） 複数の半導体素子が搭載される製品領域と、前記製品領域の周辺に配置される周辺領域とを有する基板本体と、前記周辺領域に形成される複数の孔部と、前記複数の孔部の内周壁面に形成される熱可塑性の樹脂とを備えることを特徴とする基板。
（付記７） 前記樹脂は、前記孔部の内周壁面のうち、少なくとも前記製品領域に近い部分に形成されることを特徴とする付記６記載の基板。
（付記８） 前記樹脂は、前記孔部の内周壁面の全体に形成されていることを特徴とする付記６記載の基板。
（付記９） 前記孔部は、前記基板本体の縁部から前記製品領域に延在する長孔であることを特徴とする付記６乃至８のいずれか１に記載の基板。
（付記１０） 前記基板本体は矩形状に形成され、前記複数の孔部のうち、前記基板本体の角部近傍に形成される孔部は、前記基板本体の縁部に傾斜して延在する長孔であることを特徴とする付記９に記載の基板。 Regarding the embodiment including the above-described Examples 1 to 3, the following additional notes are disclosed.
(Additional remark 1) The product region in which a plurality of semiconductor elements are mounted, and the periphery in which a plurality of holes are formed in the periphery of the product region and the thermoplastic resin is disposed on the inner peripheral wall surface A substrate having a region, and disposing the substrate between a first mold and a second mold constituting a mold, and the first mold or the second mold in the plurality of holes. A step of inserting a plurality of pins arranged in a mold of 2, a step of clamping the peripheral region by the first mold and the second mold, and the first mold and the second mold Filling the cavity to be formed with the melted second resin to seal the plurality of semiconductor elements, and after the melted second resin is cured, the substrate and the second resin are And a step of cutting each semiconductor element.
(Additional remark 2) The said several hole part is formed in the downstream of the flow direction of said 2nd resin in the said board | substrate, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Additional remark 3) The said 1st resin is arrange | positioned at least in the part near the said product area among the inner peripheral wall surfaces of the said hole, The manufacturing method of the semiconductor device of Additional remark 2 characterized by the above-mentioned.
(Additional remark 4) The said 1st resin is arrange | positioned in the whole inner peripheral wall surface of the said hole, The manufacturing method of the semiconductor device of Additional remark 1 or 2 characterized by the above-mentioned.
(Appendix 5) Any one of appendices 1 to 4, wherein the first mold and the second mold reach a melting temperature of the second resin before clamping the peripheral portion. The manufacturing method of the semiconductor device as described in any one of.
(Supplementary Note 6) A substrate body having a product region on which a plurality of semiconductor elements are mounted, a peripheral region disposed around the product region, a plurality of holes formed in the peripheral region, and the plurality of holes And a thermoplastic resin formed on the inner peripheral wall surface of the hole.
(Additional remark 7) The said resin is formed in the part close | similar to the said product area | region among the inner peripheral wall surfaces of the said hole part, The board | substrate of Additional remark 6 characterized by the above-mentioned.
(Additional remark 8) The said resin is formed in the whole inner peripheral wall surface of the said hole, The board | substrate of Additional remark 6 characterized by the above-mentioned.
(Supplementary note 9) The substrate according to any one of supplementary notes 6 to 8, wherein the hole portion is a long hole extending from an edge portion of the substrate main body to the product region.
(Additional remark 10) The said board | substrate body is formed in a rectangular shape, and the hole part formed in the corner | angular part vicinity of the said board | substrate body among the said several hole parts inclines and extends in the edge of the said board | substrate body. The substrate according to appendix 9, wherein the substrate is a long hole.

本発明の活用例としては、半導体集積回路装置のトランスファモールド工程が典型的なものであるが、光半導体装置や混成集積回路装置等の他の電子デバイスのトランスファモールド工程にも適用されるものである。   A typical application example of the present invention is a transfer molding process of a semiconductor integrated circuit device, but it is also applicable to a transfer molding process of other electronic devices such as an optical semiconductor device and a hybrid integrated circuit device. is there.

本発明の実施の形態の構成説明図である。It is a configuration explanatory view of an embodiment of the present invention. 本発明の実施例１の実装基板の概略的平面図である。It is a schematic plan view of the mounting board of Example 1 of the present invention. 本発明の実施例１の実装基板を用いたトランスファモールド工程における撓み解消効果の説明図である。It is explanatory drawing of the bending elimination effect in the transfer mold process using the mounting board | substrate of Example 1 of this invention. 本発明の実施例２の実装基板の概略的平面図である。It is a schematic plan view of the mounting board of Example 2 of the present invention. 本発明の実施例３の実装基板の概略的平面図である。It is a schematic plan view of the mounting board of Example 3 of the present invention. トランスファモールド装置の概略的断面図である。It is a schematic sectional drawing of a transfer mold device. 下方から見た上金型の概略的平面図である。It is a schematic plan view of the upper mold viewed from below. 上方から見た位置合わせした状態における下金型の概略的平面図である。It is a schematic plan view of the lower metal mold in the state of alignment seen from above. モールド樹脂をセットした状態における概略的断面図である。It is a schematic sectional view in the state where mold resin was set. 実装基板をクランプした状態における概略的断面図である。It is a schematic sectional drawing in the state where the mounting substrate was clamped. モールド樹脂を注入した状態における概略的断面図である。It is a schematic sectional drawing in the state where mold resin was poured. トランスファ圧力を利用した場合の問題点の説明図である。It is explanatory drawing of the problem at the time of utilizing a transfer pressure.

符号の説明Explanation of symbols

１ 基板本体
２ 製品領域
３ 周辺領域
４ 孔部
５ 第１の樹脂
６ ピン
７ 第２の樹脂
１１，２１，３１ 実装基板
１２，２２，２２1 ，２２2 ，３２ 位置合わせ穴
１３，２３，３３ 熱可塑性樹脂
１４，２４，３４ 開口部
１５ モールド樹脂
１６ 位置決めピン
５０ モールド装置本体部
５１ 金型
５１1 下金型
５１2 上金型
５２ 位置決めピン
５３ 収容孔
５４ エアベント
５５ 通過孔
５６ カル
５７ ランナー
５８ キャビティ
５９ 分岐路
６０ モールド樹脂
６１ プランジャー
６２ ポット
６３ 溶融モールド樹脂
７０ 大判実装基板
７１ 位置合わせ穴
７２ 半導体チップ
７３ 金ワイヤ
７４ 撓み 1 substrate main body 2 product area 3 surrounding region 4 hole 5 first resin 6 pin 7 second resin 11, 21, 31 mounting board 12,22,22 1, 22 2, 32 alignment holes 13, 23, 33 Thermoplastic resins 14, 24, 34 Opening 15 Mold resin 16 Positioning pin 50 Molding device main body 51 Mold 51 1 Lower mold 51 2 Upper mold 52 Positioning pin 53 Housing hole 54 Air vent 55 Passing hole 56 Cal 57 Runner 58 Cavity 59 Branching path 60 Mold resin 61 Plunger 62 Pot 63 Molten mold resin 70 Large format mounting board 71 Alignment hole 72 Semiconductor chip 73 Gold wire 74 Deflection

Claims (6)

複数の半導体素子が搭載された製品領域と、前記製品領域の周辺に配置され、内周壁面に熱可塑性の第１の樹脂が配設された複数の孔部が形成された周辺領域とを有する基板を用意する工程と、
金型を構成する第１の型と第２の型との間に前記基板を配置するとともに、前記複数の孔部に前記第１の型又は前記第２の型に配設された複数のピンを挿入する工程と、
前記第１の型と前記第２の型により前記周辺領域をクランプする工程と、
前記第１の型と前記第２の型により形成されるキャビティに、溶融した第２の樹脂を充填して、前記複数の半導体素子を封止する工程と、
前記溶融した第２の樹脂が硬化した後、前記基板及び前記第２の樹脂を前記半導体素子毎に切断する工程と、
を含むことを特徴とする半導体装置の製造方法。 A product region on which a plurality of semiconductor elements are mounted; and a peripheral region that is disposed around the product region and has a plurality of holes in which an inner peripheral wall surface is provided with a first thermoplastic resin. Preparing a substrate;
A plurality of pins disposed in the first mold or the second mold in the plurality of hole portions while the substrate is disposed between the first mold and the second mold constituting the mold. Inserting
Clamping the peripheral region with the first mold and the second mold;
Filling the melted second resin into a cavity formed by the first mold and the second mold, and sealing the plurality of semiconductor elements;
Cutting the substrate and the second resin for each semiconductor element after the molten second resin is cured;
A method for manufacturing a semiconductor device, comprising: 前記複数の孔部は、前記基板における、前記第２の樹脂の流動方向の下流側に形成されていることを特徴とする請求項１記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the plurality of holes are formed on a downstream side of the substrate in a flow direction of the second resin. 前記孔部の内周壁面のうち、少なくとも前記製品領域に近い部分に前記第１の樹脂が配設されていることを特徴とする請求項２記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 2, wherein the first resin is disposed at least in a portion close to the product region in an inner peripheral wall surface of the hole. 複数の半導体素子が搭載される製品領域と、前記製品領域の周辺に配置される周辺領域とを有する基板本体と、
前記周辺領域に形成される複数の孔部と、前記複数の孔部の内周壁面に形成される熱可塑性の樹脂と、
を備えることを特徴とする基板。 A substrate body having a product region on which a plurality of semiconductor elements are mounted, and a peripheral region disposed around the product region;
A plurality of holes formed in the peripheral region; and a thermoplastic resin formed on an inner peripheral wall surface of the plurality of holes;
A substrate characterized by comprising: 前記樹脂は、前記孔部の内周壁面のうち、少なくとも前記製品領域に近い部分に形成されることを特徴とする請求項４記載の基板。 The substrate according to claim 4, wherein the resin is formed at least in a portion close to the product region of the inner peripheral wall surface of the hole. 前記孔部は、前記基板本体の縁部から前記製品領域に延在する長孔であることを特徴とする請求項４または５に記載の基板。 The substrate according to claim 4 or 5, wherein the hole is a long hole extending from an edge of the substrate body to the product region.
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
JP2013191690A (en) * 2012-03-13 2013-09-26 Shin Etsu Chem Co Ltd Semiconductor device and method of manufacturing the same

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JP2003188198A (en) * 2001-12-20 2003-07-04 Matsushita Electric Ind Co Ltd Method and apparatus for manufacturing electronic component mounted component
JP2005129783A (en) * 2003-10-24 2005-05-19 Daiichi Seiko Kk Semiconductor resin sealing die

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JP2003188198A (en) * 2001-12-20 2003-07-04 Matsushita Electric Ind Co Ltd Method and apparatus for manufacturing electronic component mounted component
JP2005129783A (en) * 2003-10-24 2005-05-19 Daiichi Seiko Kk Semiconductor resin sealing die

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013191690A (en) * 2012-03-13 2013-09-26 Shin Etsu Chem Co Ltd Semiconductor device and method of manufacturing the same
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