JP2003188198A - Method and apparatus for manufacturing electronic component mounted component - Google Patents

Method and apparatus for manufacturing electronic component mounted component

Info

Publication number
JP2003188198A
JP2003188198A JP2001387617A JP2001387617A JP2003188198A JP 2003188198 A JP2003188198 A JP 2003188198A JP 2001387617 A JP2001387617 A JP 2001387617A JP 2001387617 A JP2001387617 A JP 2001387617A JP 2003188198 A JP2003188198 A JP 2003188198A
Authority
JP
Japan
Prior art keywords
electronic component
base material
component
electrode
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001387617A
Other languages
Japanese (ja)
Other versions
JP3739699B2 (en
JP2003188198A5 (en
Inventor
Daisuke Sakurai
大輔 櫻井
Norito Tsukahara
法人 塚原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001387617A priority Critical patent/JP3739699B2/en
Priority to US10/285,475 priority patent/US7176055B2/en
Priority to CNB02149813XA priority patent/CN1204610C/en
Publication of JP2003188198A publication Critical patent/JP2003188198A/en
Publication of JP2003188198A5 publication Critical patent/JP2003188198A5/ja
Application granted granted Critical
Publication of JP3739699B2 publication Critical patent/JP3739699B2/en
Priority to US11/653,304 priority patent/US20070200217A1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and an apparatus for manufacturing an electronic component mounted component capable of satisfying reduction in thickness, flexibility, waterproofness, moistureproofness and high productivity and to provide the electronic component mounted component and a method for manufacturing a multilayer laminated electronic component mounted component. <P>SOLUTION: The method for manufacturing the electronic component mounted with components comprises the steps of embedding the electronic component 1 having electrodes 2 in a thermoplastic resin sheet base 3, and then exposing the electrode 2 to the surface of the sheet base by polishing or plasma etching. Thereafter, a circuit pattern formation by thin film forming or printing or laminating can be performed. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体素子等の電
子部品を基材に実装して電子部品実装済部品を製造す
る、電子部品実装済部品の製造方法及び製造装置、電子
部品実装済部品、及び、上記電子部品実装済部品の製造
方法により製造される電子部品実装済部品を複数枚、厚
み方向に積層化し、ラミネート処理を行う多層積層電子
部品実装済み部品の製造方法に関するものである。より
具体的には、本発明は、上記電子部品の例として、１個
又は複数の半導体素子、コンデンサ、抵抗等の受動部品
を、上記基材の例としての一つのキャリア基板に実装し
たＣＳＰ（チップサイズパッケージ）、ＭＣＭ（マルチ
チップモジュール）、複数個のメモリーチップを多段に
重ねてなるスタックモジュール、メモリーカード、非接
触ＩＣカード等に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for manufacturing an electronic component-mounted component for manufacturing an electronic component-mounted component by mounting an electronic component such as a semiconductor element on a base material, and an electronic component-mounted component. And a method for manufacturing a multi-layer laminated electronic component mounted component in which a plurality of electronic component mounted components manufactured by the above-described electronic component mounted component manufacturing method are laminated in the thickness direction and laminated. More specifically, in the present invention, as an example of the electronic component, a passive component such as one or a plurality of semiconductor elements, capacitors, and resistors is mounted on one carrier substrate as an example of the base material (CSP). Chip size package), MCM (multi-chip module), a stack module formed by stacking a plurality of memory chips in multiple stages, a memory card, a non-contact IC card, and the like.

【０００２】[0002]

【従来の技術】従来の電子部品実装済完成品の製造方法
について、図６及び図７を参照しながら以下に説明す
る。2. Description of the Related Art A conventional method for manufacturing a completed electronic component-mounted product will be described below with reference to FIGS.

【０００３】従来、半導体素子、受動部品等の電子部品
が実装されたＣＳＰ、ＭＣＭ、メモリーモジュールにお
いては、キャリア基板上に半導体素子を導電性接着剤あ
るいはシートを介して加熱・圧接する方法がとられてい
る。また、電子部品は、キャリア基板上の所定の回路パ
ターンにクリーム半田を印刷したのち装着し、その後、
クリーム半田をリフローする方法により、実装されてい
る。Conventionally, in CSPs, MCMs, and memory modules in which electronic components such as semiconductor devices and passive components are mounted, a method of heating and pressing the semiconductor device onto a carrier substrate via a conductive adhesive or a sheet is used. Has been. In addition, electronic parts are printed with cream solder on a predetermined circuit pattern on the carrier board and then mounted, and then
It is mounted by the method of reflowing the solder paste.

【０００４】具体的には、図６に示すように、半導体素
子１０１は、図示していないその電極パッドに形成され
た突起状電極１０２とキャリア基板１０６上の電極１０
３とが、図示していない異方性導電性接着剤を介して，
電気的に接続されて、電子部品実装済み部品が形成され
ている。なお、半導体１０１とキャリア基板１０６との
間にはその接合強度を向上させるため、封止材１０５が
注入・硬化されている。Specifically, as shown in FIG. 6, the semiconductor element 101 includes a projecting electrode 102 formed on an electrode pad (not shown) and the electrode 10 on the carrier substrate 106.
3 and an anisotropic conductive adhesive (not shown)
The components are electrically connected to each other to form electronic component-mounted components. A sealing material 105 is injected and cured between the semiconductor 101 and the carrier substrate 106 to improve the bonding strength.

【０００５】また、キャリア基板１０６及び電子部品１
０９は、キャリア基板１０６上の所定の電極１０４及び
電子部品１０９の電極１０と、マザー基板１１１の所定
の電極１０８とがクリーム半田１０７を介してそれぞれ
接続されている。尚、図６の１１３は、マザー基板１１
１の表面の電極１０８と裏面の回路パターン１１２を電
気的に接続する導体がその内部に形成されたスルーホー
ルである。該スルーホール１１３は、電極１０８が形成
されている面のみで製品としての機能を果たすモジュー
ルの場合は、必要では無い。その製造工程は、図７に示
すように、まず、ステップ(図内では「Ｓ」にて示す)１で
は、マザー基板１１１上の所定の電極１０７上にクリー
ム半田を印刷して塗布する。クリーム半田１０７の印刷
は、一般的にスクリーン印刷法により実施される。Further, the carrier substrate 106 and the electronic component 1
A predetermined electrode 104 on the carrier substrate 106 and the electrode 10 of the electronic component 109 are connected to the predetermined electrode 108 on the mother substrate 111 via cream solder 107. Incidentally, 113 in FIG. 6 is a mother substrate 11
A conductor that electrically connects the electrode 108 on the front surface and the circuit pattern 112 on the back surface is a through hole formed therein. The through hole 113 is not necessary in the case of a module that functions as a product only on the surface on which the electrode 108 is formed. In the manufacturing process, as shown in FIG. 7, first, in step (indicated by “S” in the figure) 1, cream solder is printed and applied on a predetermined electrode 107 on the mother substrate 111. Printing of the solder paste 107 is generally performed by a screen printing method.

【０００６】次のステップ２では、マザー基板１１１上
の上記印刷により形成したクリーム半田１０７上に、半
導体素子１０１が搭載されたキャリア基板１０６及び電
子部品１０９を位置合わせしてそれぞれ実装する。In the next step 2, the carrier substrate 106 on which the semiconductor element 101 is mounted and the electronic component 109 are aligned and mounted on the cream solder 107 formed by printing on the mother substrate 111.

【０００７】その次のステップ３では、半導体素子１０
１を搭載したキャリア基板１０６及び電子部品１０９が
実装されたマザー基板１１１をリフロー炉に通し、クリ
ーム半田１０７を溶融し、その後、硬化させる。In the next step 3, the semiconductor device 10 is
The carrier substrate 106 on which 1 is mounted and the mother substrate 111 on which the electronic component 109 is mounted are passed through a reflow furnace to melt the cream solder 107 and then cure.

【０００８】このようにして、電子部品実装済み部品を
有する電子部品実装済み完成品としてのメモリーモジュ
ール１１４が作製される。In this way, the memory module 114 as a completed electronic component-mounted product having the electronic component-mounted components is manufactured.

【０００９】[0009]

【発明が解決しようとする課題】しかし、上述した従来
の電子部品実装済部品を有する電子部品実装済完成品の
製造方法、及び該電子部品実装済完成品の製造方法にて
製造される電子部品実装済完成品としてのＭＣＭ、メモ
リーモジュール等の構成では、以下の問題があった。However, a method of manufacturing an electronic component-mounted finished product having the above-described conventional electronic component-mounted component, and an electronic component manufactured by the method of manufacturing the electronic component-mounted finished product. The configuration of the MCM, the memory module, etc., as a mounted finished product has the following problems.

【００１０】マザー基板１１１上にＣＳＰ等の電子部品
を搭載するために、モジュールの厚み方向の高さが高く
なり、薄型化が要求される最近の製品二ーズに答えられ
ない。また、そのために、曲げの影響を受けやすく、モ
ジュールを軟らかくすることが難しく、曲面などの形状
に適用が困難である。また、電子部品１０９やキャリア
基板１０６を搭載するためにマザー基板１１１を搭載す
るための領域が必要で、一つのマザー基板１１１に搭載
できる電子部品点数や回路パターンを形成する領域がマ
ザー基板１１１の大きさにより決定され、マザー基板１
１１の小型化が要求される最近の製品二ーズにも応える
ことができない。さらに、半導体素子１０１やクリーム
半田１０７は直接大気にさらされるため、高温高湿の環
境で使用すると酸化が起こり、電気的短絡、オープン不
良、接合強度の低下などが起こりやすい。また、リフロ
ー炉中での温度ばらつきがあるために基板サイズを大き
くできず、バッチ処理が主流になっているが、生産性が
悪い。Since the electronic components such as CSP are mounted on the mother substrate 111, the height of the module in the thickness direction becomes high, and it is not possible to meet the recent needs for thin products. Further, for that reason, it is easily affected by bending, it is difficult to soften the module, and it is difficult to apply it to a shape such as a curved surface. In addition, a region for mounting the mother substrate 111 is required to mount the electronic components 109 and the carrier substrate 106, and the number of electronic components that can be mounted on one mother substrate 111 and a region for forming a circuit pattern are the mother substrate 111. Mother board 1 determined by size
It is not possible to meet the latest product requirements that require downsizing of 11. Further, since the semiconductor element 101 and the cream solder 107 are directly exposed to the air, when used in a high temperature and high humidity environment, they are likely to be oxidized, causing an electrical short circuit, an open defect, and a decrease in bonding strength. In addition, since the substrate size cannot be increased due to temperature variations in the reflow furnace, batch processing has become the mainstream, but productivity is poor.

【００１１】本発明はこのような問題点を解決する為に
なされたもので、高品質、高生産性で安価な電子部品実
装済部品の製造方法及び製造装置、電子部品実装済部
品、及び、多層積層電子部品実装済み部品の製造方法を
提供することを目的とする。The present invention has been made to solve the above problems, and is a method and a device for manufacturing an electronic component mounted component which is of high quality, high productivity and low cost, and an electronic component mounted component, and An object of the present invention is to provide a method for manufacturing a component on which a multilayer laminated electronic component is mounted.

【００１２】[0012]

【課題を解決するための手段】上記目的を達成するため
に、本発明は以下のように構成する。In order to achieve the above object, the present invention is configured as follows.

【００１３】本発明の第１態様によれば、電子部品を基
材中に埋設する工程と、上記電子部品の電極を上記基材
表面に露出させる工程とを備え、上記露出工程におい
て、研磨加工とプラズマ放電加工とのいずれか、あるい
は両方により、上記電極を上記基材表面に露出させるこ
とを特徴とする電子部品実装済み部品の製造方法を提供
する。According to the first aspect of the present invention, the method comprises the steps of burying an electronic component in a base material and exposing the electrodes of the electronic component to the surface of the base material. And a plasma electric discharge machining, or both, exposing the electrode on the surface of the base material.

【００１４】本発明の第２態様によれば、上記電子部品
を上記基材中に埋設する工程の前に、上記電子部品とし
ての半導体素子の電極パッドに突起状電極を形成した
後、上記埋設工程において、上記突起状電極を一定の高
さに揃えるかあるいは直接、上記半導体素子を基材に埋
設し、上記露出工程において、上記突起状電極を上記基
材表面に露出させる第１の態様に記載の電子部品実装済
み部品の製造方法を提供する。According to the second aspect of the present invention, prior to the step of burying the electronic component in the base material, a protruding electrode is formed on an electrode pad of a semiconductor element as the electronic component, and then the burying is performed. In the first mode, in the step, the protruding electrodes are aligned to a constant height or directly embedded in the base material, and in the exposing step, the protruding electrodes are exposed on the surface of the base material. Provided is a method for manufacturing the described electronic component-mounted component.

【００１５】本発明の第３態様によれば、上記露出工程
の後、上記基材表面に露出した上記電極上に、メッキ又
はイオンプレーティング又はスパッタリング又は蒸着に
より、回路パターン、金属薄膜コンデンサ、コイル、又
は、抵抗を形成する第１又は２の態様に記載の電子部品
実装済み部品の製造方法を提供する。According to the third aspect of the present invention, after the exposing step, a circuit pattern, a metal thin film capacitor, a coil is formed on the electrode exposed on the surface of the base material by plating, ion plating, sputtering or vapor deposition. Or a method of manufacturing a component having an electronic component mounted thereon according to the first or second aspect of forming a resistor.

【００１６】本発明の第４態様によれば、上記露出工程
の後、上記基材表面に露出した電極上に半田ペースト又
は導電性接着剤を印刷した後、高温炉又は高温ステージ
で加熱硬化することにより回路パターンを形成する第１
又は２記載の電子部品実装済み部品の製造方法を提供す
る。According to the fourth aspect of the present invention, after the exposing step, a solder paste or a conductive adhesive is printed on the electrodes exposed on the surface of the base material, and then heat-cured in a high temperature furnace or a high temperature stage. First to form a circuit pattern by
Alternatively, there is provided a method of manufacturing an electronic component-mounted component according to item 2.

【００１７】本発明の第５態様によれば、上記埋設工程
において、複数個の電子部品を一括して上記基材に埋設
し、上記露出工程の後、個片に切断する工程をさらに備
える第１から５のいずれか１つの態様に記載の電子部品
実装済み部品の製造方法を提供する。According to a fifth aspect of the present invention, in the embedding step, the method further comprises the step of embedding a plurality of electronic components in the base material together, and after the exposing step, cutting into individual pieces. A method for manufacturing an electronic component-mounted component according to any one of 1 to 5 is provided.

【００１８】本発明の第６態様によれば、第１から５の
いずれか１つの態様に記載の電子部品実装済み部品の製
造方法により電子部品実装済み部品を製造した後、この
電子部品実装済み部品の片面あるいは両面に、電子部品
実装済み部品あるいは基材を複数枚、厚み方向に積層化
し、積層化した表裏両面に保護シートを配置することに
より多層積層電子部品実装済み部品を製造する多層積層
電子部品実装済み部品の製造方法を提供する。According to the sixth aspect of the present invention, after the electronic component-mounted component is manufactured by the method for manufacturing an electronic component-mounted component according to any one of the first to fifth aspects, the electronic component-mounted component is manufactured. Multi-layer lamination to produce electronic component-mounted components by stacking multiple electronic component-mounted components or base materials on one or both sides of the component in the thickness direction and arranging protective sheets on both sides Provided is a method of manufacturing an electronic component mounted component.

【００１９】本発明の第７態様によれば、第１から５の
いずれか１つの態様に記載の電子部品実装済み部品の製
造方法により製造された電子部品実装済み部品を提供す
る。According to a seventh aspect of the present invention, there is provided an electronic component mounted component manufactured by the method for manufacturing an electronic component mounted component according to any one of the first to fifth aspects.

【００２０】本発明の第８態様によれば、基材と、研磨
加工、プラズマ放電加工のいずれかあるいは両方によ
り、上記基材表面に電極が露出された状態で、上記基材
中に埋設された電子部品とを備えることを特徴とする電
子部品実装済み部品を提供する。According to the eighth aspect of the present invention, the base material is embedded in the base material with the electrodes being exposed on the surface of the base material by one or both of polishing and plasma discharge machining. An electronic component-mounted component, characterized by comprising:

【００２１】本発明の第９態様によれば、上記基材表面
に露出した上記電極上に、メッキ又はイオンプレーティ
ング又はスパッタリング又は蒸着により形成された、回
路パターン、金属薄膜コンデンサ、コイル、又は抵抗を
さらに備えるようにした第８の態様に記載の電子部品実
装済み部品を提供する。According to a ninth aspect of the present invention, a circuit pattern, a metal thin film capacitor, a coil, or a resistor formed by plating, ion plating, sputtering or vapor deposition on the electrode exposed on the surface of the base material. An electronic component-mounted component according to the eighth aspect is further provided.

【００２２】本発明の第１０態様によれば、基材及び電
子部品を供給する電子部品供給装置と、上記電子部品及
びその電極位置及び形状を認識する認識装置と、上記電
子部品を吸引した後、上下反転する上下反転装置と、上
記電子部品を上記基材上に搭載する電子部品搭載装置
と、上記電子部品を上記基材内に埋設する電子部品埋設
装置と、プラズマ放電加工・研磨加工のいずれかあるい
は両方を用いて上記電子部品の上記電極を上記基材の表
面に露出させる電極露出装置とを備えることを特徴とす
る電子部品実装済み部品の製造装置を提供する。According to the tenth aspect of the present invention, an electronic component supply device for supplying a base material and an electronic component, a recognition device for recognizing the electronic component and its electrode position and shape, and after sucking the electronic component A vertical reversing device for reversing upside down, an electronic component mounting device for mounting the electronic component on the base material, an electronic component embedding device for embedding the electronic component in the base material, and a plasma discharge machining / polishing process. An electrode exposing device for exposing the electrode of the electronic component to the surface of the base material by using one or both of them is provided.

【００２３】[0023]

【発明の実施の形態】以下に、本発明にかかる実施の形
態を図面に基づいて詳細に説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings.

【００２４】（第１実施形態）図１（ａ）〜（ｄ）は、
本発明の第１実施形態にかかる電子部品実装済部品を製
造する工程を示す一部断面図である。この実装済み部品
製造工程は、電子部品をシート基材に埋設する工程と、
上記埋設された電子部品の電極をこのシート基材の表面
に露出させる工程とから構成されている。(First Embodiment) FIGS. 1A to 1D show
It is a partial cross section figure which shows the process of manufacturing the electronic component mounted component concerning 1st Embodiment of this invention. This mounted component manufacturing process includes a process of embedding electronic components in a sheet base material,
And a step of exposing the electrodes of the embedded electronic component to the surface of the sheet base material.

【００２５】ここでは、一例として、電子部品１は、コ
ンデンサ部品又は抵抗部品などの受動部品、半導体素
子、ＣＳＰ部品などを熱可塑性樹脂シート基材３中に埋
設する、電子部品実装済部品の一例としてのシートモジ
ュールの形成方法について説明する。Here, as an example, the electronic component 1 is an example of an electronic component mounted component in which a passive component such as a capacitor component or a resistor component, a semiconductor element, a CSP component, etc. are embedded in a thermoplastic resin sheet base material 3. A method of forming the seat module as described above will be described.

【００２６】熱可塑性樹脂シート基材３は、例えば、ポ
リエチレンテレフタレート、塩化ビニル、ポリカーボネ
イト、アクリルニトリルブタジエンスチレン、又は、熱
可塑性ポリイミド等の、電気的絶縁性を有し、その厚さ
が１０μｍ〜１ｍｍであることが望ましい。The thermoplastic resin sheet base material 3 has electrical insulation such as polyethylene terephthalate, vinyl chloride, polycarbonate, acrylonitrile butadiene styrene, or thermoplastic polyimide, and has a thickness of 10 μm to 1 mm. Is desirable.

【００２７】図１（ａ）〜（ｂ）は、電子部品１を熱可
塑性樹脂シート基材３に埋設する工程の一例を示す一部
断面図である。なお、電子部品１の熱可塑性樹脂シート
基材３への埋設はこの方法によらず、他の方法で行うよ
うにしてもよい。FIGS. 1A and 1B are partial cross-sectional views showing an example of the step of burying the electronic component 1 in the thermoplastic resin sheet base material 3. Note that the embedding of the electronic component 1 in the thermoplastic resin sheet base material 3 may be performed by another method instead of this method.

【００２８】図１（ａ）は、電子部品１を熱可塑性樹脂
シート基材３に埋設する前の状態を示す一部断面図であ
り、加熱ステージ５上に熱可塑性樹脂シート基材３を置
き、熱可塑性樹脂シート基材３の上に、複数の電極２を
有する電子部品１を置いている。その電子部品１の上方
に、プレスツール４を配置する。なお、加熱ステージ５
及びプレスツール４の表面は、ガラス、ステンレス、セ
ラミックス、又は、テフロン（登録商標）などで平面状
であることが望ましい。図中には示していないが、電子
部品１の一例としてのコンデンサ部品１とプレスツール
４との間、あるいはシート基材３と加熱ステージ５の間
には、ガラス板、セラミック板やテフロン（登録商標）
シートなどの基材を介しても構わない。このように基材
を介する理由は、熱可塑性樹脂シート基材３は、そのガ
ラス転移点以上に加熱するとゲル状化しかつ粘性を有す
るため、加熱ツール４やステージ５に付着して離れなく
なるためである。そのまま冷却すると、硬化収縮し、さ
らに離れにくくなる。そのために、離型材としてテフロ
ン（登録商標）などの材料の基材を介することが望まし
い。例えば、電子部品１の一例としての１８０μｍの半
導体素子を、基材の一例としてのポリエステルテレフタ
レートに埋設するときは、厚さ５０μｍ〜１００μｍの
テフロン（登録商標）シートを介することが望ましい。
このように基材を介する理由は、ポリエステルテレフタ
レートのガラス転移点は１２０℃であり、その際、加熱
ツールは２００℃まで上がる。耐熱性の観点から、ポリ
テトラフルオロエチレンが望ましい。なお、その厚さが
厚すぎると半導体素子が熱可塑性基材ではなく、離型紙
の方に埋め込まれてしまう。また、薄過ぎると半導体素
子裏面に接触時離型紙が破れる可能性がある。高さ０．
０４０ｍｍの突起状電極を有する０．１８０ｍｍ厚の半
導体素子を０．２００ｍｍ厚のＰＥＴシート基材に埋め
込む際、テフロン（登録商標）は０．０５０から０．１
００ｍｍ厚が適正であった。FIG. 1A is a partial cross-sectional view showing a state before the electronic component 1 is embedded in the thermoplastic resin sheet base material 3, and the thermoplastic resin sheet base material 3 is placed on the heating stage 5. An electronic component 1 having a plurality of electrodes 2 is placed on a thermoplastic resin sheet base material 3. The press tool 4 is arranged above the electronic component 1. The heating stage 5
The surface of the press tool 4 is preferably flat such as glass, stainless steel, ceramics, or Teflon (registered trademark). Although not shown in the drawing, a glass plate, a ceramic plate, or a Teflon (registered) is provided between the capacitor component 1 as an example of the electronic component 1 and the press tool 4, or between the sheet base material 3 and the heating stage 5. Trademark)
A base material such as a sheet may be used. The reason for interposing the base material in this way is that the thermoplastic resin sheet base material 3 becomes a gel and has a viscosity when heated above its glass transition point, so that the thermoplastic resin sheet base material 3 adheres to the heating tool 4 and the stage 5 and does not separate. is there. If it is cooled as it is, it will cure and shrink, making it more difficult to separate. Therefore, it is desirable to interpose a base material made of a material such as Teflon (registered trademark) as a release material. For example, when embedding a 180 μm semiconductor element as an example of the electronic component 1 in polyester terephthalate as an example of a base material, it is desirable to interpose a Teflon (registered trademark) sheet having a thickness of 50 μm to 100 μm.
The reason for passing through the substrate in this way is that the glass transition point of polyester terephthalate is 120 ° C., at which time the heating tool rises to 200 ° C. From the viewpoint of heat resistance, polytetrafluoroethylene is desirable. If the thickness is too large, the semiconductor element will be embedded in the release paper instead of the thermoplastic substrate. Further, if it is too thin, the release paper may break when coming into contact with the back surface of the semiconductor element. Height 0.
When embedding a 0.180 mm thick semiconductor device having a 040 mm protruding electrode in a 0.200 mm thick PET sheet substrate, Teflon (registered trademark) may be used in a range of 0.050 to 0.10.
A thickness of 00 mm was appropriate.

【００２９】埋設工程では、加熱したプレスツール４を
加熱ステージ５に向けて任意の荷重をかけながら電子部
品１を熱可塑性樹脂シート基材３内に押し込むことによ
り、電子部品１を熱可塑性樹脂シート基材３中に埋設す
る。この状態では、プレスツール４に接触した電子部品
１の裏面１ｒがシート基材３の裏面３ｒと大略同一面を
形成している。In the embedding step, the electronic component 1 is pushed into the thermoplastic resin sheet base material 3 while the heated press tool 4 is directed toward the heating stage 5 and an arbitrary load is applied, so that the electronic component 1 is made into the thermoplastic resin sheet. It is embedded in the base material 3. In this state, the back surface 1r of the electronic component 1 that is in contact with the press tool 4 forms substantially the same surface as the back surface 3r of the sheet base material 3.

【００３０】図１（ｂ）は、電子部品１が熱可塑性樹脂
シート基材３中に埋設された状態を示す。なお、電子部
品１の埋め込み中の熱可塑性樹脂シート基材３を加熱す
るとき、その加熱温度が、熱可塑性樹脂シート基材３の
ガラス転移点と、熱可塑性樹脂シート基材３の粘度が下
がりかつ電子部品１が熱可塑性樹脂シート基材３を貫通
する上限温度との間となるように、熱可塑性樹脂シート
基材３を加熱することが望ましい。例えば、電子部品が
０．３ｍｍ×０．６ｍｍ×０．３ｍｍのチップコンデン
サをポリエチレンテレフタレートのシート基材に埋め込
む場合には、そのポリエチレンテレフタレートのシート
基材の厚さは０．３〜０．４ｍｍ、埋め込み時の樹脂温
度は１５０〜１７０℃、荷重４０〜５０ｋｇｆ（３９
２．４〜４９０．５Ｎ）、プレス時間２０ｓ〜１５０ｓ
であることが望ましい。FIG. 1B shows a state in which the electronic component 1 is embedded in the thermoplastic resin sheet base material 3. When the thermoplastic resin sheet base material 3 during the embedding of the electronic component 1 is heated, the heating temperature lowers the glass transition point of the thermoplastic resin sheet base material 3 and the viscosity of the thermoplastic resin sheet base material 3. Further, it is desirable to heat the thermoplastic resin sheet base material 3 so that the electronic component 1 has a temperature between the upper limit temperature at which the electronic component 1 penetrates the thermoplastic resin sheet base material 3. For example, when a 0.3 mm × 0.6 mm × 0.3 mm chip capacitor for an electronic component is embedded in a polyethylene terephthalate sheet base material, the thickness of the polyethylene terephthalate sheet base material is 0.3 to 0.4 mm. , The resin temperature at the time of embedding is 150 to 170 ° C., and the load is 40 to 50 kgf (39
2.4 ~ 490.5N), press time 20s ~ 150s
Is desirable.

【００３１】次いで、プレスツール４を引き上げ、電子
部品１が埋設されたシート基材３を加熱ステージ５から
剥離し、室温まで冷却することにより、シート基材３は
硬化し、シート基材３に電子部品１が埋設される。Next, the press tool 4 is pulled up, the sheet base material 3 in which the electronic component 1 is embedded is peeled off from the heating stage 5, and cooled to room temperature, whereby the sheet base material 3 is cured and the sheet base material 3 is formed. The electronic component 1 is embedded.

【００３２】しかし、この時点では、シート基材３内に
埋設された電子部品１の電極２がシート基材３を突き破
ってそのシート表面に露出しておらず、プレスツール４
に接触した電子部品１の裏面１ｒがシート基材３の裏面
３ｒと大略同一面を形成しているだけであり、シート面
の片面（すなわち、この場合には電子部品１の裏面１
ｒ）しかシート基材３の裏面３ｒ側の表面に露出してお
らず、電子部品１の表面１ｆ側の電極２との接続を取る
ことができない。例えば、前記した例では、電極からシ
ート基材３の表面までの距離は最大で０．４ｍｍ−０．
３ｍｍ＝０．１ｍｍ＝１００μｍになる。また、ＩＣチ
ップなどのように片面（すなわちＩＣチップ表面）だけ
電極を持つ電子部品の場合、ＩＣチップ裏面からは導通
をとれないため、シート基材３のいずれの面からも電気
的接続を得ることができない。However, at this time, the electrode 2 of the electronic component 1 embedded in the sheet base material 3 has not penetrated the sheet base material 3 and is not exposed on the sheet surface, and the press tool 4
The back surface 1r of the electronic component 1 that is in contact with the back surface 3r is substantially the same as the back surface 3r of the sheet base material 3, and only one side of the sheet surface (that is, the back surface 1r of the electronic component 1 in this case).
Only r) is exposed on the surface of the sheet base material 3 on the back surface 3r side, and connection with the electrode 2 on the front surface 1f side of the electronic component 1 cannot be established. For example, in the above-described example, the maximum distance from the electrode to the surface of the sheet base material 3 is 0.4 mm-0.
It becomes 3 mm = 0.1 mm = 100 μm. Further, in the case of an electronic component such as an IC chip having an electrode only on one surface (that is, the front surface of the IC chip), since electrical continuity cannot be established from the back surface of the IC chip, electrical connection is obtained from any surface of the sheet base material 3. I can't.

【００３３】そこで、露出工程において、研磨加工又は
プラズマ放電加工あるいはその両方を用いて、電極２を
シート基材３の表面に露出させる。Therefore, in the exposing step, the electrode 2 is exposed on the surface of the sheet base material 3 by polishing or plasma discharge machining or both.

【００３４】図１（ｃ）は、研磨加工を説明する一部断
面図である。電子部品１を埋設したシート基材３を研磨
加工用ステージ１０に対して固定用ジグの使用、吸引な
どにより固定する。研磨機６により研磨紙７をシート基
材３の電極２を露出させたい面に押し当て、回転あるい
は水平動作させ、シート基材３を研磨する。＃８０、＃
１００、＃１５０、＃５００、＃８００、＃１０００、
＃１２００、＃１５００、＃２０００の順に徐々に細
目の研磨紙を用いてシート基材３を研磨した後、１μ
ｍ、０．５μｍ、０．３μｍと徐々に小さい粒径のセラ
ミックス粉（アルミナなど）でシート基材３をバフ研磨
することが望ましい。なお、研磨紙の粗さ、粉末径は必
ずしもこれらすべてを用いる必要は無く、これらの値以
外の粗さ及び粉末径であっても構わない。また、研磨時
に研磨粉を除去するために水や有機溶剤を用いることが
望ましい。このように研磨することにより、複数の電極
２をシート基材３の表面に露出させる。FIG. 1C is a partial sectional view for explaining the polishing process. The sheet base material 3 in which the electronic component 1 is embedded is fixed to the polishing stage 10 by using a fixing jig or suction. The polishing paper 6 is pressed against the surface of the sheet base material 3 where the electrode 2 is to be exposed by the polishing machine 6 and is rotated or horizontally operated to polish the sheet base material 3. # 80, #
100, # 150, # 500, # 800, # 1000,
Gradually grind the sheet base material 3 with # 1200, # 1500, and # 2000 in order of 1 μm, and then 1 μ
It is desirable that the sheet base material 3 be buffed with a ceramic powder (alumina or the like) having a gradually decreasing particle size of m, 0.5 μm, and 0.3 μm. It should be noted that the roughness and the powder diameter of the polishing paper do not necessarily have to be all of these, and the roughness and the powder diameter other than these values may be used. Further, it is desirable to use water or an organic solvent to remove the polishing powder during polishing. By polishing in this manner, the plurality of electrodes 2 are exposed on the surface of the sheet base material 3.

【００３５】また、図１（ｄ）は、プラズマ放電加工を
説明する一部断面図である。電子部品１が実装されたシ
ート基材３を真空炉の真空チャンバー９内に入れて真空
チャンバー９中のプラズマ放電用下側電極１２に固定
し、真空チャンバー９内の真空引きを行って減圧状態と
し、Ａｒなどの不活性ガスを真空チャンバー９内に導入
し、プラズマ放電用上側電極１１とプラズマ放電用下側
電極１２との間に高電圧を印加し、真空チャンバー９内
の上側電極１１と下側電極１２との間でプラズマを発生
させてプラズマエッチングさせる。なお、プラズマを局
所的に集中して発生させるために磁場などを同時に用い
ても構わない。プラズマがシート基材３の粒子をたたき
出し、シート基材３をその厚み方向に削っていく。Further, FIG. 1D is a partial sectional view for explaining the plasma electric discharge machining. The sheet base material 3 on which the electronic component 1 is mounted is put in the vacuum chamber 9 of the vacuum furnace, fixed to the lower electrode 12 for plasma discharge in the vacuum chamber 9, and the vacuum chamber 9 is evacuated to reduce the pressure. Then, an inert gas such as Ar is introduced into the vacuum chamber 9, and a high voltage is applied between the upper electrode 11 for plasma discharge and the lower electrode 12 for plasma discharge. Plasma is generated between the lower electrode 12 and the lower electrode 12 for plasma etching. Note that a magnetic field or the like may be used at the same time in order to locally generate plasma. The plasma knocks out the particles of the sheet base material 3 and scrapes the sheet base material 3 in the thickness direction.

【００３６】上記露出工程での電極露出方法の具体例と
しては、（１）シート基材３に対して電極２が露出する
まですべて研磨加工で行う、（２）シート基材３に対し
て電極２が露出するまですべてプラズマ加工を行う、
（３）シート基材３に対して研磨加工により粗く削り、
最後の仕上げはプラズマ放電加工を用いて、電極２をさ
せる、（４）シート基材３に対して研磨加工により全体
を削り、電極２の近傍のみプラズマ放電加工を行うなど
の組み合わせ方法が挙げられる。Specific examples of the electrode exposing method in the exposing step include (1) polishing processing until the electrode 2 is exposed on the sheet base material 3, (2) electrode on the sheet base material 3 Plasma processing is performed until 2 is exposed,
(3) Roughly scraping the sheet base material 3 by polishing,
For the final finishing, there can be mentioned a combination method in which the electrodes 2 are formed by using plasma electric discharge machining, (4) the sheet base material 3 is entirely ground by polishing, and plasma electric discharge machining is performed only in the vicinity of the electrodes 2. .

【００３７】このような方法を用いると、（１）一括で
複数個の電極２を露出させることが可能となり、生産タ
クトが向上する、（２）加工後のシート表面が平面であ
るため、シート表面への印刷、膜形成やシートモジュー
ルの積層化、カード化などが容易になる、などのメリッ
トがあり、実用的である。When such a method is used, (1) it is possible to expose a plurality of electrodes 2 at a time, which improves the production takt time. (2) Since the sheet surface after processing is flat, the sheet It is practical because it has advantages such as easy printing on the surface, film formation, lamination of sheet modules, and carding.

【００３８】従って、第１実施形態によれば、電子部品
１がシート基材３に埋設されているため、シートモジュ
ールの厚みを小さくすることができて薄型化が可能とな
る。さらに、薄いために従来の基板よりも軟らかく、曲
面や曲げ動作を行う場所で使用することができる。さら
に、電子部品１の一例としてＩＣチップをシート基材３
に内蔵させる場合には、基板すなわちシート基材３の表
面への膜形成領域及び回路パターン形成領域を大きくす
ることができ、高機能化が可能となるとともに、基板サ
イズの小型化も可能となる。Therefore, according to the first embodiment, since the electronic component 1 is embedded in the sheet base material 3, the thickness of the sheet module can be reduced and the thickness can be reduced. Further, since it is thin, it is softer than the conventional substrate and can be used in a curved surface or a place where a bending operation is performed. Further, as an example of the electronic component 1, an IC chip is used as the sheet base material 3
When it is built in the substrate, the film forming region and the circuit pattern forming region on the surface of the substrate, that is, the sheet base material 3 can be increased, and high functionality can be achieved and the substrate size can be reduced. .

【００３９】（第２実施形態）電子部品は、第１実施形
態ではコンデンサ部品、抵抗等の受動部品のチップ型部
品を例にとったが、半導体素子であっても構わない。本
発明の第２実施形態では電子部品として半導体素子を例
にとり、図２を用いて、電子部品実装済部品の一例とし
ての半導体素子実装済み部品の製造工程について説明す
る。(Second Embodiment) In the first embodiment, the electronic component is a chip-type component such as a capacitor component or a passive component such as a resistor, but it may be a semiconductor element. In the second embodiment of the present invention, a semiconductor element is taken as an example of an electronic component, and a manufacturing process of a semiconductor element-mounted component as an example of an electronic component-mounted component will be described with reference to FIG.

【００４０】この半導体素子実装済み部品の製造方法
は、まず、半導体素子の電極パッドに突起状電極を形成
する。次に、その突起状電極の高さを揃え、その半導体
素子をシート基材に埋め込んだ後、シート基材の表面に
その突起状電極表面を露出させることにより大略構成し
ている。なお、突起状電極の高さを揃える（レベリン
グ）工程は省いてもよい。以下、各工程の詳細について
図２（ａ）から図２（ｄ）を用いて説明する。In this method for manufacturing a semiconductor element-mounted component, first, a protruding electrode is formed on the electrode pad of the semiconductor element. Next, the height of the projecting electrodes is made uniform, the semiconductor element is embedded in a sheet base material, and then the surface of the projecting electrode is exposed on the surface of the sheet base material. The step of aligning the heights of the protruding electrodes (leveling) may be omitted. Hereinafter, the details of each step will be described with reference to FIGS. 2A to 2D.

【００４１】図２（ａ）は、半導体素子１３に複数の突
起状電極１５を形成する工程を示す一部断面図である。
まず、金又はアルミニウムなどから成る表面層を有する
平面の金属電極パッド１４を複数個有する半導体素子１
３をステージ１７上に置き、図示していない固定用ジグ
や吸引などの方法によりステージ１７に固定する。次
に、金又はアルミニウムなどの金属細線７０を電極形成
用ジグ１６に通し、そのジグ１６の先端から出た金属細
線７０を放電して球状部を形成した後、その金属細線７
０の球状部を電極パッド１４に熱、荷重、及び、超音波
を印加しながら、押し当てる。その後、ジグ１６を引き
上げると、金属細線７０の球状部のうち再結晶化した領
域とアモルファス状態の領域との境界近傍で金属細線７
０が破断し、半導体素子１３の電極パッド１４には、突
起状電極１５が形成される。なお、メッキやクリーム半
田の印刷・溶融・硬化などにより突起状電極１５を形成
しても構わない。FIG. 2A is a partial cross-sectional view showing a step of forming a plurality of projecting electrodes 15 on the semiconductor element 13.
First, a semiconductor device 1 having a plurality of flat metal electrode pads 14 having a surface layer made of gold or aluminum
3 is placed on the stage 17 and fixed to the stage 17 by a fixing jig or a suction method (not shown). Next, a metal thin wire 70 such as gold or aluminum is passed through the electrode forming jig 16, the metal thin wire 70 protruding from the tip of the jig 16 is discharged to form a spherical portion, and then the metal thin wire 7 is formed.
The spherical portion of 0 is pressed against the electrode pad 14 while applying heat, load, and ultrasonic waves. Then, when the jig 16 is pulled up, the metal fine wire 7 is formed near the boundary between the recrystallized region and the amorphous region of the spherical portion of the metal fine wire 70.
0 breaks, and protruding electrodes 15 are formed on the electrode pads 14 of the semiconductor element 13. The protruding electrodes 15 may be formed by printing, melting, curing, etc. of plating or cream solder.

【００４２】図２（ｂ）は、レベリング工程を示す一部
断面図である。前工程で形成された複数の突起状電極１
５を有する半導体素子１３をステージ１９に固定し、全
ての突起状電極１５の上からレベリング用ツール１８で
荷重を印加しながら一定量押し込む。それにより、全て
の突起状電極１５の高さを一定に揃えることができる。
ステージ１９の半導体素子１３の固定面及びレベリング
用ツール１８の全ての突起状電極１５の接触面は平面と
なっている。FIG. 2B is a partial sectional view showing the leveling step. Plural protruding electrodes 1 formed in the previous step
The semiconductor element 13 having 5 is fixed to the stage 19, and a certain amount of the protruding electrodes 15 are pushed in while applying a load with the leveling tool 18. Thereby, the heights of all the protruding electrodes 15 can be made uniform.
The fixed surface of the semiconductor element 13 of the stage 19 and the contact surfaces of all the protruding electrodes 15 of the leveling tool 18 are flat.

【００４３】図２（ｃ）及び（ｄ）は半導体素子１３を
シート基材３に埋め込む工程、図２（ｅ）及び（ｆ）は
シート基材３に半導体素子１３の電極露出工程を示す一
部断面図である。これらの工程は、第１実施形態の図１
（ａ）及び（ｂ）並びに図１（ｃ）及び（ｄ）とそれぞ
れ同じ手法が用いられる。2C and 2D show a step of embedding the semiconductor element 13 in the sheet base material 3, and FIGS. 2E and 2F show an electrode exposing step of the semiconductor element 13 on the sheet base material 3. FIG. These steps are similar to those of the first embodiment shown in FIG.
The same methods as in (a) and (b) and FIGS. 1 (c) and (d) are used, respectively.

【００４４】この半導体素子実装済み部品の製造方法の
より具体的な例としては、一辺が８０μｍの正方形のＡ
ｌメッキされたランドを２〜１０個有する外形２ｍｍＸ
１．８ｍｍ、 厚さ０．１８ｍｍの半導体素子１３の一
例であるＩＣチップに、Ａｕの突起状電極を形成する場
合、直径２５μｍの金線を用い、電流値３０．０ｍＡ、
放電時間２．０ｍｓ、超音波出力１５０ｍＷ、接合温度
１５０℃、ボンド（接合）荷重７０ｇの条件が望まし
い。この条件では、バンプ高さが６０〜８０μｍになる
が、レベリングにより４０〜６０μｍに揃えた後、厚さ
１９０〜２１０μｍのポリエチレンテレフタレートのシ
ート基材に埋め込むとき、樹脂温度は１５０〜１７０
℃、荷重４０〜５０ｋｇｆ（３９２．４〜４９０．５
Ｎ）、プレス時間２０ｓ〜１５０ｓで埋め込む。する
と、電極先端からポリエチレンテレフタレートまでの距
離が最大１０μｍになる。その後、プラズマエッチング
や研磨により電極をシート基材表面に露出させる。As a more specific example of the method for manufacturing the semiconductor element mounted component, a square A having a side of 80 μm is used.
l 2mmX with 2 to 10 plated lands
When an Au protruding electrode is formed on an IC chip which is an example of the semiconductor element 13 having a thickness of 1.8 mm and a thickness of 0.18 mm, a gold wire having a diameter of 25 μm is used, and a current value of 30.0 mA,
It is desirable that the discharge time is 2.0 ms, the ultrasonic output is 150 mW, the bonding temperature is 150 ° C., and the bond (bonding) load is 70 g. Under this condition, the bump height is 60 to 80 μm, but when the bumps are aligned to 40 to 60 μm by leveling and then embedded in a polyethylene terephthalate sheet base material having a thickness of 190 to 210 μm, the resin temperature is 150 to 170 μm.
℃, load 40-50kgf (392.4-490.5
N), the embedding time is 20 s to 150 s. Then, the distance from the tip of the electrode to the polyethylene terephthalate becomes 10 μm at maximum. After that, the electrode is exposed on the surface of the sheet base material by plasma etching or polishing.

【００４５】上記第２実施形態によれば、半導体素子１
３がシート基材３に埋設されているため、半導体素子実
装済み部品であるシートモジュールの厚みを小さくする
ことができて薄型化が可能となる。さらに、シートモジ
ュールが薄くなるため、従来の基板よりも軟らかく、曲
面や曲げ動作を行う場所で使用することができる。さら
に、半導体素子１３がシート基材３に内蔵されているた
め、基板すなわちシート基材３の表面への膜形成領域及
び回路パターン形成領域を大きくすることができ、高機
能化が可能となるとともに、基板サイズの小型化も可能
となる。According to the second embodiment, the semiconductor device 1
Since 3 is embedded in the sheet base material 3, it is possible to reduce the thickness of the sheet module, which is a component on which semiconductor elements have been mounted, and to reduce the thickness. Further, since the sheet module is thin, it is softer than the conventional substrate and can be used in a curved surface or a place where a bending operation is performed. Further, since the semiconductor element 13 is built in the sheet base material 3, the film forming area and the circuit pattern forming area on the surface of the substrate, that is, the sheet base material 3 can be increased, and high functionality can be achieved. Also, the substrate size can be reduced.

【００４６】(第３実施形態)本発明の第３実施形態にか
かる電子部品実装済部品の製造方法について図３に基き
説明する。(Third Embodiment) A method of manufacturing an electronic component-mounted component according to a third embodiment of the present invention will be described with reference to FIG.

【００４７】図３は、電子部品実装済み部品の一例とし
てシートモジュールを示した一部断面図及び平面図であ
る。このシートモジュールは、ＮＣパンチャーやレーザ
などで空けた穴の周囲をメッキや導電性ペーストで電気
的導通をとった導通用貫通穴（スルーホール）４８を有
しかつ電気的絶縁性を有する熱可塑性樹脂シート基材３
Ｄに、第２実施形態と同様の方法で形成された突起状電
極１５を複数個有する半導体素子１３を埋め込む。その
後、研磨加工やプラズマ放電加工で複数個の突起状電極
１５を露出させる。次いで、突起状電極１５にそれぞれ
接続されるように、薄膜コンデンサ４６やコイル４７を
形成したものである。なお、導通用貫通穴４８は、製品
であるシートモジュールが片面（ここでは突起状電極１
５が露出された面）だけで機能を果たす場合には必要な
い。また、薄膜コンデンサ４６は、誘電体膜を介して突
起状電極１５を覆うように２種類の導電膜をスパッタリ
ングや蒸着でシート基材３Ｄに形成することにより製造
される。コイル４７は、クリーム半田や導電性ペースト
をマスクスキージを用いてシート基材３Ｄに印刷した
り、メッキ後にフォトリソグラフィを行うことによりシ
ート基材３Ｄに作製される。なお、シート基材３Ｄに薄
膜抵抗を形成しても構わない。すなわち、回路パター
ン、金属薄膜コンデンサ４６、コイル４７、又は、抵抗
は、シート基材３Ｄに対して、メッキ又はイオンプレー
ティング又はスパッタリング又は蒸着により形成するこ
とができる。また、回路パターンは、上記基材表面に露
出した電極上に半田ペースト又は導電性接着剤を印刷し
た後、高温炉又は高温ステージで加熱硬化することによ
り形成することができる。FIG. 3 is a partial cross-sectional view and a plan view showing a sheet module as an example of the electronic component-mounted component. This sheet module has a through hole for conduction (through hole) 48 which is electrically conducted by plating or a conductive paste around a hole made by an NC puncher or a laser and has an electrically insulating thermoplastic property. Resin sheet base material 3
A semiconductor element 13 having a plurality of protruding electrodes 15 formed by the same method as in the second embodiment is embedded in D. After that, a plurality of protruding electrodes 15 are exposed by polishing or plasma discharge machining. Next, the thin film capacitor 46 and the coil 47 are formed so as to be connected to the protruding electrodes 15, respectively. The conduction through hole 48 is provided on one side of the sheet module as a product (here, the protruding electrode 1
It is not necessary when the function is performed only on the exposed surface (5). The thin film capacitor 46 is manufactured by forming two kinds of conductive films on the sheet base material 3D by sputtering or vapor deposition so as to cover the protruding electrodes 15 with the dielectric film interposed therebetween. The coil 47 is produced on the sheet base material 3D by printing cream solder or a conductive paste on the sheet base material 3D using a mask squeegee or by performing photolithography after plating. Note that a thin film resistor may be formed on the sheet base material 3D. That is, the circuit pattern, the metal thin film capacitor 46, the coil 47, or the resistor can be formed on the sheet base material 3D by plating, ion plating, sputtering, or vapor deposition. In addition, the circuit pattern can be formed by printing a solder paste or a conductive adhesive on the electrodes exposed on the surface of the base material and then heating and curing the solder paste in a high temperature furnace or a high temperature stage.

【００４８】この第３実施形態によれば、上記第２実施
形態の作用効果に加えて、半導体素子１３がシート基材
３Ｄに内蔵されているため、基板すなわちシート基材３
Ｄの表面への膜形成領域及び回路パターン形成領域（例
えば、薄膜コンデンサ４６やコイル４７を形成する領
域）を大きくすることができ、高機能化が可能となると
ともに、基板サイズの小型化も可能となる。According to the third embodiment, in addition to the effects of the second embodiment, the semiconductor element 13 is built in the sheet base material 3D, so that the substrate, that is, the sheet base material 3 is formed.
The film forming area and the circuit pattern forming area (for example, the area where the thin film capacitor 46 and the coil 47 are formed) on the surface of D can be increased, which enables high functionality and downsizing of the substrate size. Becomes

【００４９】上記第３実施形態の変形例として、図４
（ａ）〜（ｄ）は、このモジュールを９個同時に作製し
た場合の電子部品実装済み部品の製造工程を示す一部断
面図と平面図である。この変形例で使用する電気的絶縁
性を有する熱可塑性樹脂シート基材３Ｅは、９個の個別
モジュール用領域３ｚを一体的に形成したものであり、
各個別モジュール用領域３ｚは上記シート基材３Ｄに対
応する。各個別モジュール用領域３ｚには、導通用貫通
穴（スルーホール）４８を有している。As a modified example of the third embodiment, FIG.
(A)-(d) is a partial cross section figure and top view which show the manufacturing process of the electronic component mounted component at the time of manufacturing this 9 modules simultaneously. An electrically insulating thermoplastic resin sheet base material 3E used in this modification has nine individual module regions 3z integrally formed,
Each individual module region 3z corresponds to the sheet base material 3D. Each individual module region 3z has a through hole 48 for conduction.

【００５０】この電子部品実装済み部品の製造工程は、
９個のＩＣチップ１３を、電気的絶縁性を有する熱可塑
性樹脂シート基材３Ｅの９個の個別モジュール用領域３
ｚ中に一括して埋め込む工程と、各ＩＣチップ１３の電
極１５を研磨加工やプラズマ加工によりシート基材３Ｅ
の表面に露出させる工程と、そのシート基材３Ｅへの導
電接着剤の印刷、金属膜の成膜などによる回路パターン
形成工程と、モジュール毎に個片に切断する工程とから
成る。The manufacturing process of this electronic component mounted component is as follows:
The nine IC chips 13 are connected to the nine individual module regions 3 of the thermoplastic resin sheet base material 3E having electrical insulation properties.
The step of embedding in the z at once and the electrode 15 of each IC chip 13 by polishing or plasma processing
A step of exposing the surface of the sheet base material 3E, a step of forming a circuit pattern by printing a conductive adhesive on the sheet base material 3E, a film formation of a metal film, and the like, and a step of cutting each module into individual pieces.

【００５１】上記９個のＩＣチップ１３を一括して埋め
込む工程は、基本的には第２実施形態従って第１実施形
態と同様の方法で行い、９個のＩＣチップ１３がプレス
ツール４に接触し、加熱ステージ５に向けて任意の荷重
をかけながら、９個のＩＣチップ１３をプレスツール４
により同時的にシート基材３Ｅの９個の個別モジュール
用領域３ｚ内に押し込むことにより、９個のＩＣチップ
１３をシート基材３Ｅ中に一括して同時的に埋設する。
次いで、プレスツール４を引き上げ、９個のＩＣチップ
１３が埋設されたシート基材３Ｅを加熱ステージ５から
剥離し、室温まで冷却することにより、シート基材３Ｅ
は硬化し、シート基材３Ｅに９個のＩＣチップ１３が埋
設されてる。The step of embedding the nine IC chips 13 at once is basically performed by the same method as in the second embodiment and the first embodiment, and the nine IC chips 13 come into contact with the press tool 4. Then, the nine IC chips 13 are pressed by the press tool 4 while applying an arbitrary load toward the heating stage 5.
Thus, by simultaneously pushing into the nine individual module regions 3z of the sheet base material 3E, the nine IC chips 13 are simultaneously embedded in the sheet base material 3E at the same time.
Then, the press tool 4 is pulled up, the sheet base material 3E in which the nine IC chips 13 are embedded is peeled off from the heating stage 5, and cooled to room temperature to obtain the sheet base material 3E.
Is cured, and nine IC chips 13 are embedded in the sheet base material 3E.

【００５２】また、上記電極露出工程は、基本的には第
２実施形態従って第１実施形態と同様の方法で行い、各
ＩＣチップ１３の複数個の電極１５を研磨加工やプラズ
マ加工によりシート基材３Ｅの表面に同時的に一括して
露出させる。The electrode exposing step is basically performed by the same method as that of the second embodiment and the first embodiment, and the plurality of electrodes 15 of each IC chip 13 are subjected to polishing or plasma processing to form a sheet substrate. The surface of the material 3E is simultaneously exposed at once.

【００５３】さらに、上記回路パターン形成工程は、基
本的には第２実施形態と同様の方法で行い、そのシート
基材３Ｅへの導電接着剤の印刷、金属膜の成膜などによ
り一括して回路パターンを同時的に形成する。Further, the above-mentioned circuit pattern forming step is basically carried out in the same manner as in the second embodiment, and the sheet base material 3E is collectively printed by printing a conductive adhesive, forming a metal film, and the like. Circuit patterns are formed simultaneously.

【００５４】上記切断工程は、個別モジュール用領域３
ｚ毎に、言い替えれば、個別モジュール毎に、個片に切
断する。この個片切断は、ダイシング機、又は、レーザ
などを用いることが望ましい。なお、５０はモジュール
毎に個片に切断するときの仮想切断線である。The cutting step is performed in the individual module area 3
Each z, in other words, each individual module is cut into individual pieces. It is desirable to use a dicing machine, a laser, or the like for this individual piece cutting. In addition, 50 is a virtual cutting line when cutting into individual pieces for each module.

【００５５】上記第３実施形態の変形例によれば、上記
第３実施形態の作用効果に加えて、従来のバッチ処理に
対して、多数の半導体素子１３を一括して埋設すること
が可能で、かつ、多数の半導体素子１３の突起状電極１
５の露出を一括してすることが可能になるため、生産性
が向上するといった効果がある。According to the modification of the third embodiment, in addition to the effects of the third embodiment, it is possible to embed a large number of semiconductor elements 13 in a batch in comparison with the conventional batch processing. And the protruding electrodes 1 of a large number of semiconductor elements 13
Since it is possible to expose the wafers 5 at a time, there is an effect that productivity is improved.

【００５６】(第４実施形態)本発明の第４実施形態にか
かる多層積層電子部品実装済み部品の製造方法を以下に
説明する。(Fourth Embodiment) A method of manufacturing a multi-layer laminated electronic component-mounted component according to a fourth embodiment of the present invention will be described below.

【００５７】この製造方法では、先の実施形態にかかる
電子部品実装済み部品の製造方法により電子部品の一例
である半導体素子１３を、電気的絶縁性を有する熱可塑
性樹脂シート基材３Ｆに埋設した後、研磨加工やプラズ
マ加工により突起状電極１５をシート基材３Ｆの表面に
露出させ、その後、回路パターン、薄膜抵抗、薄膜コン
デンサ４６などをシート基材３Ｆの表面又は表面及び裏
面に形成してシートモジュール４９を形成する。その
後、そのシートモジュール４９を複数個重ねてプレス
し、ラミネートするようにしている。In this manufacturing method, the semiconductor element 13, which is an example of an electronic component, is embedded in the electrically insulating thermoplastic resin sheet base material 3F by the method of manufacturing an electronic component-mounted component according to the previous embodiment. After that, the protruding electrodes 15 are exposed on the surface of the sheet base material 3F by polishing or plasma processing, and then a circuit pattern, a thin film resistor, a thin film capacitor 46 and the like are formed on the front surface or the front and back surfaces of the sheet base material 3F. The seat module 49 is formed. After that, a plurality of the sheet modules 49 are stacked and pressed to be laminated.

【００５８】具体的には、図５は、研磨加工又はプラズ
マ加工により、半導体素子の電極を露出した半導体素子
実装済みのシートモジュール４９を積層化し、ラミネー
トする方法を説明するためのシートモジュールなどの一
部断面図である。電気的貫通穴４８を有する熱可塑性樹
脂シート基材３Ｆは、半導体素子１３を埋設し、その
後、半導体素子１３の突起状電極１５は研磨加工又はプ
ラズマ加工によりそのシート基材３Ｆの表面に露出させ
る。次いで、突起状電極１５上に薄膜コンデンサ４６及
び導電性ペーストによるコイル４７を形成してある。シ
ート基材３Ｆの裏面には、半導体素子１９を有しかつ電
気的絶縁性を有するとともに、突起状電極１５上に薄膜
コンデンサ２２及び導電性ペーストによるコイル２１が
形成されている熱可塑性樹脂シート基材３Ｇを電気的接
合が取れるように位置合わせをする。次いで、両面に電
気的絶縁性を有する保護シート２３，２４を重ね、厚み
方向に積層化し、上下から上下ロール４０，４１により
ロールプレスを行う。それにより、積層化電子部品内蔵
モジュールが形成される。Specifically, FIG. 5 shows a sheet module or the like for explaining a method of laminating and laminating sheet modules 49 on which semiconductor elements are mounted and exposed by exposing the electrodes of the semiconductor elements to each other by polishing or plasma processing. FIG. The thermoplastic resin sheet base material 3F having the electrical through holes 48 embeds the semiconductor element 13, and then the protruding electrodes 15 of the semiconductor element 13 are exposed on the surface of the sheet base material 3F by polishing or plasma processing. . Next, a thin film capacitor 46 and a coil 47 made of a conductive paste are formed on the protruding electrode 15. On the back surface of the sheet base material 3F, a thermoplastic resin sheet substrate having a semiconductor element 19 and having an electrical insulation property, on which a thin film capacitor 22 and a coil 21 made of a conductive paste are formed on the projecting electrodes 15. The material 3G is aligned so that electrical connection can be obtained. Next, protective sheets 23 and 24 having electrical insulation properties are superposed on both surfaces, laminated in the thickness direction, and roll-pressed from above and below with upper and lower rolls 40 and 41. As a result, a laminated electronic component built-in module is formed.

【００５９】上記保護シート２３，２４の有する機能、
材質としては、保護シート２３，２４は、熱可塑性樹脂
から成り、埋め込み用の熱可塑性樹脂シート基材３と同
じ材料が望ましいが、同じでなくても構わない。例え
ば、ポリエチレンテレフタレート、塩化ビニル、ポリカ
ーボネイト、又は、アクリルニトリルブタジエンスチレ
ンなどが望ましい。図５では、シート基材３Ｆの下面に
シート基材３Ｇを配置したが、これに限られるものでは
なく、シート基材３Ｆの上面に配置してもよく、シート
基材３Ｆの両面に配置してもよく、さらに、シート基材
３Ｆの片面あるいは両面に、他のシート基材を複数枚、
厚み方向に積層化するようにしてもよい。The functions of the protective sheets 23 and 24,
As a material, the protective sheets 23 and 24 are made of a thermoplastic resin, and the same material as the thermoplastic resin sheet base material 3 for embedding is desirable, but it is not necessary to be the same. For example, polyethylene terephthalate, vinyl chloride, polycarbonate, or acrylonitrile butadiene styrene is desirable. Although the sheet base material 3G is arranged on the lower surface of the sheet base material 3F in FIG. 5, the present invention is not limited to this, and it may be arranged on the upper surface of the sheet base material 3F or on both sides of the sheet base material 3F. Further, a plurality of other sheet base materials may be provided on one or both sides of the sheet base material 3F,
You may make it laminate | stack in a thickness direction.

【００６０】この第４実施形態によれば、上記第１，２
実施形態の作用効果に加えて、さらに、複数のシート基
材３Ｆ，３Ｇを積層することにより、半導体素子１３，
１９や配線パターンが保護シート２３，２４に覆われる
ため、半導体素子１３，１９や配線パターンの耐湿性が
良好になる。すなわち、大気に半導体素子１３，１９が
触れず、半導体素子１３，１９の電極１５などでの酸化
やマイグレーションが起こりにくくなるとともに、磨耗
も防げ、薄型カードとして携帯できるなど実用的であ
る。According to the fourth embodiment, the first and second
In addition to the effects of the embodiment, by further stacking a plurality of sheet base materials 3F and 3G, the semiconductor element 13,
Since 19 and the wiring pattern are covered by the protective sheets 23 and 24, the moisture resistance of the semiconductor elements 13 and 19 and the wiring pattern becomes good. That is, it is practical that the semiconductor elements 13 and 19 do not come into contact with the atmosphere, oxidation and migration at the electrodes 15 of the semiconductor elements 13 and 19 are less likely to occur, abrasion is prevented, and it can be carried as a thin card.

【００６１】次に、本発明の他の実施形態として、突起
状電極を一定の高さに揃えずに直接半導体素子に基材を
埋設することについて説明する。Next, as another embodiment of the present invention, a description will be given of directly embedding a base material in a semiconductor element without aligning the protruding electrodes at a constant height.

【００６２】図８は、突起状電極を予め一定の高さに揃
えずに、直接、電子部品の一例としての半導体素子（Ｉ
Ｃチップ）１３を熱可塑性樹脂シート基材３に埋設する
方法を説明するための断面図である。FIG. 8 shows a semiconductor element (I) as an example of an electronic component directly without the protruding electrodes being arranged at a predetermined height in advance.
FIG. 6 is a cross-sectional view for explaining a method of burying a C chip) 13 in a thermoplastic resin sheet base material 3.

【００６３】対比のため、図８（Ａ），（Ｂ）には予め
レベリングを行った後、熱可塑性樹脂シート基材３に埋
設する方法を説明するための熱可塑性樹脂シート基材３
などの断面図を示す。剛性のあるステージ５上に熱可塑
性樹脂シート基材３を置き、その上に突起状電極１５
ａ，１５ｂを有する半導体素子１３を、電極面を下向き
にして置き、その半導体素子１３の裏面を熱プレスツー
ル４により加熱しながら加圧する。半導体素子１３の突
起状電極１５ａ，１５ｂはレベリングが行われているた
め、その高さはほぼ等しい。そのため、半導体素子１３
はステージ５の表面に対して大略平行に埋め込まれ、電
極１５ａ，１５ｂは容易に熱可塑性樹脂シート基材３の
表面に露出する。For comparison, FIGS. 8 (A) and 8 (B) show the thermoplastic resin sheet base material 3 for explaining a method of embedding in the thermoplastic resin sheet base material 3 after performing leveling in advance.
A cross-sectional view such as is shown. The thermoplastic resin sheet base material 3 is placed on the stage 5 having rigidity, and the protruding electrodes 15 are placed on the base material 3.
The semiconductor element 13 having a and 15b is placed with the electrode surface facing downward, and the back surface of the semiconductor element 13 is pressed while being heated by the hot press tool 4. Since the protruding electrodes 15a and 15b of the semiconductor element 13 are leveled, their heights are substantially equal. Therefore, the semiconductor element 13
Are embedded substantially parallel to the surface of the stage 5, and the electrodes 15a and 15b are easily exposed on the surface of the thermoplastic resin sheet base material 3.

【００６４】一方、図９（Ａ），（Ｂ）は、バンプ形成
後、レベリングせずに、直接的に熱可塑性樹脂シート基
材３に半導体素子１３を埋設する方法を説明するための
熱可塑性樹脂シート基材などの断面図である。半導体素
子１３の突起状電極１５ｃ，１５ｄの高さは、バンプ形
成後のばらつきにより、（電極１５ｃの高さ）＜（電極
１５ｄの高さ）となっている。そのため、半導体素子１
３はステージ５の表面に対して傾き、そのまま押し込む
と、図９（Ｂ）の突起状電極１５ｃのように先端が熱可
塑性樹脂シート基材３の表面に届かず露出しなかった
り、突起状電極１５ｄのように突起状電極先端が倒れて
不規則な形で露出することになる。このような露出で
は、次の回路形成工程で接合不良や、接合信頼性不足が
発生する。On the other hand, FIGS. 9 (A) and 9 (B) are thermoplastic views for explaining a method of directly embedding the semiconductor element 13 in the thermoplastic resin sheet base material 3 without leveling after the bump formation. It is sectional drawing of a resin sheet base material. The heights of the protruding electrodes 15c and 15d of the semiconductor element 13 are (height of the electrode 15c) <(height of the electrode 15d) due to variations after the bump formation. Therefore, the semiconductor device 1
When 3 is tilted with respect to the surface of the stage 5 and pushed in as it is, the tip does not reach the surface of the thermoplastic resin sheet base material 3 and is not exposed as in the protruding electrode 15c of FIG. As shown in 15d, the tip of the protruding electrode falls and is exposed in an irregular shape. Such exposure causes defective bonding and insufficient bonding reliability in the next circuit forming process.

【００６５】そこで、レベリングが無い場合の埋め込み
方法を図１０（Ａ），（Ｂ）を用いて説明する。Therefore, an embedding method in the case where there is no leveling will be described with reference to FIGS. 10 (A) and 10 (B).

【００６６】図１０（Ａ）に示すように、半導体素子１
３の吸引機構を有する熱プレスツール４を用い、半導体
素子１３の裏面を吸引しながら熱可塑性基材２中に埋設
する。半導体素子１３は常に吸引されているため、ステ
ージ５の表面に対し平行であり、突起状電極１ｃが剛体
であるステージ５に押し当てられて塑性変形し、図１０
（Ｂ）のような形に変形するまでプレスすれば、突起状
電極１ｃだけでなくそれよりも高い突起状電極１ｄも熱
可塑性樹脂シート基材３の表面に露出する。半導体素子
１３は常にステージ５に対し水平であるため図１０
（Ｂ）に示すように、突起状電極１ｃと１ｄの高さは等
しくなる。なお、この方法では、半導体素子１３を吸引
する機構が必要なため、熱可塑性樹脂シート基材３が加
熱時ガラス状になりプレスツール４に付着防止策として
の、半導体素子１３とプレスツール４の間に離型紙を介
することはできない。プレスツール４を熱可塑性樹脂シ
ート基材３と離型性の良い材料にしたり、プレスツール
４の形状を半導体素子１３のサイズよりも小さくしたり
することが望ましい。As shown in FIG. 10A, the semiconductor device 1
Using the heat press tool 4 having the suction mechanism 3 of 3, the back surface of the semiconductor element 13 is sucked and embedded in the thermoplastic base material 2. Since the semiconductor element 13 is constantly attracted, the semiconductor element 13 is parallel to the surface of the stage 5, and the projecting electrode 1c is pressed against the rigid stage 5 to be plastically deformed.
By pressing until it is deformed into the shape as shown in (B), not only the protruding electrode 1c but also the protruding electrode 1d higher than that is exposed on the surface of the thermoplastic resin sheet substrate 3. Since the semiconductor element 13 is always horizontal with respect to the stage 5, FIG.
As shown in (B), the protruding electrodes 1c and 1d have the same height. In this method, since a mechanism for sucking the semiconductor element 13 is required, the thermoplastic resin sheet base material 3 becomes glass when heated, and the semiconductor element 13 and the press tool 4 are prevented from adhering to the press tool 4. Release paper cannot be inserted between them. It is desirable that the press tool 4 be made of a material having good releasability from the thermoplastic resin sheet base material 3, or that the shape of the press tool 4 be smaller than the size of the semiconductor element 13.

【００６７】次に、図１１は、本発明のさらに他の実施
形態にかかる電子部品実装済み部品の製造装置の一例を
示す模式図である。この装置は、熱可塑性樹脂シート基
材３の供給機構７２と、半導体素子供給機構６７、その
認識カメラ７３と、その半導体素子１３の搬送機構７
８、半導体素子反転ツール７９と、仮埋めステージ７４
と、熱プレス機構６８を構成する上側プレスツール４と
加熱ステージ５と、プラズマエッチング機構６９とから
大略構成している。Next, FIG. 11 is a schematic view showing an example of an electronic component mounted component manufacturing apparatus according to still another embodiment of the present invention. This apparatus includes a supply mechanism 72 for the thermoplastic resin sheet base material 3, a semiconductor element supply mechanism 67, a recognition camera 73 for the semiconductor element supply mechanism 73, and a conveyance mechanism 7 for the semiconductor element 13.
8. Semiconductor element inversion tool 79 and temporary filling stage 74
The upper pressing tool 4, the heating stage 5, and the plasma etching mechanism 69, which constitute the heat pressing mechanism 68, are roughly configured.

【００６８】まず、熱可塑性樹脂シート基材３の供給
は、ロール供給方式又は枚葉方式を用いることが望まし
い。図１１では、ロール供給方式の場合を示す。まず、
ロール状の熱可塑性樹脂シート基材３は弛みなく図１１
の右側から左側へ供給機構７２により供給する。First, it is desirable that the thermoplastic resin sheet base material 3 be supplied by a roll supply method or a single-wafer method. FIG. 11 shows the case of the roll supply method. First,
The roll-shaped thermoplastic resin sheet base material 3 does not sag, and FIG.
Is supplied from the right side to the left side by the supply mechanism 72.

【００６９】電極パッド１４に突起状電極１５が予め形
成された半導体素子１３を、その電極面を上面にし、規
則的にトレイに収納しておく。これらのトレイを多段に
重ねて電子部品供給装置の一例としての半導体素子供給
機構６７の供給トレイ部７１に置く。なお、半導体素子
１３の収納方法はこの方法に限らず、ウエハ状のままで
も構わない。The semiconductor element 13 in which the protruding electrodes 15 are previously formed on the electrode pad 14 is regularly housed in a tray with the electrode surface of the semiconductor element 13 facing upward. These trays are stacked in multiple stages and placed on a supply tray section 71 of a semiconductor element supply mechanism 67 as an example of an electronic component supply device. The method of housing the semiconductor element 13 is not limited to this method, and may be in the form of a wafer.

【００７０】次に、上下反転装置の一例としての半導体
素子反転ツール７９の認識装置の一例としての半導体素
子認識カメラによりトレイ内の半導体素子１３の電極面
の特徴点、パターン、突起状電極外径などを認識する。
その後、半導体素子反転ツール７９の吸着機能の付いた
吸着ジグ７９ａにより、トレイ内の半導体素子１３の電
極面のある一方の面を吸着したのち、半導体素子反転ツ
ール７９をその回転軸回りに回転させて、半導体素子１
３の上下を反転させ、上記半導体素子１３の電極面を下
向きにする。Next, by using a semiconductor element recognition camera as an example of a device for recognizing a semiconductor element inversion tool 79 as an example of an upside-down device, characteristic points of the electrode surface of the semiconductor element 13 in the tray, a pattern, and an outer diameter of a protruding electrode. Etc.
After that, one surface of the semiconductor element 13 in the tray, which has the electrode surface, is sucked by the suction jig 79a having the suction function of the semiconductor element reversing tool 79, and then the semiconductor element reversing tool 79 is rotated around its rotation axis. Semiconductor element 1
3 is turned upside down so that the electrode surface of the semiconductor element 13 faces downward.

【００７１】次いで、電子部品搭載装置の一例としての
半導体素子搬送機構７８の搬送用吸着ノズル７８ａが半
導体素子反転ツール７９の上方までレール７８ｃ沿いに
移動し、搬送用吸着ノズル７８ａを下降させて、搬送用
吸着ノズル７８ａにより、半導体素子反転ツール７９の
吸着ジグ７８ａにより吸着された半導体素子１３の他方
の面を吸着保持する。このように、半導体素子搬送機構
７８の搬送用吸着ノズル７８ａにより吸着された半導体
素子１３は、その電極面である一方の面が下向きになっ
ている。Next, the transfer suction nozzle 78a of the semiconductor element transfer mechanism 78 as an example of the electronic component mounting apparatus moves along the rail 78c to above the semiconductor element reversing tool 79, and the transfer suction nozzle 78a is lowered. The transport suction nozzle 78a sucks and holds the other surface of the semiconductor element 13 sucked by the suction jig 78a of the semiconductor element reversing tool 79. In this way, the semiconductor element 13 sucked by the suction nozzle 78a for conveyance of the semiconductor element conveying mechanism 78 has one surface, which is the electrode surface, facing downward.

【００７２】次いで、半導体素子搬送機構７８の搬送用
吸着ノズル７８ａにより半導体素子１３を吸着した状態
で、半導体素子搬送機構７８の搬送用吸着ノズル７８ａ
が仮埋めステージ７４上の熱可塑性樹脂シート基材３の
上方までレール７８ｃ沿いに移動する。次いで、仮埋め
ステージ７４上の熱可塑性樹脂シート基材３の埋め込み
位置を認識カメラ７３により認識したのち、搬送用吸着
ノズル７８ａを下降させて、仮埋めステージ７４上の当
該埋め込み位置に、搬送用吸着ノズル７８ａにより吸着
された半導体素子１３を埋め込む。このとき、埋め込ん
だのちの搬送中の位置ずれを防ぐために、搬送用吸着ノ
ズル７８ａを加熱しながら短時間一定量押し込むことが
望ましい。なお、搬送用吸着ノズル７８ａの平面的なサ
イズは半導体素子１３と同じサイズが望ましい。Next, in a state where the semiconductor element 13 is sucked by the transfer suction nozzle 78a of the semiconductor element transfer mechanism 78, the transfer suction nozzle 78a of the semiconductor element transfer mechanism 78 is held.
Moves along the rail 78c to above the thermoplastic resin sheet substrate 3 on the temporary filling stage 74. Next, after the recognition position of the thermoplastic resin sheet base material 3 on the temporary filling stage 74 is recognized by the recognition camera 73, the transport suction nozzle 78a is lowered to the embedded position on the temporary filling stage 74 for transportation. The semiconductor element 13 sucked by the suction nozzle 78a is embedded. At this time, in order to prevent the positional displacement during the transportation after the embedding, it is desirable to press the transportation suction nozzle 78a for a short time while heating it. The planar size of the transport suction nozzle 78a is preferably the same as that of the semiconductor element 13.

【００７３】次に、熱可塑性樹脂シート基材３を仮埋め
ステージ７４上から加熱ステージ５上まで移動させ、電
子部品埋設装置の一例としての上側プレスツール４によ
り半導体素子１３を熱可塑性樹脂シート基材３内に一定
時間押し込む。なお、この熱プレス機構６８は、大気下
又は真空下のいずれで用いても構わない。また、半導体
素子１３の熱可塑性樹脂シート基材３に対する重ね方向
に複数枚重ねるように熱プレスできる多段重ね機構や、
予熱工程、本加熱工程、冷却工程などに分けた、回転ス
テージ機構や温度プロファイルコントローラが付随して
いることが望ましい。なお、この熱プレス機構６８は、
半導体素子１３の熱可塑性樹脂シート基材３に対する、
接触開始位置、押し込み終了位置、下降速度、上昇速度
などが制御できることが望ましい。Next, the thermoplastic resin sheet base material 3 is moved from the temporary filling stage 74 to the heating stage 5, and the semiconductor element 13 is mounted on the semiconductor element 13 by the upper press tool 4 as an example of an electronic component burying apparatus. Push in the material 3 for a certain time. The hot press mechanism 68 may be used either under the atmosphere or under vacuum. In addition, a multi-stage stacking mechanism capable of hot pressing a plurality of semiconductor elements 13 in the stacking direction on the thermoplastic resin sheet base material 3,
It is desirable that a rotary stage mechanism and a temperature profile controller, which are divided into a preheating step, a main heating step, and a cooling step, are attached. The heat press mechanism 68 is
For the thermoplastic resin sheet base material 3 of the semiconductor element 13,
It is desirable to be able to control the contact start position, the pushing end position, the descending speed, the ascending speed, and the like.

【００７４】次に、加熱ステージ５上から電極露出装置
の一例としてのプラズマエッチング機構６９まで、熱可
塑性樹脂シート基材３を搬送し、プラズマエッチングに
より半導体素子１３の電極１５を熱可塑性樹脂シート基
材３から露出させる。プラズマエッチング機構６９で
は、熱可塑性樹脂シート基材３の上方にプラズマ放電用
上側電極１１を配し、熱可塑性樹脂シート基材３を隙間
無きように吸着する。プラズマ放電用上側電極１１の表
面と平行になるように熱可塑性樹脂シート基材３の下側
にはプラズマ放電用下側電極１２を配置する。両電極１
１，１２間に高電圧を印加できる高周波発生電源、及
び、プラズマとその電源とのインピーダンス整合を取る
ためのマッチャーを備える必要がある。また、酸素ガ
ス、フッ化水素ガス、アルゴンガスなどを導入できる配
管と、対応するガスが収納されたボンベとを備えること
が望ましい。さらに、高真空を引くための、油回転ポン
プ、油拡散ポンプ、又は、クライオポンプなどのポンプ
と、真空到達を確認するための真空計とを備えることが
望ましい。なお、このプラズマエッチング機構６９は研
磨機能に置き換えても良い。研磨の場合は、真空を引く
必要は無い。Next, the thermoplastic resin sheet base material 3 is conveyed from the heating stage 5 to the plasma etching mechanism 69 as an example of the electrode exposing device, and the electrodes 15 of the semiconductor element 13 are connected to the thermoplastic resin sheet substrate by plasma etching. It is exposed from the material 3. In the plasma etching mechanism 69, the upper electrode 11 for plasma discharge is arranged above the thermoplastic resin sheet base material 3, and the thermoplastic resin sheet base material 3 is adsorbed without a gap. The lower electrode 12 for plasma discharge is arranged below the thermoplastic resin sheet substrate 3 so as to be parallel to the surface of the upper electrode 11 for plasma discharge. Both electrodes 1
It is necessary to provide a high-frequency generating power supply capable of applying a high voltage between 1 and 12, and a matcher for impedance matching between plasma and the power supply. Further, it is desirable to provide a pipe into which oxygen gas, hydrogen fluoride gas, argon gas, etc. can be introduced, and a cylinder containing the corresponding gas. Further, it is desirable to provide a pump such as an oil rotary pump, an oil diffusion pump, or a cryopump for drawing a high vacuum, and a vacuum gauge for confirming the arrival of the vacuum. The plasma etching mechanism 69 may be replaced with a polishing function. For polishing, it is not necessary to draw a vacuum.

【００７５】このように構成することにより、熱可塑性
樹脂シート基材３に対して半導体素子１３の仮埋め、押
し込み、電極露出を連続して行うことができる。With such a structure, the semiconductor element 13 can be continuously embedded, pushed, and exposed to the thermoplastic resin sheet base material 3 continuously.

【００７６】次に、本発明のさらに他の実施形態とし
て、複数個のメモリーチップを多段に重ねてなるスタッ
クモジュールの例について説明する。Next, as still another embodiment of the present invention, an example of a stack module in which a plurality of memory chips are stacked in multiple stages will be described.

【００７７】図１２は、メモリーチップ２個（ここで
は、第１半導体素子１３Ａと第２半導体素子１３Ｂ）を
積み重ねたスタックモジュール８３がプリント配線板８
５に装着されて形成された埋め込みパッケージモジュー
ルの断面図である。図１３はその製造方法のフローチャ
ートである。In FIG. 12, the stack module 83 in which two memory chips (here, the first semiconductor element 13A and the second semiconductor element 13B) are stacked is the printed wiring board 8.
FIG. 6 is a cross-sectional view of an embedded package module formed by being attached to the No. 5 device. FIG. 13 is a flowchart of the manufacturing method.

【００７８】埋め込みパッケージモジュールは、スタッ
クモジュール８３に予め配線の施されたプリント配線板
８５が装着されたものであり、埋め込みパッケージモジ
ュールの基板電極８０，８０ａ，８０ｂは、図１２には
示していないマザーボードと、半田や導電性接着剤など
によって、接合され、マザーボードと電気的接続が得ら
れる。例えば、第１半導体素子１３Ａの電極１５ｅ，１
５ｆは、スタックモジュール８３の表面の配線８６、ス
タックモジュール８３のスルーホール８８、プリント配
線板８５の電極８１などを介して、電極８０ａ，８０ｂ
まで電気的接続が得られる。The embedded package module is a stack module 83 to which a printed wiring board 85 having wiring is attached in advance, and the substrate electrodes 80, 80a, 80b of the embedded package module are not shown in FIG. It is joined to the mother board by soldering or a conductive adhesive to obtain an electrical connection with the mother board. For example, the electrodes 15e, 1 of the first semiconductor element 13A
5f is an electrode 80a, 80b via the wiring 86 on the surface of the stack module 83, the through hole 88 of the stack module 83, the electrode 81 of the printed wiring board 85, and the like.
Up to electrical connection.

【００７９】スタックモジュール８３の製造工程は、ま
ず、ステップＳ３１において、第１半導体素子１３Ａを
第１熱可塑性樹脂シート基材３Ａに埋め込んだ後、 ス
テップＳ３２において、プラズマエッチングあるいは研
磨により第１半導体素子１３Ａの電極１５ｅ，１５ｆを
露出させる。プラズマエッチングは、第１熱可塑性樹脂
シート基材３Ａの表面全面でも、電極周囲のみでも構わ
ない。In the manufacturing process of the stack module 83, first, in step S31, the first semiconductor element 13A is embedded in the first thermoplastic resin sheet substrate 3A, and then in step S32, the first semiconductor element is subjected to plasma etching or polishing. The electrodes 15e and 15f of 13A are exposed. The plasma etching may be performed on the entire surface of the first thermoplastic resin sheet substrate 3A or only around the electrodes.

【００８０】また、ステップＳ３３において、第２熱可
塑性樹脂シート基材３ＢにＮＣパンチャーを用い、電気
的導通穴８９を開ける。穴径は直径０．１〜１．０ｍｍ
が望ましい。次いで、ステップＳ３４において、スパッ
タリング、めっき、又は、導電性接着剤印刷などによ
り、回路パターン８７の印刷を行う。In step S33, the second thermoplastic resin sheet base material 3B is provided with the NC puncher to form the electrical conduction hole 89. Hole diameter is 0.1-1.0 mm
Is desirable. Next, in step S34, the circuit pattern 87 is printed by sputtering, plating, or printing with a conductive adhesive.

【００８１】また、同じ工法で、ステップＳ３５におい
て、第２半導体素子１３Ｂを第２熱可塑性樹脂シート基
材３Ｂに埋め込み、ステップＳ３６において、その電極
１５ｇを露出させる。ステップＳ３１〜Ｓ３４とステッ
プＳ３５〜Ｓ３６は別個に又は並行して行うことができ
る。Further, by the same method, the second semiconductor element 13B is embedded in the second thermoplastic resin sheet base material 3B in step S35, and the electrode 15g is exposed in step S36. Steps S31 to S34 and steps S35 to S36 can be performed separately or in parallel.

【００８２】次に、ステップＳ３７において、第１熱可
塑性樹脂シート基材３Ａを第２熱可塑性樹脂シート基材
３Ｂの上に重ねて熱プレスして積層状態に固着した後、
ステップＳ３８において、第１熱可塑性樹脂シート基材
３Ａと第２熱可塑性樹脂シート基材３Ｂとを貫通するス
ルーホール８８を穴あけして形成する。Next, in step S37, the first thermoplastic resin sheet base material 3A is overlaid on the second thermoplastic resin sheet base material 3B and hot pressed to fix them in a laminated state.
In step S38, a through hole 88 penetrating the first thermoplastic resin sheet base material 3A and the second thermoplastic resin sheet base material 3B is formed by punching.

【００８３】次いで、ステップＳ３９において、第１熱
可塑性樹脂シート基材３Ａの上面に回路パターンの配線
８６を印刷し、上記スルーホール８８に電気的導通材を
充填する。これにより、スタックモジュール８３が完成
する。Next, in step S39, wiring 86 having a circuit pattern is printed on the upper surface of the first thermoplastic resin sheet base material 3A, and the through holes 88 are filled with an electrically conductive material. As a result, the stack module 83 is completed.

【００８４】最後に、ステップＳ４０において、予め配
線の施されたプリント配線板８５、たとえば、セラミッ
クス、ガラスエポキシ樹脂、樹脂多層基板（例えば、松
下電器産業株式会社製の商品名ＡＬＩＶＨ（アリブ＝An
y Layer Interstitial Via Hole））などと、上記スタ
ックモジュール８３とを熱プレスすることにより、埋め
込みパッケージモジュールを形成する。Finally, in step S40, a printed wiring board 85 on which wiring is preliminarily provided, for example, ceramics, glass epoxy resin, resin multilayer substrate (for example, trade name ALIVH manufactured by Matsushita Electric Industrial Co., Ltd.
y Layer Interstitial Via Hole)) and the like and the stack module 83 are hot pressed to form an embedded package module.

【００８５】図１４は、本発明のさらに他の実施形態に
おいて、２個のメモリー用半導体素子（ＩＣチップ）１
３Ｃを内蔵する熱可塑性樹脂シート基材３Ｃの層から構
成されるメモリー用シートモジュール９１の４層と、１
個のコントローラ用半導体素子（ＩＣチップ）１３Ｄを
内蔵する熱可塑性樹脂シート基材３Ｄのコントローラ用
シートモジュール９２の１層とから成るメモリーカード
の断面図である。１個のメモリー用半導体素子１３Ｃが
６４ＭＢの容量があるため、２個のメモリー用半導体素
子１３Ｃが埋め込まれるメモリー用シートモジュール９
１の１層で１２８ＭＢ、４層全体で５１２ＭＢの記録能
力がある。図１５はその製造工程フローチャートであ
る。FIG. 14 shows two memory semiconductor elements (IC chips) 1 according to still another embodiment of the present invention.
4 layers of a memory sheet module 91 composed of layers of a thermoplastic resin sheet substrate 3C containing 3C;
It is sectional drawing of the memory card which consists of one layer of the controller sheet module 92 of the thermoplastic resin sheet base material 3D which incorporates each controller semiconductor element (IC chip) 13D. Since one memory semiconductor element 13C has a capacity of 64 MB, a memory sheet module 9 in which two memory semiconductor elements 13C are embedded
There is a recording capacity of 128 MB in one layer of 1 and 512 MB in the whole four layers. FIG. 15 is a flowchart of the manufacturing process.

【００８６】例えば、図１４のメモリー用シートモジュ
ール９１は、縦１６ｍｍ×横８ｍｍ×厚さ０．０８０ｍ
ｍのメモリ用半導体素子１３Ｃを２個内蔵するメモリー
用シートモジュール９１が４層と、一辺が７．８ｍｍの
正方形でかつ厚さ０．２００ｍｍのコントローラ用半導
体素子１３Ｄを１個内蔵するコントローラ用シートモジ
ュール９２が１層とから成り、各層間は導電性ペースト
９３などにより電気的な接続が得られる。なお、それぞ
れの半導体素子１３Ｃ，１３Ｄの各電極には、高さ０．
０４０ｍｍの突起状バンプが形成されている。For example, the memory sheet module 91 of FIG. 14 has a length of 16 mm × width of 8 mm × thickness of 0.080 m.
4 sheets of the memory sheet module 91 containing two m semiconductor memory elements 13C, and a controller sheet containing one 7.8 mm square side controller semiconductor element 13D with a thickness of 0.200 mm. The module 92 is made up of one layer, and the layers are electrically connected by the conductive paste 93 or the like. The height of each electrode of the semiconductor elements 13C and 13D is 0.
A projecting bump of 040 mm is formed.

【００８７】以下に一例としてのメモリーカードの製造
方法について説明する。A method of manufacturing a memory card as an example will be described below.

【００８８】まず、ステップＳ４１において、熱可塑性
樹脂シート基材３Ｃ、例えば熱可塑性ポリイミドのシー
ト基材３Ｃの所定個所に、ＮＣパンチャーあるいはレー
ザを用い、φ０．２ｍｍのスルーホール９４を開ける。First, in step S41, an NC puncher or a laser is used to form a through hole 94 of φ0.2 mm in a predetermined portion of the thermoplastic resin sheet base material 3C, for example, the thermoplastic polyimide sheet base material 3C.

【００８９】次に、ステップＳ４２において、メモリ用
熱可塑性樹脂シート基材３Ｃにはメモリ用半導体素子１
３Ｃを２個同時に埋設するとともに、コントローラ用熱
可塑性樹脂シート基材３Ｄはコントローラ用半導体素子
１３Ｄを１個を埋設する。Next, in step S42, the memory semiconductor element 1 is attached to the memory thermoplastic resin sheet substrate 3C.
Two 3C are embedded at the same time, and the controller thermoplastic resin sheet base material 3D also embeds one controller semiconductor element 13D.

【００９０】次いで、ステップＳ４３において、プラズ
マエッチングにより、半導体素子１３Ｃ，１３Ｄのバン
プ電極１５を表面に露出させる。プラズマエッチングに
は、酸素プラズマを用いることが望ましい。Then, in step S43, the bump electrodes 15 of the semiconductor elements 13C and 13D are exposed on the surface by plasma etching. It is desirable to use oxygen plasma for plasma etching.

【００９１】次に、ステップＳ４４において、メモリ用
熱可塑性樹脂シート基材３Ｃとコントローラ用熱可塑性
樹脂シート基材３Ｄのそれぞれにおいて、無電解Ｎｉめ
っきにより約１μｍのＮｉ層を付着させた後、電解めっ
き溶液に漬け、１５μｍのＣｕ層を形成する。その後、
フォトリソグラフィー工程により、上記電極１５と接続
された回路パターン９５を形成する。このとき、同時に
スルーホール９４の周囲もメッキされ、電気的導通が得
られる。なお、この工程は、導電性接着剤の印刷やスパ
ッタリングでも構わない。その後、筐体９７Ａの筐体電
極９６上に、印刷用マスクを載置した上で、導電性ペー
スト９８、例えば、クリーム半田あるいは導電性接着
剤、例えば銀ペースト、銅ペースト、銀・パラジウムペ
ーストなどをスキージを用いて印刷する。印刷後の、導
電性ペースト９８のペースト厚は０．０２０〜０．０３
０ｍｍであることが望ましい。Next, in step S44, a Ni layer of about 1 μm is deposited by electroless Ni plating on each of the memory thermoplastic resin sheet substrate 3C and the controller thermoplastic resin sheet substrate 3D, and then electrolysis is performed. It is dipped in a plating solution to form a Cu layer of 15 μm. afterwards,
A circuit pattern 95 connected to the electrode 15 is formed by a photolithography process. At this time, the periphery of the through hole 94 is also plated at the same time, and electrical conduction is obtained. Note that this step may be printing of a conductive adhesive or sputtering. After that, a printing mask is placed on the casing electrode 96 of the casing 97A, and then a conductive paste 98 such as cream solder or a conductive adhesive such as silver paste, copper paste, silver / palladium paste, etc. Is printed using a squeegee. The paste thickness of the conductive paste 98 after printing is 0.020 to 0.03.
It is preferably 0 mm.

【００９２】その後、ステップＳ４５において、コント
ローラ用シートモジュール９２を筐体９７Ａに搭載し
て、筐体９７Ａの筐体電極９６をコントローラ用熱可塑
性樹脂シート基材３Ｄの回路パターン９５に導電性ペー
スト９８を介して電気的に接続し、硬化炉あるいはリフ
ロー炉で導電性ペースト９８を硬化させる。Then, in step S45, the controller sheet module 92 is mounted on the casing 97A, and the casing electrodes 96 of the casing 97A are applied to the circuit pattern 95 of the controller thermoplastic resin sheet base material 3D and the conductive paste 98. The conductive paste 98 is hardened in a hardening furnace or a reflow furnace.

【００９３】次に、コントローラ用シートモジュール９
２の上側の電極９９上に、クリーム半田あるいは導電性
接着剤、例えば、銀ペースト、銅ペースト、銀・パラジ
ウムペーストなどの導電性ペースト９３を印刷して、４
層目すなわち最下層のメモリー用シートモジュール９１
を搭載し、硬化する。次に、４層目のメモリー用シート
モジュール９１の上側の電極上に、クリーム半田あるい
は導電性接着剤、例えば、銀ペースト、銅ペースト、銀
・パラジウムペーストなどの導電性ペースト９３を印刷
して、３層目のメモリー用シートモジュール９１を搭載
し、硬化する。次に、３層目のメモリー用シートモジュ
ール９１の上側の電極上に、クリーム半田あるいは導電
性接着剤、例えば、銀ペースト、銅ペースト、銀・パラ
ジウムペーストなどの導電性ペースト９３を印刷して、
２層目のメモリー用シートモジュール９１を搭載し、硬
化する。次に、２層目のメモリー用シートモジュール９
１の上側の電極上に、クリーム半田あるいは導電性接着
剤、例えば、銀ペースト、銅ペースト、銀・パラジウム
ペーストなどの導電性ペースト９３を印刷して、１層目
すなわち最上層のメモリー用シートモジュール９１を搭
載し、硬化する。Next, the controller seat module 9
A conductive paste 93 such as cream solder or a conductive adhesive, for example, a silver paste, a copper paste, a silver / palladium paste or the like is printed on the electrode 99 on the upper side of 2.
The sheet module 91 for the memory of the second layer, that is, the lowermost layer
Mount and cure. Next, a cream solder or a conductive adhesive, for example, a conductive paste 93 such as a silver paste, a copper paste, or a silver / palladium paste is printed on the upper electrode of the fourth-layer memory sheet module 91, The memory sheet module 91 of the third layer is mounted and cured. Next, a cream solder or a conductive adhesive, for example, a conductive paste 93 such as a silver paste, a copper paste, or a silver / palladium paste is printed on the upper electrode of the third-layer memory sheet module 91,
The second-layer memory sheet module 91 is mounted and cured. Next, the sheet module 9 for the second layer memory
A conductive paste 93 such as cream solder or a conductive adhesive, for example, a silver paste, a copper paste, a silver / palladium paste, etc. is printed on the upper electrode of 1, and the first layer, that is, the uppermost memory sheet module. Mount 91 and cure.

【００９４】最後に、ステップＳ４６において、筐体蓋
９７Ｂを上記シートモジュール９１，９２に被せること
により、メモリーカードが形成される。Finally, in step S46, the cover 97B is put on the sheet modules 91 and 92 to form a memory card.

【００９５】図１６は、本発明のさらに他の実施形態に
かかる非接触ＩＣカードの製造方法により製造される非
接触ＩＣカードの中間層の上面、下面及びその断面図で
ある。図１７は非接触ＩＣカードの製造方法のフローチ
ャートである。図１８〜図１９は非接触ＩＣカードの製
造方法の工程図である。この非接触ＩＣカードでは、デ
ータを短時間で書き取り読み取りができる。FIG. 16 is an upper surface and a lower surface of a middle layer of a non-contact IC card manufactured by a method of manufacturing a non-contact IC card according to still another embodiment of the present invention, and cross-sectional views thereof. FIG. 17 is a flowchart of a method for manufacturing a non-contact IC card. 18 to 19 are process diagrams of a method for manufacturing a non-contact IC card. With this non-contact IC card, data can be written and read in a short time.

【００９６】図１６の非接触ＩＣカードは、データの書
き換え可能なＦｅＲＡＭの半導体素子（ＩＣチップ）１
３Ｅを内蔵し、表面にアンテナとしての役割を果たすコ
イル５６が印刷されている。The non-contact IC card of FIG. 16 is a data rewritable FeRAM semiconductor element (IC chip) 1
A coil 56 that contains 3E and that functions as an antenna is printed on the surface.

【００９７】非接触ＩＣカードの製造工程は、まず、ス
テップＳ５０及び図１８（Ｂ）において、シート厚０．
１００ｍｍの熱可塑性樹脂シート基材３Ｈ、例えば、ポ
リエチレンテレフタレートのシート基材３ＨにＮＣパン
チャーを用いて、直径０．２００ｍｍのスルーホールを
２箇所（５４ａ，５４ｂ）開ける。In the manufacturing process of the non-contact IC card, first, in step S50 and FIG.
Two through holes (54a, 54b) having a diameter of 0.200 mm are formed in a 100 mm thermoplastic resin sheet base material 3H, for example, a polyethylene terephthalate sheet base material 3H, using an NC puncher.

【００９８】次に、ステップＳ５１及び図１８（Ｃ）に
おいて、スルーホール５４ａ，５４ｂを被うようにジャ
ンパー線５３を導電性ペースト印刷により形成し、硬化
する。硬化条件は、銀ペーストの場合、１１０℃、１０
秒である。Next, in step S51 and FIG. 18C, a jumper wire 53 is formed by conductive paste printing so as to cover the through holes 54a and 54b, and is hardened. The curing conditions are 110 ° C and 10 for silver paste.
Seconds.

【００９９】次に、ステップＳ５４及び図１８（Ｄ）に
おいて、４隅に高さ０．０４０ｍｍの金の突起状電極が
予めステップＳ５２で形成されてステップＳ５３でレベ
リングされた縦４ｍｍ×横６ｍｍ×厚さ０．０８０ｍｍ
のＦｅＲＡＭの半導体素子１３Ｅ（図１８（Ａ）参照）
をシート厚０．１００ｍｍのポリエチレンテレフタレー
トのシート基材３Ｈに埋設する。その後、ステップＳ５
５及び図１９（Ｅ）において、プラズマエッチングによ
り半導体素子１３Ｅの電極１５ｈを一括して露出する。
ステップＳ５０〜Ｓ５１とステップＳ５２〜Ｓ５３とは
別個に又は並行して行うことができる。Next, in step S54 and FIG. 18 (D), gold protruding electrodes having a height of 0.040 mm are previously formed in four corners in step S52 and leveled in step S53: vertical 4 mm × horizontal 6 mm × Thickness 0.080 mm
FeRAM semiconductor element 13E (see FIG. 18A)
Is embedded in a sheet base material 3H made of polyethylene terephthalate having a sheet thickness of 0.100 mm. Then, step S5
5 and FIG. 19E, the electrodes 15h of the semiconductor element 13E are collectively exposed by plasma etching.
Steps S50 to S51 and steps S52 to S53 can be performed separately or in parallel.

【０１００】その後、ステップＳ５６及び図１９（Ｆ）
において、導電性ペーストによりアンテナ用のコイル５
６を上記電極１５ｈと接触するように印刷・硬化する。Then, step S56 and FIG. 19 (F).
In the coil 5 for the antenna in the conductive paste
6 is printed and cured so as to come into contact with the electrode 15h.

【０１０１】最後に、ステップＳ５７及び図１９（Ｇ）
において、熱可塑性樹脂、例えば、ポリエチレンテレフ
タレートのシート５５を、上記熱可塑性樹脂シート基材
３Ｈの両面に重ね、ラミネートプレスしカード化する
（図１６（Ｃ），図１７（Ｇ）参照）。Finally, step S57 and FIG. 19 (G).
In, a sheet 55 of a thermoplastic resin, for example, polyethylene terephthalate, is placed on both sides of the thermoplastic resin sheet base material 3H and laminated and pressed to form a card (see FIGS. 16C and 17G).

【０１０２】その後、ステップＳ５８において模様柄を
印刷した後、ステップＳ５９において打ち抜き機により
カードサイズに打ち抜く。これにより、非接触ＩＣカー
ドが完成する。Then, after the pattern is printed in step S58, it is punched into a card size by a punching machine in step S59. As a result, the contactless IC card is completed.

【０１０３】なお、上記様々な実施形態のうちの任意の
実施形態を適宜組み合わせることにより、それぞれの有
する効果を奏するようにすることができる。It is to be noted that, by properly combining the arbitrary embodiments of the aforementioned various embodiments, the effects possessed by them can be produced.

【０１０４】[0104]

【発明の効果】本発明により、電子部品がシート基材に
埋設するためモジュールの厚みを薄型化が可能となる。
さらに、薄いために従来基板よりも軟らかく、曲面や曲
げ動作を行う場所で使用することができる。さらに、電
子部品の一例としてＩＣチップが内蔵されている場合に
は、基板表面への膜形成、回路パターン形成領域が大き
くなり、高機能化か可能となるとともに、基板サイズの
小型化も可能となる。さらに、複数のシート基材をラミ
ネートして使用すると、部品や配線パターンがシートに
覆われ、耐湿性が良好である。さらに、従来のバッチ処
理に対して、一括して埋設、電極露出をすることが可能
になるため、生産性が向上するといった効果がある。According to the present invention, since the electronic component is embedded in the sheet base material, the thickness of the module can be reduced.
Further, since it is thin, it is softer than the conventional substrate and can be used in a curved surface or a place where a bending operation is performed. Further, when an IC chip is built in as an example of an electronic component, a film forming area on the substrate surface and a circuit pattern forming area become large, so that high functionality can be achieved and the substrate size can be reduced. Become. Furthermore, when a plurality of sheet base materials are laminated and used, parts and wiring patterns are covered with the sheet, and the moisture resistance is good. Further, as compared with the conventional batch processing, it becomes possible to embed and expose the electrodes all at once, which has an effect of improving productivity.

【図面の簡単な説明】[Brief description of drawings]

【図１】 （ａ）〜（ｄ）は、それぞれ、本発明の第１
実施形態にかかる電子部品実装済み部品の製造方法の製
造工程を示す一部断面図である。1A to 1D are respectively the first of the present invention.
It is a partial cross section figure which shows the manufacturing process of the manufacturing method of the electronic component mounted component concerning embodiment.

【図２】 （ａ）〜（ｆ）は、それぞれ、本発明の第２
実施形態にかかる半導体素子実装済み部品の製造方法の
製造工程を示す一部断面図である。2 (a) to (f) are respectively the second aspect of the present invention.
It is a partial cross section figure which shows the manufacturing process of the manufacturing method of the semiconductor element mounted component concerning embodiment.

【図３】 （ａ）〜（ｂ）は、それぞれ、本発明の第３
実施形態において、基材表面に薄膜コンデンサおよびコ
イルを有する電子部品実装済み部品を示す一部断面図及
び平面図である。3 (a) and (b) are respectively the third aspect of the present invention.
FIG. 4 is a partial cross-sectional view and a plan view showing an electronic component mounted component having a thin film capacitor and a coil on the surface of a base material in the embodiment.

【図４】 （ａ）〜（ｄ）は、それぞれ、本発明の上記
第３実施形態の変形例において、複数の電子部品を実装
し、モジュール毎の個片に分割する工程を説明するため
の電子部品実装済み部品の製造工程を示す一部断面図、
平面図、一部断面図、及び平面図である。4 (a) to 4 (d) are views for explaining a process of mounting a plurality of electronic components and dividing the module into individual pieces in a modified example of the third embodiment of the present invention. Partial cross-sectional view showing the manufacturing process of electronic parts mounted components,
It is a top view, a partial cross section, and a top view.

【図５】 本発明の第４実施形態において、電子部品実
装済み部品を積層化した多層積層電子部品実装済み部品
の製造方法の製造工程を示す一部断面図である。FIG. 5 is a partial cross-sectional view showing a manufacturing step of a method for manufacturing a multilayer laminated electronic component-mounted component in which electronic component-mounted components are laminated in the fourth embodiment of the present invention.

【図６】 従来の電子部品実装済み部品を示す一部断面
図である。FIG. 6 is a partial cross-sectional view showing a conventional electronic component mounted component.

【図７】 従来の電子部品実装済み基板の製造工程を示
すフローチャートである。FIG. 7 is a flowchart showing a manufacturing process of a conventional electronic component-mounted board.

【図８】 （Ａ），（Ｂ）はそれぞれ、本発明の他の実
施形態において、突起状電極を予め一定の高さに揃えず
に、直接、半導体素子を熱可塑性樹脂シート基材に埋設
する方法を説明するための熱可塑性樹脂シート基材など
の断面図である。8 (A) and 8 (B) respectively show that, in another embodiment of the present invention, a semiconductor element is directly embedded in a thermoplastic resin sheet base material without preliminarily aligning protruding electrodes with a predetermined height. FIG. 4 is a cross-sectional view of a thermoplastic resin sheet base material or the like for explaining the method of doing.

【図９】 （Ａ），（Ｂ）はそれぞれ、本発明のさらに
他の実施形態において、バンプ形成後、レベリングせず
に、直接的に熱可塑性樹脂シート基材に半導体素子を埋
設する方法を説明するための熱可塑性樹脂シート基材な
どの断面図である。9 (A) and 9 (B) show a method of directly embedding a semiconductor element in a thermoplastic resin sheet base material after bump formation without leveling, in another embodiment of the present invention. It is sectional drawing of a thermoplastic resin sheet base material for description.

【図１０】 （Ａ），（Ｂ）はそれぞれ本発明のさらに
他の実施形態において、レベリングが無い場合の埋め込
み方法を説明するための熱可塑性樹脂シート基材などの
断面図である。10A and 10B are cross-sectional views of a thermoplastic resin sheet base material and the like for explaining a filling method in the case where there is no leveling in still another embodiment of the present invention.

【図１１】 本発明のさらに他の実施形態にかかる電子
部品実装済み部品の製造装置の一例を示す模式図であ
る。FIG. 11 is a schematic view showing an example of an electronic component mounted component manufacturing apparatus according to still another embodiment of the present invention.

【図１２】 本発明のさらに他の実施形態において、メ
モリーチップ２個を積み重ねたスタックモジュールがプ
リント配線板に装着されて形成された埋め込みパッケー
ジモジュールの断面図である。FIG. 12 is a cross-sectional view of an embedded package module formed by mounting a stack module in which two memory chips are stacked on a printed wiring board according to another embodiment of the present invention.

【図１３】 図１２のパッケージモジュールの製造方法
のフローチャートである。13 is a flowchart of a method for manufacturing the package module of FIG.

【図１４】 本発明のさらに他の実施形態において、２
個のメモリー用半導体素子を内蔵する熱可塑性樹脂シー
ト基材の層から構成されるメモリー用シートモジュール
の４層と、１個のコントローラ用半導体素子を内蔵する
熱可塑性樹脂シート基材のコントローラ用シートモジュ
ールの１層とから成るメモリーカードの断面図である。FIG. 14 is a further embodiment of the present invention, in which 2
4 layers of a memory sheet module composed of layers of a thermoplastic resin sheet substrate containing one semiconductor element for memory, and a controller sheet of a thermoplastic resin sheet substrate containing one semiconductor element for controller FIG. 6 is a cross-sectional view of a memory card including one layer of a module.

【図１５】 図１４のメモリーカードの製造工程フロー
チャートである。15 is a flow chart of a manufacturing process of the memory card of FIG.

【図１６】 （Ａ），（Ｂ），（Ｃ）はそれぞれ、本発
明のさらに他の実施形態にかかる非接触ＩＣカードの製
造方法により製造される非接触ＩＣカードの中間層の上
面、下面及びその断面図である。16 (A), (B), and (C) are upper and lower surfaces of an intermediate layer of a non-contact IC card manufactured by a method of manufacturing a non-contact IC card according to still another embodiment of the present invention. FIG.

【図１７】 図１６の非接触ＩＣカードの製造方法のフ
ローチャートである。17 is a flowchart of a method for manufacturing the non-contact IC card of FIG.

【図１８】 （Ａ）〜（Ｄ）はそれぞれ図１７の非接触
ＩＣカードの製造方法の工程図である。18A to 18D are process diagrams of the method for manufacturing the non-contact IC card of FIG.

【図１９】 （Ｅ）〜（Ｇ）はそれぞれ図１８に続く非
接触ＩＣカードの製造方法の工程図である。19 (E) to (G) are process diagrams of the method for manufacturing the non-contact IC card, which are subsequent to FIG. 18.

【符号の説明】[Explanation of symbols]

１…電子部品、１ｆ…表面、１ｒ…裏面、２…電極、
３，３Ｄ，３Ｅ，３Ｆ，３Ｇ，３Ｈ…熱可塑性樹脂シー
ト基材、３Ａ…第１熱可塑性樹脂シート基材、３Ｂ…第
２熱可塑性樹脂シート基材、３ｒ…裏面、４…電子部品
埋め込み用上側プレスツール、５…加熱ステージ、６…
研磨機、７…研磨紙、８…研磨屑、９…真空チャンバ
ー、１０…研磨加工用ステージ、１１…プラズマ装置の
電極、１２…プラズマ装置のステージ、１３…半導体素
子、１３Ａ…第１半導体素子、１３Ｂ…第２半導体素
子、１３Ｃ…メモリー用半導体素子、１３Ｄ…コントロ
ーラ用半導体素子、１４…電極パッド、１５…突起状電
極、１５ａ，１５ｂ，１５ｅ，１５ｆ，１５ｇ，１５ｈ
…電極、１６…突起状電極形成用ジグ、１７…ステー
ジ、１８…レベリング用ツール、１９…レベリング用ス
テージ、２１…コイル、２２…薄膜コンデンサ、４０…
上ロール、４１…下ロール、４６…薄膜コンデンサ、４
７…コイル、４８…貫通穴、４９…モジュール、５０…
仮想切断線、５３…ジャンパー線、５４ａ，５４ｂ…ス
ルーホール、５５…シート、５６…コイル、６７…半導
体素子供給機構、６８…熱プレス機構、６９…プラズマ
エッチング機構、７０…金属細線、７１…供給トレイ部、
７２…熱可塑性樹脂シート基材供給機構、７３…認識カ
メラ、７４…仮埋めステージ、７５…、７６…、７７…、７
８…半導体素子搬送機構、７８ａ…搬送用吸着ノズル、７
９…半導体素子反転ツール、８０…基板電極、８０ａ，８
０ｂ…電極、８１…電極、８２…、８３…スタックモジュ
ール、８５…プリント配線板、８６…配線、８７…回路パ
ターン、８８…スルーホール、８９…電気的導通穴、９０
…、９１…メモリー用シートモジュール、９２…コントロ
ーラ用シートモジュール、９３…導電性ペースト、９４…
スルーホール、９５…回路パターン、９６…筐体電極、９
７Ａ…筐体、９７Ｂ…筐体蓋、９８…導電性ペースト、９
９…上側の電極。1 ... Electronic component, 1f ... Front surface, 1r ... Back surface, 2 ... Electrode,
3, 3D, 3E, 3F, 3G, 3H ... Thermoplastic resin sheet base material, 3A ... First thermoplastic resin sheet base material, 3B ... Second thermoplastic resin sheet base material, 3r ... Back surface, 4 ... Electronic component embedding Upper press tool, 5 ... Heating stage, 6 ...
Polishing machine, 7 ... Polishing paper, 8 ... Polishing dust, 9 ... Vacuum chamber, 10 ... Polishing stage, 11 ... Plasma device electrode, 12 ... Plasma device stage, 13 ... Semiconductor element, 13A ... First semiconductor element , 13B ... Second semiconductor element, 13C ... Memory semiconductor element, 13D ... Controller semiconductor element, 14 ... Electrode pad, 15 ... Projection electrode, 15a, 15b, 15e, 15f, 15g, 15h.
... electrodes, 16 ... jigs for forming protruding electrodes, 17 ... stage, 18 ... leveling tool, 19 ... leveling stage, 21 ... coil, 22 ... thin film capacitor, 40 ...
Upper roll, 41 ... Lower roll, 46 ... Thin film capacitor, 4
7 ... Coil, 48 ... Through hole, 49 ... Module, 50 ...
Virtual cutting line, 53 ... Jumper wire, 54a, 54b ... Through hole, 55 ... Sheet, 56 ... Coil, 67 ... Semiconductor element supply mechanism, 68 ... Heat press mechanism, 69 ... Plasma etching mechanism, 70 ... Thin metal wire, 71 ... Supply tray section,
72 ... Thermoplastic resin sheet base material supply mechanism, 73 ... Recognition camera, 74 ... Temporary filling stage, 75 ..., 76 ..., 77 ..., 7
8 ... Semiconductor element transfer mechanism, 78a ... Transfer suction nozzle, 7
9 ... Semiconductor element inversion tool, 80 ... Substrate electrode, 80a, 8
0b ... Electrode, 81 ... Electrode, 82 ..., 83 ... Stack module, 85 ... Printed wiring board, 86 ... Wiring, 87 ... Circuit pattern, 88 ... Through hole, 89 ... Electrically conductive hole, 90
..., 91 ... memory sheet module, 92 ... controller sheet module, 93 ... conductive paste, 94 ...
Through hole, 95 ... Circuit pattern, 96 ... Casing electrode, 9
7A ... Casing, 97B ... Casing lid, 98 ... Conductive paste, 9
9 ... Upper electrode.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 25/18 ─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. 7 Identification Code FI Theme Coat (Reference) H01L 25/18

Claims (10)

【特許請求の範囲】[Claims] 【請求項１】 電子部品（１，１３，１９）を基材
（３，３Ｄ，３Ｅ，３Ｆ，３Ｇ）中に埋設する工程と、 上記電子部品の電極（２，１５）を上記基材表面に露出
させる工程とを備え、 上記露出工程において、研磨加工とプラズマ放電加工と
のいずれか、あるいは両方により、上記電極を上記基材
表面に露出させることを特徴とする電子部品実装済み部
品の製造方法。1. A step of embedding an electronic component (1, 13, 19) in a substrate (3, 3D, 3E, 3F, 3G), and electrodes (2, 15) of the electronic component on the surface of the substrate. And a step of exposing the electrodes to the surface of the base material by polishing processing and / or plasma discharge processing in the exposure step. Method. 【請求項２】 上記電子部品を上記基材中に埋設する工
程の前に、上記電子部品としての半導体素子（１３）の
電極パッド（１４）に突起状電極（１５）を形成した
後、 上記埋設工程において、上記突起状電極を一定の高さに
揃えるかあるいは直接、上記半導体素子を基材に埋設
し、 上記露出工程において、上記突起状電極を上記基材表面
に露出させる請求項１に記載の電子部品実装済み部品の
製造方法。2. Before the step of embedding the electronic component in the base material, after forming the protruding electrode (15) on the electrode pad (14) of the semiconductor element (13) as the electronic component, In the embedding step, the protruding electrodes are aligned at a constant height or directly embedded in the base material, and in the exposing step, the protruding electrodes are exposed on the surface of the base material. A method for manufacturing the electronic component-mounted component described above. 【請求項３】 上記露出工程の後、上記基材表面に露出
した上記電極上に、メッキ又はイオンプレーティング又
はスパッタリング又は蒸着により、回路パターン、金属
薄膜コンデンサ（４６）、コイル（４７）、又は、抵抗
を形成する請求項１又は２に記載の電子部品実装済み部
品の製造方法。3. After the exposing step, a circuit pattern, a metal thin film capacitor (46), a coil (47), or a metal thin film capacitor (46) is formed on the electrode exposed on the surface of the base material by plating, ion plating, sputtering or vapor deposition. A method of manufacturing a component having electronic components mounted thereon according to claim 1 or 2, wherein a resistor is formed. 【請求項４】 上記露出工程の後、上記基材表面に露出
した電極上に半田ペースト又は導電性接着剤を印刷した
後、高温炉又は高温ステージで加熱硬化することにより
回路パターンを形成する請求項１又は２記載の電子部品
実装済み部品の製造方法。4. After the exposing step, a circuit pattern is formed by printing a solder paste or a conductive adhesive on the electrodes exposed on the surface of the base material, and then heating and curing in a high temperature furnace or a high temperature stage. Item 3. A method of manufacturing an electronic component-mounted component according to Item 1 or 2. 【請求項５】 上記埋設工程において、複数個の電子部
品を一括して上記基材に埋設し、 上記露出工程の後、個片に切断する工程をさらに備える
請求項１〜５のいすれか１つに記載の電子部品実装済み
部品の製造方法。5. The burying step, further comprising a step of burying a plurality of electronic components in the base material in a lump and, after the exposing step, cutting into individual pieces. A method of manufacturing an electronic component-mounted component according to one item. 【請求項６】 請求項１から５のいずれか１つに記載の
電子部品実装済み部品の製造方法により電子部品実装済
み部品を製造した後、この電子部品実装済み部品の片面
あるいは両面に、電子部品実装済み部品あるいは基材を
複数枚、厚み方向に積層化し、積層化した表裏両面に保
護シート（２３，２４）を配置することにより多層積層
電子部品実装済み部品を製造する多層積層電子部品実装
済み部品の製造方法。6. An electronic component-mounted component is manufactured by the method for manufacturing an electronic component-mounted component according to claim 1, and the electronic component is mounted on one or both sides of the electronic component-mounted component. Multi-layer electronic component mounting for manufacturing multi-layer electronic component-mounted components by laminating a plurality of component-mounted components or base materials in the thickness direction and arranging protective sheets (23, 24) on the laminated front and back surfaces Method of manufacturing finished parts. 【請求項７】 請求項１から５のいずれか１つに記載の
電子部品実装済み部品の製造方法により製造された電子
部品実装済み部品。7. An electronic component-mounted component manufactured by the method for manufacturing an electronic component-mounted component according to claim 1. Description: 【請求項８】 基材（３，３Ｄ，３Ｅ，３Ｆ，３Ｇ）
と、 研磨加工、プラズマ放電加工のいずれかあるいは両方に
より、上記基材表面に電極（２，１５）が露出された状
態で、上記基材中に埋設された電子部品（１，１３）と
を備えることを特徴とする電子部品実装済み部品。8. Base material (3, 3D, 3E, 3F, 3G)
And an electronic component (1, 13) embedded in the base material in a state where the electrodes (2, 15) are exposed on the surface of the base material by polishing processing, plasma discharge processing, or both. An electronic component mounted component characterized by being provided. 【請求項９】 上記基材表面に露出した上記電極上に、
メッキ又はイオンプレーティング又はスパッタリング又
は蒸着により形成された、回路パターン、金属薄膜コン
デンサ（４６）、コイル（４７）、又は抵抗をさらに備
えるようにした請求項８に記載の電子部品実装済み部
品。9. On the electrode exposed on the surface of the base material,
The electronic component-mounted component according to claim 8, further comprising a circuit pattern, a metal thin film capacitor (46), a coil (47), or a resistor formed by plating, ion plating, sputtering or vapor deposition. 【請求項１０】 基材及び電子部品を供給する電子部品
供給装置と、 上記電子部品及びその電極位置及び形状を認識する認識
装置と、 上記電子部品を吸引した後、上下反転する上下反転装置
と、 上記電子部品を上記基材上に搭載する電子部品搭載装置
と、 上記電子部品を上記基材内に埋設する電子部品埋設装置
と、 プラズマ放電加工・研磨加工のいずれかあるいは両方を
用いて上記電子部品の上記電極を上記基材の表面に露出
させる電極露出装置とを備えることを特徴とする電子部
品実装済み部品の製造装置。10. An electronic component supply device for supplying a base material and an electronic component, a recognition device for recognizing the position and shape of the electronic component and its electrodes, and a vertical inversion device for vertically inverting after sucking the electronic component. , An electronic component mounting device for mounting the electronic component on the base material, an electronic component embedding device for embedding the electronic component in the base material, and either or both of plasma discharge machining and polishing An electrode exposing device that exposes the electrode of an electronic component to the surface of the base material, a manufacturing device of a component having an electronic component mounted thereon.
JP2001387617A 2001-11-02 2001-12-20 Method and apparatus for manufacturing electronic component mounted component Expired - Fee Related JP3739699B2 (en)

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US10/285,475 US7176055B2 (en) 2001-11-02 2002-11-01 Method and apparatus for manufacturing electronic component-mounted component, and electronic component-mounted component
CNB02149813XA CN1204610C (en) 2001-11-02 2002-11-04 Method and device for mfg. parts after installation of electronic element
US11/653,304 US20070200217A1 (en) 2001-11-02 2007-01-16 Method and apparatus for manufacturing electronic component-mounted component, and electronic component-mounted component

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