JP2009147313A5 - - Google Patents

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Publication number
JP2009147313A5
JP2009147313A5 JP2008291094A JP2008291094A JP2009147313A5 JP 2009147313 A5 JP2009147313 A5 JP 2009147313A5 JP 2008291094 A JP2008291094 A JP 2008291094A JP 2008291094 A JP2008291094 A JP 2008291094A JP 2009147313 A5 JP2009147313 A5 JP 2009147313A5
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JP
Japan
Prior art keywords
substrate
crystal
semiconductor layer
semiconductor
plane orientation
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Application number
JP2008291094A
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English (en)
Japanese (ja)
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JP2009147313A (ja
JP5394043B2 (ja
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Priority to JP2008291094A priority Critical patent/JP5394043B2/ja
Priority claimed from JP2008291094A external-priority patent/JP5394043B2/ja
Publication of JP2009147313A publication Critical patent/JP2009147313A/ja
Publication of JP2009147313A5 publication Critical patent/JP2009147313A5/ja
Application granted granted Critical
Publication of JP5394043B2 publication Critical patent/JP5394043B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2008291094A 2007-11-19 2008-11-13 半導体基板及びそれを用いた半導体装置、並びにそれらの作製方法 Expired - Fee Related JP5394043B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008291094A JP5394043B2 (ja) 2007-11-19 2008-11-13 半導体基板及びそれを用いた半導体装置、並びにそれらの作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007298799 2007-11-19
JP2007298799 2007-11-19
JP2008291094A JP5394043B2 (ja) 2007-11-19 2008-11-13 半導体基板及びそれを用いた半導体装置、並びにそれらの作製方法

Publications (3)

Publication Number Publication Date
JP2009147313A JP2009147313A (ja) 2009-07-02
JP2009147313A5 true JP2009147313A5 (enExample) 2011-11-24
JP5394043B2 JP5394043B2 (ja) 2014-01-22

Family

ID=40640958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008291094A Expired - Fee Related JP5394043B2 (ja) 2007-11-19 2008-11-13 半導体基板及びそれを用いた半導体装置、並びにそれらの作製方法

Country Status (2)

Country Link
US (2) US7879689B2 (enExample)
JP (1) JP5394043B2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7767546B1 (en) * 2009-01-12 2010-08-03 International Business Machines Corporation Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer
US20100176495A1 (en) * 2009-01-12 2010-07-15 International Business Machines Corporation Low cost fabrication of double box back gate silicon-on-insulator wafers
US20100176482A1 (en) * 2009-01-12 2010-07-15 International Business Machine Corporation Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation
US8587063B2 (en) * 2009-11-06 2013-11-19 International Business Machines Corporation Hybrid double box back gate silicon-on-insulator wafers with enhanced mobility channels
US11521972B2 (en) * 2020-05-01 2022-12-06 Tokyo Electron Limited High performance multi-dimensional device and logic integration

Family Cites Families (27)

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Publication number Priority date Publication date Assignee Title
JPH01162376A (ja) * 1987-12-18 1989-06-26 Fujitsu Ltd 半導体装置の製造方法
JPH07101679B2 (ja) * 1988-11-01 1995-11-01 三菱電機株式会社 電子デバイス用ウエハ，ウエハ用棒状基材および電子デバイス
JPH0590117A (ja) 1991-09-27 1993-04-09 Toshiba Corp 単結晶薄膜半導体装置
JPH07297377A (ja) 1994-04-21 1995-11-10 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2000012864A (ja) * 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP3432187B2 (ja) * 1999-09-22 2003-08-04 シャープ株式会社 半導体装置の製造方法
US20020031909A1 (en) * 2000-05-11 2002-03-14 Cyril Cabral Self-aligned silicone process for low resistivity contacts to thin film silicon-on-insulator mosfets
US6583440B2 (en) * 2000-11-30 2003-06-24 Seiko Epson Corporation Soi substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the soi substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
WO2003049189A1 (en) * 2001-12-04 2003-06-12 Shin-Etsu Handotai Co.,Ltd. Pasted wafer and method for producing pasted wafer
US6908797B2 (en) * 2002-07-09 2005-06-21 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US6818529B2 (en) * 2002-09-12 2004-11-16 Applied Materials, Inc. Apparatus and method for forming a silicon film across the surface of a glass substrate
JP3927165B2 (ja) 2003-07-03 2007-06-06 株式会社東芝 半導体装置
US6821826B1 (en) * 2003-09-30 2004-11-23 International Business Machines Corporation Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
US20050275018A1 (en) * 2004-06-10 2005-12-15 Suresh Venkatesan Semiconductor device with multiple semiconductor layers
DE102004031708B4 (de) * 2004-06-30 2008-02-07 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Herstellen eines Substrats mit kristallinen Halbleitergebieten unterschiedlicher Eigenschaften
JP2006040911A (ja) * 2004-07-22 2006-02-09 Renesas Technology Corp 半導体装置及びその製造方法
US7312487B2 (en) * 2004-08-16 2007-12-25 International Business Machines Corporation Three dimensional integrated circuit
US7235433B2 (en) * 2004-11-01 2007-06-26 Advanced Micro Devices, Inc. Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device
US7298009B2 (en) * 2005-02-01 2007-11-20 Infineon Technologies Ag Semiconductor method and device with mixed orientation substrate
US7372720B1 (en) * 2005-02-16 2008-05-13 Altera Corporation Methods and apparatus for decreasing soft errors and cell leakage in integrated circuit structures
US7432149B2 (en) * 2005-06-23 2008-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS on SOI substrates with hybrid crystal orientations
US7709317B2 (en) * 2005-11-14 2010-05-04 International Business Machines Corporation Method to increase strain enhancement with spacerless FET and dual liner process
US7288458B2 (en) * 2005-12-14 2007-10-30 Freescale Semiconductor, Inc. SOI active layer with different surface orientation
KR101461206B1 (ko) * 2007-05-17 2014-11-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치 및 그의 제조방법
JP2009076879A (ja) * 2007-08-24 2009-04-09 Semiconductor Energy Lab Co Ltd 半導体装置
US8232598B2 (en) * 2007-09-20 2012-07-31 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same

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