JP2009141268A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2009141268A JP2009141268A JP2007318745A JP2007318745A JP2009141268A JP 2009141268 A JP2009141268 A JP 2009141268A JP 2007318745 A JP2007318745 A JP 2007318745A JP 2007318745 A JP2007318745 A JP 2007318745A JP 2009141268 A JP2009141268 A JP 2009141268A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 97
- 239000011347 resin Substances 0.000 claims abstract description 83
- 229920005989 resin Polymers 0.000 claims abstract description 83
- 238000005520 cutting process Methods 0.000 claims abstract description 49
- 238000010438 heat treatment Methods 0.000 claims abstract description 30
- 238000007789 sealing Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 137
- 238000002474 experimental method Methods 0.000 description 28
- 238000000465 moulding Methods 0.000 description 19
- 230000000052 comparative effect Effects 0.000 description 18
- 239000004593 Epoxy Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 238000000691 measurement method Methods 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】基板10の片面を樹脂20で封止する工程と、基板10と樹脂20とを、平坦な状態に保持しながら加熱する第1加熱工程と、第1加熱工程の後に、前記基板10と前記樹脂20とを、平坦な状態に保持しながら室温に戻す工程と、基板10と樹脂20とを室温に戻す工程の後に、基板10と接している面とは反対の面から、基板10を残存させるように、樹脂10を切断する工程と、基板10を個片化する工程と、を有する半導体装置の製造方法である。
【選択図】図9
Description
20 樹脂
22、24 切断線
100、110、120 半導体装置
Claims (8)
- 基板の片面を樹脂で封止する工程と、
前記基板と前記樹脂とを、平坦な状態に保持しながら、加熱する第1加熱工程と、
第1加熱工程の後に、前記基板と前記樹脂とを、平坦な状態に保持しながら、室温に戻す工程と、
前記基板と前記樹脂とを室温に戻す工程の後に、前記基板と接している面とは反対の面から、前記基板を残存させるように、前記樹脂を切断する工程と、
前記基板を個片化する工程と、を有することを特徴とする半導体装置の製造方法。 - 前記樹脂を切断する工程の後であって、前記基板を個片化する工程の前に、前記基板を加熱する第2加熱工程を含むことを特徴とする請求項1記載の半導体装置の製造方法。
- 前記樹脂を切断する工程における複数の切断線は、前記基板を個片化する工程における複数の切断線のうち、少なくとも一本と、重なっていることを特徴とする請求項1または2記載の半導体装置の製造方法。
- 前記基板を個片化する工程における切断線は、前記樹脂を切断する工程における切断線を含んでいることを特徴とする請求項1から3いずれか一項記載の半導体装置の製造方法。
- 前記樹脂を切断する工程は、前記樹脂を幅方向に切断する工程であることを特徴とする請求項1から4いずれか一項記載の半導体装置の製造方法。
- 前記樹脂を切断する工程は、前記樹脂を格子状に切断する工程であることを特徴とする請求項1から4いずれか一項記載の半導体装置の製造方法。
- 前記基板の前記片面を前記樹脂で封止する工程は、前記基板と前記樹脂とを加熱する第3加熱工程を含むことを特徴とする請求項1から6いずれか一項記載の半導体装置の製造方法。
- 前記第2加熱工程は、前記基板に端子を設ける工程に含まれることを特徴とする請求項2記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007318745A JP2009141268A (ja) | 2007-12-10 | 2007-12-10 | 半導体装置の製造方法 |
US12/332,146 US7851260B2 (en) | 2007-12-10 | 2008-12-10 | Method for manufacturing a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007318745A JP2009141268A (ja) | 2007-12-10 | 2007-12-10 | 半導体装置の製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013231805A Division JP5941032B2 (ja) | 2013-11-08 | 2013-11-08 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2009141268A true JP2009141268A (ja) | 2009-06-25 |
Family
ID=40871558
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007318745A Pending JP2009141268A (ja) | 2007-12-10 | 2007-12-10 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7851260B2 (ja) |
JP (1) | JP2009141268A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018117041A (ja) * | 2017-01-18 | 2018-07-26 | 株式会社ディスコ | 板状ワークの反り低減方法及びそれを用いる加工装置 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20210116762A (ko) | 2020-03-13 | 2021-09-28 | 삼성디스플레이 주식회사 | 디스플레이 장치 및 그 제조방법 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04313245A (ja) * | 1991-04-11 | 1992-11-05 | Mitsui High Tec Inc | 半導体装置の製造方法 |
JPH0917816A (ja) * | 1995-06-29 | 1997-01-17 | Nec Kyushu Ltd | 半導体装置の製造方法 |
JP2002110718A (ja) * | 2000-09-29 | 2002-04-12 | Hitachi Ltd | 半導体装置の製造方法 |
JP2002151371A (ja) * | 2000-11-16 | 2002-05-24 | Sony Corp | チップ状電子部品の製造に用いる疑似ウエーハおよびその製造方法ならびにチップ状電子部品の製造方法 |
JP2007311378A (ja) * | 2006-05-16 | 2007-11-29 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5300459A (en) * | 1989-12-28 | 1994-04-05 | Sanken Electric Co., Ltd. | Method for reducing thermal stress in an encapsulated integrated circuit package |
US5550408A (en) * | 1992-11-18 | 1996-08-27 | Matsushita Electronics Corporation | Semiconductor device |
JPH08510358A (ja) * | 1993-04-14 | 1996-10-29 | アムコール・エレクトロニクス・インク | 集積回路チップと基板との相互接続 |
MY111779A (en) * | 1994-11-10 | 2000-12-30 | Nitto Denko Corp | Semiconductor device |
TW398163B (en) * | 1996-10-09 | 2000-07-11 | Matsushita Electric Ind Co Ltd | The plate for heat transfer substrate and manufacturing method thereof, the heat-transfer substrate using such plate and manufacturing method thereof |
US6228688B1 (en) * | 1997-02-03 | 2001-05-08 | Kabushiki Kaisha Toshiba | Flip-chip resin-encapsulated semiconductor device |
US5893726A (en) * | 1997-12-15 | 1999-04-13 | Micron Technology, Inc. | Semiconductor package with pre-fabricated cover and method of fabrication |
JP3941262B2 (ja) * | 1998-10-06 | 2007-07-04 | 株式会社日立製作所 | 熱硬化性樹脂材料およびその製造方法 |
US6717245B1 (en) * | 2000-06-02 | 2004-04-06 | Micron Technology, Inc. | Chip scale packages performed by wafer level processing |
JP2002184934A (ja) * | 2000-12-13 | 2002-06-28 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP4275522B2 (ja) * | 2003-12-26 | 2009-06-10 | 日東電工株式会社 | ダイシング・ダイボンドフィルム |
US7170188B2 (en) * | 2004-06-30 | 2007-01-30 | Intel Corporation | Package stress management |
-
2007
- 2007-12-10 JP JP2007318745A patent/JP2009141268A/ja active Pending
-
2008
- 2008-12-10 US US12/332,146 patent/US7851260B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04313245A (ja) * | 1991-04-11 | 1992-11-05 | Mitsui High Tec Inc | 半導体装置の製造方法 |
JPH0917816A (ja) * | 1995-06-29 | 1997-01-17 | Nec Kyushu Ltd | 半導体装置の製造方法 |
JP2002110718A (ja) * | 2000-09-29 | 2002-04-12 | Hitachi Ltd | 半導体装置の製造方法 |
JP2002151371A (ja) * | 2000-11-16 | 2002-05-24 | Sony Corp | チップ状電子部品の製造に用いる疑似ウエーハおよびその製造方法ならびにチップ状電子部品の製造方法 |
JP2007311378A (ja) * | 2006-05-16 | 2007-11-29 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018117041A (ja) * | 2017-01-18 | 2018-07-26 | 株式会社ディスコ | 板状ワークの反り低減方法及びそれを用いる加工装置 |
Also Published As
Publication number | Publication date |
---|---|
US20090311831A1 (en) | 2009-12-17 |
US7851260B2 (en) | 2010-12-14 |
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