JP2009038351A5 - - Google Patents

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Publication number
JP2009038351A5
JP2009038351A5 JP2008163159A JP2008163159A JP2009038351A5 JP 2009038351 A5 JP2009038351 A5 JP 2009038351A5 JP 2008163159 A JP2008163159 A JP 2008163159A JP 2008163159 A JP2008163159 A JP 2008163159A JP 2009038351 A5 JP2009038351 A5 JP 2009038351A5
Authority
JP
Japan
Prior art keywords
substrate
modified region
semiconductor device
partially modified
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008163159A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009038351A (ja
Filing date
Publication date
Priority claimed from EP07012358A external-priority patent/EP2009679A1/en
Application filed filed Critical
Publication of JP2009038351A publication Critical patent/JP2009038351A/ja
Publication of JP2009038351A5 publication Critical patent/JP2009038351A5/ja
Pending legal-status Critical Current

Links

JP2008163159A 2007-06-25 2008-06-23 半導体デバイス Pending JP2009038351A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP07012358A EP2009679A1 (en) 2007-06-25 2007-06-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2009038351A JP2009038351A (ja) 2009-02-19
JP2009038351A5 true JP2009038351A5 (enExample) 2012-07-05

Family

ID=38647645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008163159A Pending JP2009038351A (ja) 2007-06-25 2008-06-23 半導体デバイス

Country Status (3)

Country Link
US (1) US20090020786A1 (enExample)
EP (1) EP2009679A1 (enExample)
JP (1) JP2009038351A (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100308440A1 (en) * 2009-06-08 2010-12-09 Globalfoundries Inc. Semiconductor structures and methods for stabilizing silicon-comprising structures on a silicon oxide layer of a semiconductor substrate
JP4794692B2 (ja) * 2009-06-24 2011-10-19 パナソニック株式会社 半導体装置の製造方法
WO2011013271A1 (ja) * 2009-07-27 2011-02-03 パナソニック株式会社 半導体装置の製造方法及びプラズマドーピング装置
US8999798B2 (en) * 2009-12-17 2015-04-07 Applied Materials, Inc. Methods for forming NMOS EPI layers
US8071467B2 (en) 2010-04-07 2011-12-06 Micron Technology, Inc. Methods of forming patterns, and methods of forming integrated circuits
US8357579B2 (en) 2010-11-30 2013-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuits
US9000498B2 (en) * 2013-06-28 2015-04-07 Stmicroelectronics, Inc. FinFET with multiple concentration percentages
US9553174B2 (en) * 2014-03-28 2017-01-24 Applied Materials, Inc. Conversion process utilized for manufacturing advanced 3D features for semiconductor device applications
US9589811B2 (en) * 2015-06-24 2017-03-07 Varian Semiconductor Equipment Associates, Inc. FinFET spacer etch with no fin recess and no gate-spacer pull-down
US10297448B2 (en) * 2015-11-30 2019-05-21 International Business Machines Corporation SiGe fins formed on a substrate

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3859821B2 (ja) * 1997-07-04 2006-12-20 株式会社半導体エネルギー研究所 半導体装置
US6432798B1 (en) * 2000-08-10 2002-08-13 Intel Corporation Extension of shallow trench isolation by ion implantation
JP2004103899A (ja) * 2002-09-11 2004-04-02 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
KR100476940B1 (ko) * 2003-06-20 2005-03-16 삼성전자주식회사 기판으로부터 수직으로 연장된 게이트 채널을 갖는디램기억 셀 및 그 제조방법
US7049662B2 (en) * 2003-11-26 2006-05-23 International Business Machines Corporation Structure and method to fabricate FinFET devices
US7384838B2 (en) * 2005-09-13 2008-06-10 International Business Machines Corporation Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such semiconductor FinFET structures
DE102006030264B4 (de) * 2006-06-30 2008-08-28 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung von Transistoren mit einem Kanal mit biaxialer Verformung, die durch Silizium/Germanium in der Gateelektrode hervorgerufen wird

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