JP2009033173A - 半導体素子およびその製造方法 - Google Patents

半導体素子およびその製造方法 Download PDF

Info

Publication number
JP2009033173A
JP2009033173A JP2008192141A JP2008192141A JP2009033173A JP 2009033173 A JP2009033173 A JP 2009033173A JP 2008192141 A JP2008192141 A JP 2008192141A JP 2008192141 A JP2008192141 A JP 2008192141A JP 2009033173 A JP2009033173 A JP 2009033173A
Authority
JP
Japan
Prior art keywords
region
gate electrode
film
thickness
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008192141A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009033173A5 (enExample
Inventor
Lee Joo Won
周 遠 李
Dong Suk Shin
東 石 申
Tae Kyun Kim
泰 均 金
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2009033173A publication Critical patent/JP2009033173A/ja
Publication of JP2009033173A5 publication Critical patent/JP2009033173A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/796—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2008192141A 2007-07-30 2008-07-25 半導体素子およびその製造方法 Pending JP2009033173A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070076505A KR20090012573A (ko) 2007-07-30 2007-07-30 반도체 소자 및 그 제조 방법

Publications (2)

Publication Number Publication Date
JP2009033173A true JP2009033173A (ja) 2009-02-12
JP2009033173A5 JP2009033173A5 (enExample) 2012-09-06

Family

ID=40337314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008192141A Pending JP2009033173A (ja) 2007-07-30 2008-07-25 半導体素子およびその製造方法

Country Status (3)

Country Link
US (1) US20090032881A1 (enExample)
JP (1) JP2009033173A (enExample)
KR (1) KR20090012573A (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7767534B2 (en) * 2008-09-29 2010-08-03 Advanced Micro Devices, Inc. Methods for fabricating MOS devices having highly stressed channels
US9202913B2 (en) * 2010-09-30 2015-12-01 Institute of Microelectronics, Chinese Academy of Sciences Method for manufacturing semiconductor structure
US9142462B2 (en) * 2010-10-21 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having a contact etch stop layer and method of forming the same
US10361282B2 (en) 2017-05-08 2019-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a low-K spacer
DE102018101511B4 (de) * 2017-09-28 2021-03-18 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren zur Halbleiterverarbeitung zum Bilden einer differenziellen Ätzstoppschicht
US10763104B2 (en) * 2017-09-28 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming differential etch stop layer using directional plasma to activate surface on device structure
US11600530B2 (en) * 2018-07-31 2023-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10943818B2 (en) 2018-10-31 2021-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5972754A (en) * 1998-06-10 1999-10-26 Mosel Vitelic, Inc. Method for fabricating MOSFET having increased effective gate length
US6521502B1 (en) * 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
US6825529B2 (en) * 2002-12-12 2004-11-30 International Business Machines Corporation Stress inducing spacers
US7279746B2 (en) * 2003-06-30 2007-10-09 International Business Machines Corporation High performance CMOS device structures and method of manufacture
US20050275034A1 (en) * 2004-04-08 2005-12-15 International Business Machines Corporation A manufacturable method and structure for double spacer cmos with optimized nfet/pfet performance
US7615426B2 (en) * 2005-02-22 2009-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. PMOS transistor with discontinuous CESL and method of fabrication
US7445978B2 (en) * 2005-05-04 2008-11-04 Chartered Semiconductor Manufacturing, Ltd Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS
US20070023845A1 (en) * 2005-07-26 2007-02-01 Fujitsu Limited Semiconductor device and method for fabricating the same
DE102006040765B4 (de) * 2006-08-31 2011-02-03 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Feldeffekttransistors mit einer verspannten Kontaktätzstoppschicht mit geringerer Konformität und Feldeffekttransistor

Also Published As

Publication number Publication date
US20090032881A1 (en) 2009-02-05
KR20090012573A (ko) 2009-02-04

Similar Documents

Publication Publication Date Title
JP5274594B2 (ja) 自己整合されたデュアル応力層を用いるｃｍｏｓ構造体及び方法
EP1565931B1 (en) Strained finfet cmos device structures
US7701010B2 (en) Method of fabricating transistor including buried insulating layer and transistor fabricated using the same
JP4994139B2 (ja) 半導体装置及びその製造方法
KR20090019693A (ko) 스트레인된 반도체 장치 및 이의 제조 방법
JP2009033173A (ja) 半導体素子およびその製造方法
US20170256459A1 (en) Method of fabricating semiconductor structure with self-aligned spacers
US20170365715A1 (en) Damage Implantation of a Cap Layer
JP2009152342A (ja) 半導体装置の製造方法
US7459382B2 (en) Field effect device with reduced thickness gate
JP2007042964A (ja) 半導体装置及びその製造方法
US7884428B2 (en) Semiconductor device and method for manufacturing the same
JP2008288364A (ja) 半導体装置および半導体装置の製造方法
JP2008263114A (ja) 半導体装置の製造方法および半導体装置
JP2006108439A (ja) 半導体装置
KR100549006B1 (ko) 완전한 실리사이드 게이트를 갖는 모스 트랜지스터 제조방법
JP4958408B2 (ja) 半導体装置
JP4997752B2 (ja) 半導体装置の製造方法
JP2005311058A (ja) 半導体装置及びその製造方法
JP2010141102A (ja) 半導体装置およびその製造方法
JP2006202860A (ja) 半導体装置及びその製造方法
JP3725137B2 (ja) 半導体装置の製造方法
JP2012230993A (ja) 半導体基板、半導体装置及びその製造方法
JP2006310524A (ja) 半導体装置およびその製造方法
JP2009059758A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110630

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110630

A072 Dismissal of procedure [no reply to invitation to correct request for examination]

Free format text: JAPANESE INTERMEDIATE CODE: A073

Effective date: 20121030