JP2009033173A5 - - Google Patents

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Publication number
JP2009033173A5
JP2009033173A5 JP2008192141A JP2008192141A JP2009033173A5 JP 2009033173 A5 JP2009033173 A5 JP 2009033173A5 JP 2008192141 A JP2008192141 A JP 2008192141A JP 2008192141 A JP2008192141 A JP 2008192141A JP 2009033173 A5 JP2009033173 A5 JP 2009033173A5
Authority
JP
Japan
Prior art keywords
region
gate electrode
etch stop
stop layer
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008192141A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009033173A (ja
Filing date
Publication date
Priority claimed from KR1020070076505A external-priority patent/KR20090012573A/ko
Application filed filed Critical
Publication of JP2009033173A publication Critical patent/JP2009033173A/ja
Publication of JP2009033173A5 publication Critical patent/JP2009033173A5/ja
Pending legal-status Critical Current

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JP2008192141A 2007-07-30 2008-07-25 半導体素子およびその製造方法 Pending JP2009033173A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070076505A KR20090012573A (ko) 2007-07-30 2007-07-30 반도체 소자 및 그 제조 방법

Publications (2)

Publication Number Publication Date
JP2009033173A JP2009033173A (ja) 2009-02-12
JP2009033173A5 true JP2009033173A5 (enExample) 2012-09-06

Family

ID=40337314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008192141A Pending JP2009033173A (ja) 2007-07-30 2008-07-25 半導体素子およびその製造方法

Country Status (3)

Country Link
US (1) US20090032881A1 (enExample)
JP (1) JP2009033173A (enExample)
KR (1) KR20090012573A (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7767534B2 (en) * 2008-09-29 2010-08-03 Advanced Micro Devices, Inc. Methods for fabricating MOS devices having highly stressed channels
US9202913B2 (en) * 2010-09-30 2015-12-01 Institute of Microelectronics, Chinese Academy of Sciences Method for manufacturing semiconductor structure
US9142462B2 (en) * 2010-10-21 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having a contact etch stop layer and method of forming the same
US10361282B2 (en) 2017-05-08 2019-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a low-K spacer
US10763104B2 (en) 2017-09-28 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming differential etch stop layer using directional plasma to activate surface on device structure
DE102018101511B4 (de) * 2017-09-28 2021-03-18 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren zur Halbleiterverarbeitung zum Bilden einer differenziellen Ätzstoppschicht
US11600530B2 (en) 2018-07-31 2023-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10943818B2 (en) 2018-10-31 2021-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5972754A (en) * 1998-06-10 1999-10-26 Mosel Vitelic, Inc. Method for fabricating MOSFET having increased effective gate length
US6521502B1 (en) * 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
US6825529B2 (en) * 2002-12-12 2004-11-30 International Business Machines Corporation Stress inducing spacers
US7279746B2 (en) * 2003-06-30 2007-10-09 International Business Machines Corporation High performance CMOS device structures and method of manufacture
US20050275034A1 (en) * 2004-04-08 2005-12-15 International Business Machines Corporation A manufacturable method and structure for double spacer cmos with optimized nfet/pfet performance
US7615426B2 (en) * 2005-02-22 2009-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. PMOS transistor with discontinuous CESL and method of fabrication
US7445978B2 (en) * 2005-05-04 2008-11-04 Chartered Semiconductor Manufacturing, Ltd Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS
TWI282624B (en) * 2005-07-26 2007-06-11 Fujitsu Ltd Semiconductor device and method for fabricating the same
DE102006040765B4 (de) * 2006-08-31 2011-02-03 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Feldeffekttransistors mit einer verspannten Kontaktätzstoppschicht mit geringerer Konformität und Feldeffekttransistor

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