JP2007335573A5 - - Google Patents

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Publication number
JP2007335573A5
JP2007335573A5 JP2006164620A JP2006164620A JP2007335573A5 JP 2007335573 A5 JP2007335573 A5 JP 2007335573A5 JP 2006164620 A JP2006164620 A JP 2006164620A JP 2006164620 A JP2006164620 A JP 2006164620A JP 2007335573 A5 JP2007335573 A5 JP 2007335573A5
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JP
Japan
Prior art keywords
region
semiconductor device
insulating film
semiconductor substrate
stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006164620A
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English (en)
Japanese (ja)
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JP2007335573A (ja
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Publication date
Application filed filed Critical
Priority to JP2006164620A priority Critical patent/JP2007335573A/ja
Priority claimed from JP2006164620A external-priority patent/JP2007335573A/ja
Priority to US11/674,420 priority patent/US20070290264A1/en
Publication of JP2007335573A publication Critical patent/JP2007335573A/ja
Publication of JP2007335573A5 publication Critical patent/JP2007335573A5/ja
Withdrawn legal-status Critical Current

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JP2006164620A 2006-06-14 2006-06-14 半導体装置およびその製造方法 Withdrawn JP2007335573A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006164620A JP2007335573A (ja) 2006-06-14 2006-06-14 半導体装置およびその製造方法
US11/674,420 US20070290264A1 (en) 2006-06-14 2007-02-13 Semiconductor device and a method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006164620A JP2007335573A (ja) 2006-06-14 2006-06-14 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
JP2007335573A JP2007335573A (ja) 2007-12-27
JP2007335573A5 true JP2007335573A5 (enExample) 2009-04-09

Family

ID=38860694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006164620A Withdrawn JP2007335573A (ja) 2006-06-14 2006-06-14 半導体装置およびその製造方法

Country Status (2)

Country Link
US (1) US20070290264A1 (enExample)
JP (1) JP2007335573A (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009064860A (ja) * 2007-09-05 2009-03-26 Renesas Technology Corp 半導体装置
US9461169B2 (en) * 2010-05-28 2016-10-04 Globalfoundries Inc. Device and method for fabricating thin semiconductor channel and buried strain memorization layer
TWI449255B (zh) * 2010-11-08 2014-08-11 Ind Tech Res Inst 具光子能隙結構之矽基懸浮天線及其製造方法
US8957462B2 (en) 2010-12-09 2015-02-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising an N-type transistor with an N-type semiconductor containing nitrogen as a gate
KR20120073727A (ko) * 2010-12-27 2012-07-05 삼성전자주식회사 스트레인드 반도체 영역을 포함하는 반도체 소자와 그 제조방법, 및 그것을 포함하는 전자 시스템
US8513773B2 (en) 2011-02-02 2013-08-20 Semiconductor Energy Laboratory Co., Ltd. Capacitor and semiconductor device including dielectric and N-type semiconductor
US8536032B2 (en) 2011-06-08 2013-09-17 International Business Machines Corporation Formation of embedded stressor through ion implantation
US9001564B2 (en) 2011-06-29 2015-04-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method for driving the same
CN102881694A (zh) 2011-07-14 2013-01-16 中国科学院微电子研究所 半导体器件及其制造方法
CN102931222B (zh) * 2011-08-08 2015-05-20 中国科学院微电子研究所 半导体器件及其制造方法
US20130277747A1 (en) * 2012-04-24 2013-10-24 Stmicroelectronics, Inc. Transistor having a stressed body
FR3003685B1 (fr) 2013-03-21 2015-04-17 St Microelectronics Crolles 2 Procede de modification localisee des contraintes dans un substrat du type soi, en particulier fd soi, et dispositif correspondant
FR3023411B1 (fr) * 2014-07-07 2017-12-22 Commissariat Energie Atomique Generation localisee de contrainte dans un substrat soi
US9209301B1 (en) * 2014-09-18 2015-12-08 Soitec Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers
CN109585273B (zh) * 2018-11-30 2020-04-28 中国电子科技集团公司第十三研究所 一种氧化镓器件隔离区的制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100265350B1 (ko) * 1998-06-30 2000-09-15 김영환 매립절연층을 갖는 실리콘 기판에서의 반도체소자 제조방법
JP4521542B2 (ja) * 1999-03-30 2010-08-11 ルネサスエレクトロニクス株式会社 半導体装置および半導体基板
US6228694B1 (en) * 1999-06-28 2001-05-08 Intel Corporation Method of increasing the mobility of MOS transistors by use of localized stress regions
US7189606B2 (en) * 2002-06-05 2007-03-13 Micron Technology, Inc. Method of forming fully-depleted (FD) SOI MOSFET access transistor
KR100500451B1 (ko) * 2003-06-16 2005-07-12 삼성전자주식회사 인장된 채널을 갖는 모스 트랜지스터를 구비하는반도체소자의 제조 방법
US7138320B2 (en) * 2003-10-31 2006-11-21 Advanced Micro Devices, Inc. Advanced technique for forming a transistor having raised drain and source regions
US7262087B2 (en) * 2004-12-14 2007-08-28 International Business Machines Corporation Dual stressed SOI substrates
JP4369359B2 (ja) * 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
JP4664760B2 (ja) * 2005-07-12 2011-04-06 株式会社東芝 半導体装置およびその製造方法
US7384851B2 (en) * 2005-07-15 2008-06-10 International Business Machines Corporation Buried stress isolation for high-performance CMOS technology
DE102005063108A1 (de) * 2005-12-30 2007-07-12 Advanced Micro Devices, Inc., Sunnyvale Technik zur Herstellung eines Isolationsgrabens als eine Spannungsquelle für die Verformungsverfahrenstechnik
US8017472B2 (en) * 2006-02-17 2011-09-13 Infineon Technologies Ag CMOS devices having stress-altering material lining the isolation trenches and methods of manufacturing thereof

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