JP2009004074A5 - - Google Patents

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Publication number
JP2009004074A5
JP2009004074A5 JP2008147062A JP2008147062A JP2009004074A5 JP 2009004074 A5 JP2009004074 A5 JP 2009004074A5 JP 2008147062 A JP2008147062 A JP 2008147062A JP 2008147062 A JP2008147062 A JP 2008147062A JP 2009004074 A5 JP2009004074 A5 JP 2009004074A5
Authority
JP
Japan
Prior art keywords
transistor
memory cell
gate electrode
load
cell according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2008147062A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009004074A (ja
Filing date
Publication date
Priority claimed from FR0703955A external-priority patent/FR2916895B1/fr
Application filed filed Critical
Publication of JP2009004074A publication Critical patent/JP2009004074A/ja
Publication of JP2009004074A5 publication Critical patent/JP2009004074A5/ja
Withdrawn legal-status Critical Current

Links

JP2008147062A 2007-06-04 2008-06-04 ４つのダブル・ゲートのトランジスタを備える非対称ｓｒａｍセル Withdrawn JP2009004074A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0703955A FR2916895B1 (fr) 2007-06-04 2007-06-04 Cellule memoire sram asymetrique a 4 transistors double grille

Publications (2)

Publication Number Publication Date
JP2009004074A JP2009004074A (ja) 2009-01-08
JP2009004074A5 true JP2009004074A5 (enExample) 2011-06-30

Family

ID=38935890

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008147062A Withdrawn JP2009004074A (ja) 2007-06-04 2008-06-04 ４つのダブル・ゲートのトランジスタを備える非対称ｓｒａｍセル

Country Status (5)

Country Link
US (1) US7733688B2 (enExample)
EP (1) EP2003650B1 (enExample)
JP (1) JP2009004074A (enExample)
DE (1) DE602008000257D1 (enExample)
FR (1) FR2916895B1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8072797B2 (en) * 2008-07-07 2011-12-06 Certichip Inc. SRAM cell without dedicated access transistors
US8363455B2 (en) 2008-12-04 2013-01-29 David Rennie Eight transistor soft error robust storage cell
TWI470631B (zh) * 2011-06-01 2015-01-21 Univ Nat Chiao Tung 雙埠次臨界靜態隨機存取記憶體單元
CN116230053B (zh) * 2023-03-01 2023-12-22 芯立嘉集成电路(杭州)有限公司 一种四晶体管静态随机存取存储器和存取方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6442060B1 (en) 2000-05-09 2002-08-27 Monolithic System Technology, Inc. High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process
KR100560948B1 (ko) 2004-03-31 2006-03-14 매그나칩 반도체 유한회사 6 트랜지스터 듀얼 포트 에스램 셀
JP4795653B2 (ja) * 2004-06-15 2011-10-19 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7532501B2 (en) * 2005-06-02 2009-05-12 International Business Machines Corporation Semiconductor device including back-gated transistors and method of fabricating the device
US7313012B2 (en) * 2006-02-27 2007-12-25 International Business Machines Corporation Back-gate controlled asymmetrical memory cell and memory using the cell
FR2898432B1 (fr) * 2006-03-10 2008-04-11 Commissariat Energie Atomique Cellules memoire en technologie cmos double-grille dotee de transistors a deux grilles independantes
FR2910999B1 (fr) * 2006-12-28 2009-04-03 Commissariat Energie Atomique Cellule memoire dotee de transistors double-grille, a grilles independantes et asymetriques
US7710765B2 (en) * 2007-09-27 2010-05-04 Micron Technology, Inc. Back gated SRAM cell

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