DE602008000257D1 - Asymmetrische SRAM-Speicherzelle mit 4 Doppelgate-Transistoren - Google Patents
Asymmetrische SRAM-Speicherzelle mit 4 Doppelgate-TransistorenInfo
- Publication number
- DE602008000257D1 DE602008000257D1 DE602008000257T DE602008000257T DE602008000257D1 DE 602008000257 D1 DE602008000257 D1 DE 602008000257D1 DE 602008000257 T DE602008000257 T DE 602008000257T DE 602008000257 T DE602008000257 T DE 602008000257T DE 602008000257 D1 DE602008000257 D1 DE 602008000257D1
- Authority
- DE
- Germany
- Prior art keywords
- double
- memory cell
- gate transistors
- sram memory
- asymmetric sram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0703955A FR2916895B1 (fr) | 2007-06-04 | 2007-06-04 | Cellule memoire sram asymetrique a 4 transistors double grille |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE602008000257D1 true DE602008000257D1 (de) | 2009-12-17 |
Family
ID=38935890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE602008000257T Active DE602008000257D1 (de) | 2007-06-04 | 2008-05-26 | Asymmetrische SRAM-Speicherzelle mit 4 Doppelgate-Transistoren |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7733688B2 (enExample) |
| EP (1) | EP2003650B1 (enExample) |
| JP (1) | JP2009004074A (enExample) |
| DE (1) | DE602008000257D1 (enExample) |
| FR (1) | FR2916895B1 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8072797B2 (en) * | 2008-07-07 | 2011-12-06 | Certichip Inc. | SRAM cell without dedicated access transistors |
| US8363455B2 (en) | 2008-12-04 | 2013-01-29 | David Rennie | Eight transistor soft error robust storage cell |
| TWI470631B (zh) * | 2011-06-01 | 2015-01-21 | Univ Nat Chiao Tung | 雙埠次臨界靜態隨機存取記憶體單元 |
| CN116230053B (zh) * | 2023-03-01 | 2023-12-22 | 芯立嘉集成电路(杭州)有限公司 | 一种四晶体管静态随机存取存储器和存取方法 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6442060B1 (en) | 2000-05-09 | 2002-08-27 | Monolithic System Technology, Inc. | High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process |
| KR100560948B1 (ko) | 2004-03-31 | 2006-03-14 | 매그나칩 반도체 유한회사 | 6 트랜지스터 듀얼 포트 에스램 셀 |
| JP4795653B2 (ja) * | 2004-06-15 | 2011-10-19 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| US7532501B2 (en) * | 2005-06-02 | 2009-05-12 | International Business Machines Corporation | Semiconductor device including back-gated transistors and method of fabricating the device |
| US7313012B2 (en) * | 2006-02-27 | 2007-12-25 | International Business Machines Corporation | Back-gate controlled asymmetrical memory cell and memory using the cell |
| FR2898432B1 (fr) * | 2006-03-10 | 2008-04-11 | Commissariat Energie Atomique | Cellules memoire en technologie cmos double-grille dotee de transistors a deux grilles independantes |
| FR2910999B1 (fr) * | 2006-12-28 | 2009-04-03 | Commissariat Energie Atomique | Cellule memoire dotee de transistors double-grille, a grilles independantes et asymetriques |
| US7710765B2 (en) * | 2007-09-27 | 2010-05-04 | Micron Technology, Inc. | Back gated SRAM cell |
-
2007
- 2007-06-04 FR FR0703955A patent/FR2916895B1/fr not_active Expired - Fee Related
-
2008
- 2008-05-26 DE DE602008000257T patent/DE602008000257D1/de active Active
- 2008-05-26 EP EP08354031A patent/EP2003650B1/fr not_active Ceased
- 2008-05-29 US US12/155,074 patent/US7733688B2/en not_active Expired - Fee Related
- 2008-06-04 JP JP2008147062A patent/JP2009004074A/ja not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| US7733688B2 (en) | 2010-06-08 |
| FR2916895B1 (fr) | 2009-08-28 |
| US20080298118A1 (en) | 2008-12-04 |
| EP2003650B1 (fr) | 2009-11-04 |
| FR2916895A1 (fr) | 2008-12-05 |
| JP2009004074A (ja) | 2009-01-08 |
| EP2003650A1 (fr) | 2008-12-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |