JP2008547298A5 - - Google Patents

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Publication number
JP2008547298A5
JP2008547298A5 JP2008517616A JP2008517616A JP2008547298A5 JP 2008547298 A5 JP2008547298 A5 JP 2008547298A5 JP 2008517616 A JP2008517616 A JP 2008517616A JP 2008517616 A JP2008517616 A JP 2008517616A JP 2008547298 A5 JP2008547298 A5 JP 2008547298A5
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JP
Japan
Prior art keywords
memory cells
array
schedule
byte
index
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JP2008517616A
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English (en)
Japanese (ja)
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JP5162455B2 (ja
JP2008547298A (ja
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Priority claimed from US11/363,769 external-priority patent/US7657818B2/en
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Publication of JP2008547298A publication Critical patent/JP2008547298A/ja
Publication of JP2008547298A5 publication Critical patent/JP2008547298A5/ja
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Publication of JP5162455B2 publication Critical patent/JP5162455B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2008517616A 2005-06-22 2006-03-16 動的最小メモリインタリーブ Expired - Fee Related JP5162455B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US69288905P 2005-06-22 2005-06-22
US60/692,889 2005-06-22
US11/363,769 US7657818B2 (en) 2005-06-22 2006-02-28 Dynamic minimum-memory interleaving
US11/363,769 2006-02-28
PCT/IB2006/000629 WO2006136883A1 (en) 2005-06-22 2006-03-16 Dynamic minimum-memory interleaving

Publications (3)

Publication Number Publication Date
JP2008547298A JP2008547298A (ja) 2008-12-25
JP2008547298A5 true JP2008547298A5 (https=) 2009-04-16
JP5162455B2 JP5162455B2 (ja) 2013-03-13

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ID=36933450

Family Applications (1)

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JP2008517616A Expired - Fee Related JP5162455B2 (ja) 2005-06-22 2006-03-16 動的最小メモリインタリーブ

Country Status (5)

Country Link
US (1) US7657818B2 (https=)
EP (1) EP1900106A1 (https=)
JP (1) JP5162455B2 (https=)
CN (1) CN101204014B (https=)
WO (1) WO2006136883A1 (https=)

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EP2051387A1 (en) * 2007-10-15 2009-04-22 CoreOptics, Inc., c/o The Corporation Trust Center Receiver, interleaving and deinterleaving circuit and method
PL2056464T3 (pl) 2007-10-30 2013-04-30 Sony Corp Urządzenie i sposób przetwarzania danych
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EP2301216A4 (en) * 2008-06-10 2016-06-22 Ikanos Communications Inc VECTED AD-ADDITIONAL ADDRESSING
JP5248677B2 (ja) 2008-07-01 2013-07-31 イカノス テクノロジー リミテッド メモリ削減されたベクトル化されたｄｓｌ
US8190848B2 (en) * 2008-07-28 2012-05-29 Lantiq Deutschland Gmbh Interleaver memory allocation method and apparatus
US8572456B1 (en) * 2009-05-22 2013-10-29 Altera Corporation Avoiding interleaver memory conflicts
US8296624B2 (en) * 2009-06-30 2012-10-23 Comcast Cable Communications, Llc Variable interleave data transmission
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EP3001572A1 (en) * 2014-09-29 2016-03-30 Panasonic Corporation Interleaving by concatenation of convolutional and block interleaving
KR20220162814A (ko) 2014-09-29 2022-12-08 파나소닉 홀딩스 코퍼레이션 콘볼루션 인터리버와 콘볼루션 디인터리버 및 콘볼루션 인터리빙 방법과 콘볼루션 디인터리빙 방법
US10033483B2 (en) * 2015-05-18 2018-07-24 Microsoft Technology Licensing, Llc Adjustable interleaving for communication data
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CN104993837B (zh) * 2015-07-24 2018-08-03 丽水博远科技有限公司 一种卷积交织方法和卷积交织器
WO2018187902A1 (en) 2017-04-10 2018-10-18 Qualcomm Incorporated An efficient interleaver design for polar codes
CN109495207B (zh) * 2017-09-11 2021-08-10 上海诺基亚贝尔股份有限公司 用于在无线通信系统中交织数据的方法和设备
CN109495210B (zh) * 2017-09-13 2020-07-31 上海诺基亚贝尔股份有限公司 用于在无线通信系统中交织数据的方法、设备和计算机可读存储介质
US11036642B2 (en) * 2019-04-26 2021-06-15 Intel Corporation Architectural enhancements for computing systems having artificial intelligence logic disposed locally to memory
CN115390545A (zh) * 2022-08-16 2022-11-25 北京经纬恒润科技股份有限公司 车辆诊断方法、装置、设备、可读存储介质及程序产品

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