JP2008532307A - 半導体パッケージ及び作成パッケージを製造する方法 - Google Patents

半導体パッケージ及び作成パッケージを製造する方法 Download PDF

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Publication number
JP2008532307A
JP2008532307A JP2007557647A JP2007557647A JP2008532307A JP 2008532307 A JP2008532307 A JP 2008532307A JP 2007557647 A JP2007557647 A JP 2007557647A JP 2007557647 A JP2007557647 A JP 2007557647A JP 2008532307 A JP2008532307 A JP 2008532307A
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Prior art keywords
resin layer
layer
protective layer
package
interconnect
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Japanese (ja)
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JP2008532307A5 (enExample
Inventor
フェーン ニコラース ジェイ エイ ファン
ロナルド デッケル
コエン シー タク
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Koninklijke Philips NV
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Koninklijke Philips NV
Koninklijke Philips Electronics NV
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    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Control Of Vending Devices And Auxiliary Devices For Vending Devices (AREA)
  • Bipolar Transistors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
JP2007557647A 2005-03-02 2006-02-27 半導体パッケージ及び作成パッケージを製造する方法 Pending JP2008532307A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05101593 2005-03-02
PCT/IB2006/050599 WO2006092754A2 (en) 2005-03-02 2006-02-27 A method of manufacturing a semiconductor packages and packages made

Publications (2)

Publication Number Publication Date
JP2008532307A true JP2008532307A (ja) 2008-08-14
JP2008532307A5 JP2008532307A5 (enExample) 2009-04-16

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US (1) US20080150118A1 (enExample)
EP (1) EP1856728B1 (enExample)
JP (1) JP2008532307A (enExample)
CN (1) CN100514591C (enExample)
AT (1) ATE412251T1 (enExample)
DE (1) DE602006003316D1 (enExample)
TW (1) TW200711081A (enExample)
WO (1) WO2006092754A2 (enExample)

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EP1905083A2 (en) * 2005-07-01 2008-04-02 Koninklijke Philips Electronics N.V. Electronic device
JP2009516369A (ja) * 2005-11-11 2009-04-16 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ チップアセンブリ及びそのチップアセンブリの製造方法
JP4956128B2 (ja) * 2006-10-02 2012-06-20 ルネサスエレクトロニクス株式会社 電子装置の製造方法
US8093689B2 (en) * 2007-07-02 2012-01-10 Infineon Technologies Ag Attachment member for semiconductor sensor device
US8114708B2 (en) * 2008-09-30 2012-02-14 General Electric Company System and method for pre-patterned embedded chip build-up
TW201114003A (en) * 2008-12-11 2011-04-16 Xintec Inc Chip package structure and method for fabricating the same
US8072041B2 (en) * 2009-04-08 2011-12-06 Finisar Corporation Passivated optical detectors with full protection layer
CN102422338B (zh) * 2009-05-02 2015-04-01 株式会社半导体能源研究所 显示设备
US8212340B2 (en) * 2009-07-13 2012-07-03 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8952519B2 (en) * 2010-01-13 2015-02-10 Chia-Sheng Lin Chip package and fabrication method thereof
JP5521862B2 (ja) * 2010-07-29 2014-06-18 三菱電機株式会社 半導体装置の製造方法
US10446442B2 (en) * 2016-12-21 2019-10-15 Globalfoundries Inc. Integrated circuit chip with molding compound handler substrate and method
KR20180136148A (ko) * 2017-06-14 2018-12-24 에스케이하이닉스 주식회사 범프를 구비하는 반도체 장치
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EP1856728A2 (en) 2007-11-21
CN101133484A (zh) 2008-02-27
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ATE412251T1 (de) 2008-11-15
WO2006092754A3 (en) 2007-01-18
US20080150118A1 (en) 2008-06-26
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EP1856728B1 (en) 2008-10-22
TW200711081A (en) 2007-03-16

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