JP2008523470A5 - - Google Patents

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Publication number
JP2008523470A5
JP2008523470A5 JP2007544553A JP2007544553A JP2008523470A5 JP 2008523470 A5 JP2008523470 A5 JP 2008523470A5 JP 2007544553 A JP2007544553 A JP 2007544553A JP 2007544553 A JP2007544553 A JP 2007544553A JP 2008523470 A5 JP2008523470 A5 JP 2008523470A5
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JP
Japan
Prior art keywords
obtaining
design data
rule
predictions
violation
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JP2007544553A
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English (en)
Japanese (ja)
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JP4763716B2 (ja
JP2008523470A (ja
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Priority claimed from US10/904,950 external-priority patent/US7240310B2/en
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Publication of JP2008523470A publication Critical patent/JP2008523470A/ja
Publication of JP2008523470A5 publication Critical patent/JP2008523470A5/ja
Application granted granted Critical
Publication of JP4763716B2 publication Critical patent/JP4763716B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007544553A 2004-12-07 2005-12-05 回路評価のための方法、システム及びプログラム Expired - Fee Related JP4763716B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/904,950 US7240310B2 (en) 2004-12-07 2004-12-07 Method, system and program product for evaluating a circuit
US10/904,950 2004-12-07
PCT/US2005/043690 WO2006062827A2 (en) 2004-12-07 2005-12-05 Method, system and program product for evaluating a circuit

Publications (3)

Publication Number Publication Date
JP2008523470A JP2008523470A (ja) 2008-07-03
JP2008523470A5 true JP2008523470A5 (enExample) 2008-10-09
JP4763716B2 JP4763716B2 (ja) 2011-08-31

Family

ID=36575834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007544553A Expired - Fee Related JP4763716B2 (ja) 2004-12-07 2005-12-05 回路評価のための方法、システム及びプログラム

Country Status (5)

Country Link
US (1) US7240310B2 (enExample)
JP (1) JP4763716B2 (enExample)
CN (1) CN101375282B (enExample)
TW (1) TW200632701A (enExample)
WO (1) WO2006062827A2 (enExample)

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US8630917B2 (en) * 2005-06-09 2014-01-14 At&T Intellectual Property Ii, L.P. Arrangement for guiding user design of comprehensive product solution using on-the-fly data validation
CN101122622B (zh) * 2006-08-09 2011-05-04 鸿富锦精密工业（深圳）有限公司 信号线分支线段长度检查系统及方法
US8032338B2 (en) 2008-06-13 2011-10-04 Power Integrations, Inc. Method and apparatus for design of a power supply
US8782577B2 (en) * 2010-07-24 2014-07-15 Cadence Design Systems, Inc. Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness
US8694950B2 (en) 2010-07-24 2014-04-08 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing electronic circuit designs with electrical awareness
CN102651038B (zh) * 2011-02-24 2015-06-17 益华公司 用于电力输送网络分析的方法和系统
US8539422B2 (en) 2011-02-24 2013-09-17 Cadence Design Systems, Inc. Method and system for power delivery network analysis
JP5182973B1 (ja) * 2011-10-19 2013-04-17 三菱航空機株式会社 配線の接続確認システム
US20150356232A1 (en) * 2014-06-06 2015-12-10 Synopsys, Inc. Method and System for Generating a Circuit Design, Method for Calibration of an Inspection Apparatus and Method for Process Control and Yield Management
CN112084294B (zh) * 2020-09-14 2022-07-26 重庆长安新能源汽车科技有限公司 一种基于人工智能的整车电磁兼容分级管理方法
WO2022183490A1 (en) 2021-03-05 2022-09-09 Paypal, Inc. Software process modification platform for compliance

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EP0186874B1 (en) * 1984-12-26 1994-06-08 Hitachi, Ltd. Method of and apparatus for checking geometry of multi-layer patterns for IC structures
US5062054A (en) * 1988-03-10 1991-10-29 Matsushita Electric Industrial Co., Ltd. Layout pattern generation and geometric processing system for LSI circuits
US5051938A (en) * 1989-06-23 1991-09-24 Hyduke Stanley M Simulation of selected logic circuit designs
DE69427417T2 (de) * 1993-03-08 2002-05-29 Koninklijke Philips Electronics N.V., Eindhoven PCB-Simulation auf der Basis von reduzierten Ersatzschaltungen
US5774367A (en) * 1995-07-24 1998-06-30 Motorola, Inc. Method of selecting device threshold voltages for high speed and low power
JP2874628B2 (ja) * 1996-01-30 1999-03-24 日本電気株式会社 論理回路の最適化装置及びその方法
US6090151A (en) * 1997-07-01 2000-07-18 Motorola, Inc. Electronic device parameter estimator and method therefor
JPH11120215A (ja) * 1997-10-14 1999-04-30 Mitsubishi Electric Corp 最適解探索支援装置
US6212490B1 (en) * 1998-06-24 2001-04-03 S3 Incorporated Hybrid circuit model simulator for accurate timing and noise analysis
JP2000029920A (ja) * 1998-07-13 2000-01-28 Mitsubishi Electric Corp シミュレーション装置、シミュレーション方法およびシミュレーションプログラムを記録した媒体
US6321186B1 (en) * 1999-05-03 2001-11-20 Motorola, Inc. Method and apparatus for integrated circuit design verification
DE60002897D1 (de) * 1999-08-31 2003-06-26 Sun Microsystems Inc System und verfahren zur analyse von störsignalen bei gleichzeitigem schalten
US6651228B1 (en) * 2000-05-08 2003-11-18 Real Intent, Inc. Intent-driven functional verification of digital designs
JP2002259481A (ja) * 2000-05-11 2002-09-13 Fujitsu Ltd ノイズ対策決定方法及び装置、記憶媒体並びにコンピュータプログラム
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JP2002073719A (ja) * 2000-08-31 2002-03-12 Hitachi Ltd 回路動作モデル記述の生成方法および論理設計検証装置
JP2002108960A (ja) * 2000-10-03 2002-04-12 Fujitsu Ltd 配置・配線処理システム
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JP2002259478A (ja) * 2001-02-28 2002-09-13 Nec Corp 統合デジタル回路設計システム及び設計方法
CN1258729C (zh) * 2003-11-14 2006-06-07 清华大学 基于虚拟模块的大规模混合模式布图方法

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