JP2008311347A - 半導体モジュール及びその製造方法 - Google Patents

半導体モジュール及びその製造方法 Download PDF

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Publication number
JP2008311347A
JP2008311347A JP2007156303A JP2007156303A JP2008311347A JP 2008311347 A JP2008311347 A JP 2008311347A JP 2007156303 A JP2007156303 A JP 2007156303A JP 2007156303 A JP2007156303 A JP 2007156303A JP 2008311347 A JP2008311347 A JP 2008311347A
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JP
Japan
Prior art keywords
interposer
semiconductor chip
tape substrate
semiconductor module
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2007156303A
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English (en)
Japanese (ja)
Other versions
JP2008311347A5 (enExample
Inventor
Yoshihide Nishiyama
佳秀 西山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2007156303A priority Critical patent/JP2008311347A/ja
Publication of JP2008311347A publication Critical patent/JP2008311347A/ja
Publication of JP2008311347A5 publication Critical patent/JP2008311347A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Wire Bonding (AREA)
JP2007156303A 2007-06-13 2007-06-13 半導体モジュール及びその製造方法 Withdrawn JP2008311347A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007156303A JP2008311347A (ja) 2007-06-13 2007-06-13 半導体モジュール及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007156303A JP2008311347A (ja) 2007-06-13 2007-06-13 半導体モジュール及びその製造方法

Publications (2)

Publication Number Publication Date
JP2008311347A true JP2008311347A (ja) 2008-12-25
JP2008311347A5 JP2008311347A5 (enExample) 2010-07-22

Family

ID=40238719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007156303A Withdrawn JP2008311347A (ja) 2007-06-13 2007-06-13 半導体モジュール及びその製造方法

Country Status (1)

Country Link
JP (1) JP2008311347A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012129555A (ja) * 2009-01-20 2012-07-05 Altera Corp 挿入層上に配置されたコンデンサーを有するｉｃパッケージ
US9160048B2 (en) 2012-06-04 2015-10-13 Fujitsu Limited Electronic device with terminal circuits

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012129555A (ja) * 2009-01-20 2012-07-05 Altera Corp 挿入層上に配置されたコンデンサーを有するｉｃパッケージ
JP2012518893A (ja) * 2009-01-20 2012-08-16 アルテラ コーポレイション 挿入層上に配置されたコンデンサーを有するｉｃパッケージ
CN102362347B (zh) * 2009-01-20 2016-11-09 阿尔特拉公司 具有布置在插入层上的电容器的集成电路封装件
US9160048B2 (en) 2012-06-04 2015-10-13 Fujitsu Limited Electronic device with terminal circuits

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