JP2008281406A - Board inspection device and board inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a board inspection device and an inspection method capable of shortening an inspection time. <P>SOLUTION: This board inspection device 20 capable of processing inspection of a plurality (M) of wiring patterns forming a plurality of nets (L) in parallel in a simultaneously-inspectable object number (N) unit, when performing conduction inspection of the wiring patterns on a circuit board 10, is equipped with an inspection probe 22 to be pressed on and contacted with an inspection point of the wiring patterns on the circuit board, a scanner means 24 for selecting an output from a wiring pattern selected by an inspection object selection means in the order of inspection, a combination circuit means 26 for combining outputs from each wiring pattern which is an inspection object, and voltage sources 28 to the number of N and a current detection means 32 for applying an inspection voltage to each wiring pattern which is the inspection object and detecting a current. The inspection object selection means for selecting the wiring pattern imparts the order of priority to each simultaneously-inspectable object, and executes selection based on an arrangement table wherein a wiring pattern of a net having the large number of wires is selected as an inspection object having a high order of priority. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a substrate inspection apparatus and a substrate inspection method, and more specifically to a substrate inspection apparatus and a substrate inspection method capable of processing a plurality of wiring patterns in parallel during a continuity inspection of wiring patterns on a circuit board.

  Conventionally, a continuity test for a circuit board having a plurality of wiring patterns has been performed by determining that a predetermined wiring pattern is equal to or less than a certain resistance value using a board inspection apparatus.

In this substrate inspection, a pair of inspection probes of a substrate inspection apparatus are pressed against two inspection points formed on both surfaces of the substrate, a predetermined inspection voltage is applied between the two inspection points, and a flowing current is generated. taking measurement. When the resistance value R = V / I of the wiring pattern between two inspection points is calculated from the inspection voltage value V and the detected current value I, and the resistance value R is equal to or less than a predetermined threshold value R _REF The conductive state of the wiring pattern is determined to be good.

  FIG. 1 is a diagram for explaining this board inspection method, and is a schematic view of a circuit board 100 as seen from a cross section in the thickness direction. It is assumed that all wiring patterns are shown in the figure. A plurality of wiring patterns 102 are formed on the circuit board 100. Here, the electrically connected wiring pattern network is referred to as a net. In FIG. 1, nets A to H are formed on the circuit board 100.

  In such a circuit board 100, continuity tests are performed in the order of net A, net B,. In each net, one reference inspection point is determined, and a continuity inspection is sequentially performed with the remaining inspection points. That is, the continuity inspection of the wiring pattern between the reference inspection point P1 and the inspection point P2, the wiring pattern between P1 and P3,..., The wiring pattern between P1 and P7 is sequentially performed on the net A. After the inspection on the net A is completed, the same inspection is sequentially performed on the net B, net C,.

  Specifically, as shown in FIG. 2, upper and lower inspection probe groups 104 u and 104 d are arranged on both surfaces of the circuit board 102, and these probes are pressed against the inspection point P. The upper and lower inspection probe groups 104u and 104d are provided with upper and lower scanners 106u and 106d, respectively, and one switch is connected to each inspection probe. The switches of the upper and lower scanners 106u and 106d are closed one by one, and the other switches are opened. A test voltage is applied from the DC voltage source 112 and the flowing current is measured by the current detection means 114. When the inspection of one wiring pattern is completed, the switches of the upper and lower scanners 106u and 106d are switched in accordance with the next wiring pattern.

  The present inventor is not aware of the existence of a published prior patent application relating to a substrate inspection apparatus capable of processing a plurality of wiring patterns in parallel when conducting a continuity inspection of a circuit board wiring pattern.

  In such a conventional substrate inspection apparatus, a continuity inspection is always performed on one wiring pattern 102, and a relatively long inspection time is required to sequentially inspect all the wiring patterns.

  For this reason, it has been desired to shorten the circuit board inspection time.

  Therefore, an object of the present invention is to provide a substrate inspection apparatus that can reduce the time required for inspection.

  Therefore, an object of the present invention is to provide a substrate inspection method capable of reducing the time required for inspection.

  In view of the above object, the substrate inspection apparatus according to the present invention can simultaneously inspect a plurality (M) of wiring patterns forming a plurality of nets (L) when conducting a continuity inspection of a circuit board wiring pattern. A board inspection apparatus capable of parallel processing in units of the number of objects (N), wherein an inspection probe is pressed against an inspection point formed on the wiring pattern that appears on the surface of the circuit board, and each inspection order Further, a scanner means for selecting an output from the wiring pattern selected by the inspection object selection means for selecting a plurality (N) of wiring patterns to be inspected, and an output from the scanner means for each individual to be inspected The combinational circuit means combined with the output corresponding to each wiring pattern and the inspection voltage is applied to each wiring pattern to be inspected to detect the flowing current. The inspection object selection means for selecting the wiring pattern including a pressure source and a current detection means assigns a priority to the simultaneously inspectable objects (number N), and assigns a priority to the wiring pattern of the net having a large number of wirings. It is implemented based on the arrangement table selected as a high inspection target.

  Furthermore, in the board inspection apparatus, the scanner means has upper and lower scanners arranged on both sides of the circuit board, and the upper and lower scanners are each based on the number (N) of simultaneously testable objects. The inspection object selection means for selecting the output from the N inspection probes and selecting the wiring pattern has N inspection points for the wiring pattern to be inspected with respect to the upper surface or the lower surface of the circuit board. Under the condition that the following is true, priorities are assigned to the simultaneously inspectable objects (number N), and the wiring pattern of the net having a large number of wirings is implemented based on an arrangement table sequentially selected as inspection objects with high priorities. You may do it.

  Furthermore, in the board inspection apparatus, the inspection object selection means for selecting the wiring pattern further arranges the inspection time necessary for each of the wiring patterns to be simultaneously inspected for each inspection order, so that the wiring to be inspected You may make it implement based on the arrangement | positioning table | surface which rearranged the pattern.

  Furthermore, in the substrate inspection method according to the present invention, when conducting a continuity inspection of a circuit board wiring pattern, a plurality of (M) wiring patterns forming a plurality of nets (L) can be simultaneously inspected (number N ) A substrate inspection method that performs parallel processing in units, and for each inspection order, a plurality (N) of wiring patterns to be simultaneously inspected are selected based on the arrangement table, and the inspection voltage is set to the plurality (N ) To each of the wiring patterns, and after a predetermined time, currents flowing through the plurality of (N) wiring patterns are detected, and the plurality of (N) wiring patterns are detected from the inspection voltage value and the detected current value. The step of calculating individual resistance values and comparing the calculated resistance value with a reference resistance value to determine whether the wiring pattern is good or bad includes the step of assigning a priority to the simultaneously inspectable target (number N). Of the net with many wires Are elected line pattern as high priority inspected.

  Furthermore, in the substrate inspection method, the layout table further includes a layout table in which the wiring patterns to be inspected are rearranged in order to align the inspection time required for each wiring pattern to be simultaneously inspected for each inspection order. It is good.

  Furthermore, in the board inspection method, an inspection time may be set in advance for each inspection order, and the inspection time may be determined according to the longest wiring pattern length among the wiring patterns that can be simultaneously inspected.

  According to the present invention, it is possible to provide a substrate inspection apparatus capable of reducing the time required for inspection.

  Therefore, according to the present invention, it is possible to provide a substrate inspection method capable of reducing the time required for inspection.

  Hereinafter, embodiments of a substrate inspection apparatus and a substrate inspection method according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  One of the features of the present embodiment is a substrate inspection apparatus and a substrate inspection method that can process a plurality of wiring patterns in parallel during the continuity inspection of the wiring patterns on the substrate. In order to enable parallel processing of the continuity inspection, there is a characteristic in the selection method of the inspection target (that is, the wiring pattern to be inspected) and the substrate inspection apparatus. These will be described in order.

[Selection method for inspection]
For convenience of explanation, it is assumed that the board inspection apparatus (see FIG. 7) is an apparatus capable of parallel processing of four inspection inspections. In the continuity inspection, one wiring pattern can be inspected by a set of two inspection probes. Therefore, among a plurality of inspection probes pressed and contacted from both the upper and lower surfaces of the circuit board, a total of eight inspection probes including arbitrarily selected upper four inspection probes and lower four inspection probes. Conduct continuity test using. For each inspection, eight inspection probes are divided into four groups of two, and a continuity test is simultaneously performed on four electrically independent wiring patterns.

(First arrangement for inspection)
3 and 4 are diagrams illustrating a first arrangement of inspection objects. Here, for example, the wiring pattern 12 is formed on the circuit board 10 from eight nets A to H. The nets are electrically independent from each other (that is, in an insulated state) and are electrically connected in the same net. The wiring pattern 12 forming each net forms an inspection point P used for continuity inspection on the upper surface 10 u and / or the rear surface 10 d of the circuit board 10.

  FIG. 3 is a diagram illustrating a method for specifying each inspection point. In order to simplify the explanation, the eight nets are illustrated in order from the left to the right in order from the net with many inspection points, and are referred to as net A to net H. The inspection points of each net are preliminarily set as one reference inspection point P1 (circled in the figure) and other inspection points P2, P3,.

  The net A has seven inspection points, and includes a reference inspection point P1 and other inspection points P2 to P7. The continuity test for the net A is sequentially performed between the reference test point P1 and the other test points PP2 to P7. That is, the continuity test is sequentially performed on the wiring pattern between P1 and P2, the wiring pattern between P1 and P3,..., The wiring pattern between P1 and P7.

  The net B has six inspection points and includes a reference inspection point P1 and other inspection points P2 to P6. Similarly, the continuity test for the net B is sequentially performed between the reference test point P1 and the other test points P2 to P6. The same applies to the other nets C to H.

  At this time, it is preferable to set the reference inspection points P1 so as to be approximately the same number on the upper surface 10u and the lower surface 10d of the circuit board. As described above, the board inspection apparatus can simultaneously perform continuity inspection on four electrically independent wiring patterns using a total of eight inspection probes, four on each of the upper and lower sides. For example, if only the inspection point on the upper surface 10u of the circuit board is set as the reference inspection point P1, the upper four inspection probes are occupied by the reference inspection point P1 of each net. As a result, the inspection point P that is a pair of the reference inspection point P1 in each net is always limited to the inspection point P on the lower surface of the circuit board, so that there is little room for selection, and substantially simultaneous conduction of four wiring patterns. This is because the inspection cannot be performed.

  Next, the first arrangement of the inspection object will be described using the arrangement table shown in FIG. FIG. 4 shows the first, second, third, and third of the objects that can be inspected at the same time (hereinafter also referred to as “inspection object”) in the upper horizontal direction, and the inspection order in the left vertical direction. The first time, the second time,..., The ninth time. In each column specified by the inspection object and the inspection order, attributes of the wiring pattern actually selected as the inspection object A to Ding, that is, the net, the inspection point-the inspection point, and the position of those inspection points (that is, the circuit) The top surface (top) or bottom surface (bottom) of the substrate is shown.

  This first arrangement is determined based on the following idea.

  (a) When the inspection order is the same, the wiring patterns 12 belonging to different nets are assigned to the inspection object A, B, B, and Ding that can be inspected simultaneously. That is, when viewed on a net basis, the two wiring patterns are not inspected for continuity.

  (b) When the priority order of inspection objects is the order of A, B, B, and Ding, the inspection priority A, B, B, and Ding are assigned to the inspection priority A, B, B, and Ding in the order of the number of inspection points. Specifically, the net A is assigned to the inspection subject A, the net B is assigned to the inspection subject B, the net C is assigned to the inspection subject cage, and the net D is assigned to the inspection subject.

  (c) Up to four inspection probes can be used simultaneously for inspection. Therefore, if inspection points are assigned to all four inspection probes on one of the upper surface and the lower surface, thereafter, an inspected wiring pattern having inspection points on that surface cannot be assigned.

  Looking again at the first arrangement of inspection objects shown in FIGS. 3 and 4, the net A having the largest number is assigned to the inspection object A. Specifically, in the network A, P1 (up) -P2 (up), P1 (up) -P3 (up), P1 (up) -P4 (down), P1 (up) -P5 (down), P1 Six wiring patterns of (upper) -P6 (lower) and P1 (upper) -P7 (lower) are inspected. Since these wiring patterns to be inspected cannot be inspected at the same time, they are assigned to the inspection target in the first to sixth inspection orders, respectively.

  Similarly, the next largest net B is assigned to the inspection object B. Specifically, in the net B, P1 (lower) -P2 (lower), P1 (lower) -P3 (lower), P1 (lower) -P4 (upper), P1 (lower) -P5 (upper), P1 (Lower) -P6 (Upper) 5 wiring patterns are inspected. These wiring patterns to be inspected are assigned to the inspection target B in the first to fifth inspection orders, respectively.

  Similarly, in the net C, four wiring patterns are inspected. These to-be-inspected wiring patterns are assigned to the inspection target bags in the first to fourth inspection orders, respectively.

  The net D is inspected for three wiring patterns of P1 (lower) -P2 (upper), P1 (lower) -P3 (lower), and P1 (lower) -P4 (lower). P1 (lower) -P2 (upper) is assigned to the inspection object in the inspection order once.

  However, P1 (bottom) -P3 (bottom) of the net D cannot be assigned to the second inspection target in the inspection order. This is because, in the second inspection order, three inspection probes on the upper surface and the lower surface are already used by the nets A, B, and C, and the inspection probes on the lower surface are insufficient in P1 (lower) -P3 (lower). . For the same reason, P1 (lower) -P3 (lower) cannot be assigned to the third to fourth inspection orders. Therefore, P1 (lower) -P3 (lower) is assigned to the fifth inspection order. For the same reason, P1 (lower) -P4 (lower) are assigned to the sixth inspection order.

  P1 (bottom) -P2 (bottom) of the net E cannot be assigned to the inspection target pieces in the inspection order 2 to 6 times for the same reason, and are assigned to the inspection target pieces in the inspection order of the seventh time.

  P1 (upper) -P2 (lower) of the next net F considers the sixth inspection order with many blanks and assigns it to the inspection target cage. P1 (upper) -P3 (lower) are assigned to the inspection object basket in the seventh inspection order.

  In the same manner, the wiring patterns to be inspected are assigned in the respective inspection orders to the wiring patterns A, B, B, and Ding that can be simultaneously inspected, and the first arrangement table to be inspected is determined.

  In accordance with the first arrangement of the inspection object shown in FIG. 4, the following four wiring patterns are simultaneously performed as the first, second, second, and second in the first continuity test.

(1) As a wiring pattern former, a wiring pattern between the reference inspection point P1 (upper) and the inspection point P2 (upper) of the net A
(2) As a wiring pattern B, a wiring pattern between the reference inspection point P1 (bottom) and inspection point P2 (bottom) of the net B
(3) A wiring pattern between the reference inspection point P1 (upper) and the inspection point P2 (lower) of the net C as a wiring pattern 丙.
(4) A wiring pattern between the reference inspection point P1 (bottom) and the inspection point P2 (top) of the net D as a wiring pattern.

  In the next second inspection, the following four wiring patterns are simultaneously inspected.

(1) As a wiring pattern former, a wiring pattern between the reference inspection point P1 (upper) and the inspection point P3 (upper) of the net A
(2) As a wiring pattern B, a wiring pattern between the reference inspection point P1 (bottom) and the inspection point P3 (bottom) of the net B
(3) As a wiring pattern 丙, a wiring pattern between the reference inspection point P1 (upper) and the inspection point P3 (lower) of the net C
(4) As a wiring pattern, the wiring pattern between the reference inspection point P1 (bottom) and the inspection point P3 (top) of the net D In the next third inspection, the continuity inspection of the four wiring patterns shown in the figure Are performed simultaneously. Until the fourth to seventh inspections, the continuity inspection of the three wiring patterns shown in the figure is performed simultaneously. In the eighth inspection, the continuity inspection of the two wiring patterns shown in the figure is performed simultaneously.

  By assigning priorities to inspection objects that can be inspected simultaneously (Exhibit A, B, etc.) and assigning a net with a large number of wirings to inspection objects with a high priority, the selection method of inspection objects is uniquely determined. Therefore, by selecting a program, the method for selecting the inspection object can be computer processed. By storing in advance in a computer ROM or the like, a substrate inspection method described later can be implemented.

  As described above, in the board inspection apparatus described later, the inspection time can be shortened by simultaneously conducting the continuity inspection of the wiring pattern A, B, B, and Ding in each of the inspection orders 1 to 8.

(Second arrangement for inspection)
The second arrangement of the inspection object will be described using the arrangement tables shown in FIGS. The arrangement shown in the arrangement table of FIG. 5 is an arrangement in which the first arrangement (see FIG. 3) is further rearranged to shorten the inspection time.

  In the continuity inspection of the circuit board 10, a pair of inspection probes are pressed and contacted with the wiring pattern 12 to be inspected, a predetermined inspection voltage is applied, and a current value is detected when the flowing current reaches a certain level. The time when this current reaches a constant (that is, the time until the wiring pattern to be inspected is charged up to a predetermined voltage) depends on the resistance value of the wiring pattern to be inspected. When determining the resistance value of the wiring pattern, the determination threshold value (determination range) is changed according to the resistance value. For this reason, since the determination range of the resistance value of the wiring pattern is changed depending on the resistance value of the wiring pattern, the inspection time is affected according to this change. In this way, the inspection time required for each inspection order is determined by the wiring pattern to be inspected having the longest inspection time among the wiring patterns that are simultaneously inspected.

  Therefore, it is preferable to further rearrange the wiring patterns assigned to the inspection subject A, B, B, and Ding that can be simultaneously inspected by the first arrangement from the viewpoint of smoothing the inspection time.

  If only one wiring pattern with a long inspection time is assigned to the inspection target A, B, Tsuji, and Ding, even if the inspection of other wiring patterns is completed, the inspection is performed until the inspection time required for the long wiring pattern is completed. Does not end. Therefore, the inspection pattern assigned as the first arrangement is replaced (rearranged), and the required inspection times of the inspection subject A, B, B, and Ding are aligned side by side (that is, smoothed) ) This rearrangement can shorten the inspection time when simultaneously inspecting four inspected wiring patterns having a short inspection time. As a result, the inspection time can be shortened as a whole circuit board continuity inspection. This will be specifically described below.

  In general, the power supply / GND pattern wiring has a relatively small resistance value, and the signal pattern wiring has a relatively high resistance value. Furthermore, when the resistance value of the signal system pattern wiring is known to some extent, the wiring pattern is divided into a power source / GND system wiring pattern, a signal system wiring pattern with a small resistance value, and a signal system with a large resistance value. It can also be divided into wiring patterns. Further, when the length of the wiring pattern can be obtained from the data when the wiring pattern forming mask is manufactured by CAD from the logic design information of the circuit board, the resistance value of the wiring pattern is proportional to the length of the wiring pattern. It is good.

  Alternatively, a non-defective circuit board may be selected and used as a criterion for continuity inspection. Using the board inspection device, the resistance value data of each wiring pattern is taken up from the non-defective circuit board, and a determination threshold value (determination range) for each wiring pattern is set based on this. The required inspection time can be determined according to the change / setting of the setting range. Here, the rearrangement in such a case will be specifically described.

  FIG. 6 shows the required inspection time of the inspected wiring pattern determined in the first arrangement (see FIG. 4) for each inspection order for the inspection target A, B, B, and Ding that can be inspected simultaneously. It is a thing. Since the inspection time is displayed as a time ratio, the unit is unnamed. In the first inspection order, the inspected wiring patterns having inspection times 3, 3, 2, and 2 are assigned to the inspection target A, B, B, and Ding, respectively. Similarly, in the second inspection order, the inspected wiring patterns with inspection times 4, 4, 3, and 3 are assigned to the inspection subject A, B, B, and Ding, respectively. The inspection order 3 and later are also shown in the same manner. In each inspection order, the longest inspection time is underlined.

  Here, in the third inspection order, the wiring pattern having the longest inspection time is the inspection time 4 (before rearrangement). Next is inspection time 3 for the inspection object. Therefore, the wiring pattern to be inspected in the inspection object cage in the third inspection order is replaced with the wiring pattern inspected (inspection time 3) in the inspection object cage in the seventh inspection order. The positions of the inspection points are all (upper) (lower), and there is no shortage of inspection probes. By this rearrangement, the wiring pattern with the longest inspection time becomes the inspection time 3 for the inspection object basket and the ditch.

  Similarly, in the fourth inspection order, the wiring pattern has the longest inspection time and the inspection time is 5 (before rearrangement). Next is inspection time 3 for inspection subject A and B. Accordingly, the wiring pattern to be inspected in the inspection object cage in the fourth inspection order is replaced with the wiring pattern inspected (inspection time 2) in the inspection object cage in the sixth inspection order. The positions of the inspection points are all (upper) (lower), and there is no shortage of inspection probes. By this rearrangement, the wiring pattern having the longest inspection time becomes inspection time 3 for the inspection subject A and the second inspection object.

  As a result, the wiring pattern with the longest inspection time increases from the inspection time 3 to 4 in the seventh inspection order. However, there is a decrease in the inspection time 1 at the third inspection order and the inspection time 3 at the fourth inspection order, and smoothing can be achieved as a whole.

  Regarding the creation of the second arrangement table, the selection method of the inspection object can be computer-processed by creating a program. By storing in advance in a computer ROM or the like, a substrate inspection method described later can be implemented.

  By carrying out such rearrangement, it is possible to shorten the continuity inspection time as a whole.

[Board inspection equipment]
(Inspection equipment)
FIG. 7 is a block diagram of the board inspection apparatus 20 that simultaneously inspects the four wiring patterns determined by the above-described inspection object selection method.

  The board inspection device 20 is located on both surfaces of the circuit board 10 and presses and contacts the inspection points. The upper and lower inspection probe groups 22u and 22d, and the upper and lower inspection probe groups select four inspection probes from each inspection probe group. The combination circuit 26 that receives the cables from the side scanners 24u and 24d and the upper and lower scanners to form four combinations corresponding to the four wiring patterns to be inspected, and the voltage source and current connected to each group Circuits 32-1 to 32-4 of detection means, a control unit 36 that controls these elements, and a monitor 38 that displays inspection results are provided.

  In this block diagram, the circuit board positioning mechanism, the inspection jig for fixing the inspection probe, the tester controller for controlling the scanner, and the circuit are usually provided in the substrate inspection apparatus 20 in order to simplify the drawing and make it easy to see. It should be noted that the driving mechanism for driving the substrate and the scanner is omitted. In this block diagram, only the minimum elements necessary for understanding the present embodiment are displayed.

  Each element will be described. The upper and lower inspection probe groups 22u and 22d have inspection probes that can press and contact all inspection points P formed on the circuit board 10.

  The upper and lower scanners 24u and 24d each have a switch (not shown) connected to one inspection probe, close the switch connected to the inspection point to be inspected, and open the other switches. In this embodiment, each of the upper and lower scanners connects the outputs from the four inspection probes to the combinational circuit 26.

  The combinational circuit 26 is a kind of selection circuit, and outputs 34u and 34d connected to eight inspection probes from the upper and lower scanners as an arrangement table (referred to as a desired first or second arrangement table). ), Four sets (37-1 to 37-4) of output combinations are made for every two pattern units to be inspected. The combinational circuit 26 sends the output of each group to the four voltage source and current detection circuit 32-1 to 32-4.

  The voltage source and current detection means circuits 32-1 to 32-4 are provided for each set, and each includes a variable DC voltage source 28 that applies a test voltage and a current detection means 30 that detects a flowing current.

  The control unit 36 includes a CPU that controls these elements, a RAM that is used for a storage area, a work area, and the like, a ROM that stores a program that executes the board inspection method, and the like (all not shown). It consists of a normal computer. A recording device (not shown) such as an HDD may be provided.

  The board inspection apparatus 20 simultaneously conducts a continuity inspection on the four inspected wiring patterns 12 on the circuit board. Eight corresponding inspection probes are selected by the upper and lower scanners 24u and 24d based on the arrangement table, and combined by the combination circuit 26 with outputs from two inspection probes corresponding to the wiring pattern 12 to be inspected. One voltage source and current detection circuit 32 is prepared for each set. Each set forms an electrically independent closed circuit, a predetermined inspection voltage is applied, and the flowing current is detected by the current detection means 30-1 to 30-4.

  In FIG. 7, the upper and lower scanners 24 u and 24 d connect outputs 34 u and 34 d from four inspection probes to the combinational circuit 26. However, the outputs from all the inspection probes belonging to the upper and lower inspection probe groups 22u and 22d may be sent to the combinational circuit 26 via the upper and lower scanners 24u and 24d. In other words, the upper and lower scanners 24u and 24d and the combinational circuit 26 may be connected by the number of cables corresponding to the number of inspection probes. In this case, the combinational circuit 26 selects eight outputs in which the switches of the upper and lower scanners 24u and 24d are closed, and makes a combination of one to two corresponding to the wiring pattern to be inspected. The signals are sent to the circuits 32-1 to 32-4 of the source and current detection means, respectively.

(Inspection method)
FIG. 8 is a flowchart of the substrate inspection method executed by the substrate inspection apparatus 20 of FIG. It is executed by the control unit 36 in accordance with a program stored in advance.

  In step S10, the inspection order is set. First, second,... Displayed in the left vertical direction of the arrangement table (see FIGS. 4 and 5) are set in order.

  In step S11, the inspection point P is determined from the arrangement table. For example, in the first inspection order of the second arrangement table, the inspection points P1 and P2 of the nets A, B, C, and D are respectively determined as the inspection target A to Ding.

  In step S12, the inspection time is set. This set inspection time is determined according to the determination range in the wiring patterns to be simultaneously inspected. Referring to FIG. 6, the wiring patterns with the longest inspection time are the wiring patterns of nets A and B, and the inspection time corresponding to these is set.

  In step S13, the inspection voltage V is applied from the inspection probe to the wiring pattern to be inspected. The inspection voltage is applied to each group electrically independently by the four voltage sources and the current detection means circuits 32-1 to 32-4.

  In step S14, it is determined whether the inspection time set in step S12 has been reached.

  In step S15, the flowing current value is measured in each group.

  In step S16, the resistance value R of the wiring pattern to be inspected is calculated for each group.

In step S17, it is determined in each group whether the resistance value R is equal to or less than a predetermined reference resistance value _RREF . If it is equal to or less than the reference resistance value R _REF , the process proceeds to step S18 and is determined to be good, and if it exceeds, the process proceeds to step S19 and is determined to be defective. If desired, the inspection results are displayed on the monitor sequentially or after completion of the inspection.

  In step S20, it is determined whether or not the inspection of all the wiring patterns shown in the arrangement table has been completed. If not, the process returns to step S10, and the inspection in the next inspection order is executed.

  As described above, the parallel processing of the continuity test for the four wiring patterns is performed.

[Alternative examples]
Additions, changes, deletions and improvements that can be easily implemented by those skilled in the art are included in the scope of the present invention. For example, the following matters can be mentioned.

  (1) In the embodiment, the simultaneous implementation of four wiring patterns has been described, but the present invention is not limited to this. The number of wiring patterns that can be simultaneously implemented is arbitrary. Corresponding to the determined number of wiring patterns, an arrangement table is created, the program is modified, and the scanner, combinational circuit, voltage source, current detection circuit, and the like are changed.

(2) Adoption of four-terminal measurement In the embodiment, when conducting a continuity test of one wiring pattern to be inspected, a pair of inspection probes are used to apply an inspection voltage and detect a flowing current.

  In recent years, in order to remove the contact resistance between the inspection probe and the wiring pattern to be inspected, four-terminal measurement in which the voltage terminal and the current terminal are separated has been adopted. Usually, one inspection probe is divided in the axial direction, or separated into a core member and a cylindrical member that concentrically surrounds it, and is electrically insulated into two terminals, a current terminal and a voltage terminal. .

  The present invention can also perform four-terminal measurement by employing such an inspection probe.

(3) Integration of the first arrangement and the second arrangement to be inspected In the explanation of the first arrangement, in the explanation using FIG. 3, the reference to the inspection point of the circuit board is given, and the reference inspection point P1 is set. Except for being optional.

  At this time, by setting the inspection points P2, P3, P4,... In the order closer to the reference inspection point P1 (shortest inspection target wiring pattern), the inspection target wiring pattern length in each inspection order is smoothed with a considerable probability. Can be planned. Furthermore, you may perform 2nd rearrangement as needed.

  (4) In the embodiment, the case where the inspection points are on both the upper surface and the lower surface of the circuit board has been described. However, the present invention can also be applied when the inspection point is on one (one side) of the upper surface and the lower surface of the circuit board.

[Advantages and effects of the embodiment]
(1) Since the continuity inspection of a plurality of wiring patterns can be performed simultaneously, the inspection time can be shortened.

  (2) As explained in the first allocation table, by assigning priorities to inspection targets (Exhibit A, B, etc.) that can be inspected at the same time, and assigning a net with a large number of wirings to inspection targets with a high priority The selection method of the inspection object is uniquely determined. Therefore, by selecting a program, the method for selecting the inspection object can be computer processed. For the same reason, the second arrangement table can also be computer-processed for selecting the inspection target.

  (3) As described in the second arrangement table, the inspection time can be further shortened by smoothing the wiring pattern length of each group (equalizing the pattern length).

[Others]
Although the embodiments of the substrate inspection apparatus and the substrate inspection method according to the present invention have been described above, the present invention is not limited to these embodiments. It is determined based on the technical scope of the present invention and the description of the appended claims.

FIG. 1 is a diagram for explaining the state of a wiring pattern on a circuit board. FIG. 2 is a diagram for explaining a conventional board inspection method for the circuit board of FIG. FIG. 3 is a diagram for explaining a method for specifying each inspection point on the circuit board in relation to the first arrangement of inspection targets. FIG. 4 is an arrangement table for explaining the inspection sequence of wiring patterns in relation to the first arrangement to be inspected. FIG. 5 is an arrangement table for explaining the inspection sequence of the wiring patterns in relation to the second arrangement to be inspected. FIG. 6 shows the inspection time of the to-be-inspected wiring pattern determined in the first arrangement table for each inspection order for the inspection subject A, B, B, and Ding that can be inspected at the same time. FIG. 7 is a block diagram of a board inspection apparatus capable of simultaneously inspecting four wiring patterns according to the present embodiment. FIG. 8 is a flowchart of a substrate inspection method executed by the substrate inspection apparatus of FIG.

Explanation of symbols

10: Circuit board, 12: Wiring pattern, 20: Board inspection device, 22u: Upper inspection probe group, 22d: Lower inspection probe group, 24u: Upper inspection scanner, 24d: Lower scanner, 26: Combination circuit, 28- 1 to 28-4: variable DC voltage source, 30-1 to 30-4: current detection means, 32-1 to 32-4: circuit of voltage source and current detection means, 36: control unit, 38: monitor, 100 : Circuit board, 102: wiring pattern, 104u: upper inspection probe group, 104d: lower inspection probe group, 106u: upper scanner, 106d: lower scanner, 112: DC voltage source, 114: current detection means,
A, B, C, D, E, F, G, H: Net, P1: Reference inspection point, P2, P3, ...: Inspection point,

Claims (6)

A circuit board inspection apparatus capable of performing parallel processing of a plurality (M) of wiring patterns forming a plurality of nets (L) in units of the number (N) that can be simultaneously inspected when conducting a continuity inspection of wiring patterns on a circuit board. There,
An inspection probe that is pressed against an inspection point formed on the wiring pattern that appears on the surface of the circuit board;
Scanner means for selecting an output from the wiring pattern selected by the inspection object selection means for selecting a plurality of (N) wiring patterns to be inspected for each inspection order;
Combinational circuit means for combining the output from the scanner means with the output corresponding to each wiring pattern to be inspected;
A number N of voltage sources and current detection means for detecting a flowing current by applying an inspection voltage to each wiring pattern to be inspected;
The inspection object selection means for selecting the wiring pattern assigns priorities to simultaneously inspectable objects (number N), and based on an arrangement table in which wiring patterns of nets with a large number of wirings are selected as inspection objects with high priorities. A substrate inspection apparatus to be implemented. The board inspection apparatus according to claim 1,
The scanner means has upper and lower scanners disposed on both sides of the circuit board,
The upper and lower scanners are each configured to select outputs from N inspection probes based on the number of simultaneously inspectable objects (N),
The inspection object selection means for selecting the wiring pattern is an object that can be inspected simultaneously (number N) under the condition that the number of inspection points of the wiring pattern to be inspected is N or less with respect to the upper or lower surface of the circuit board. A substrate inspection apparatus that is implemented based on an arrangement table in which priorities are assigned to the wiring patterns of the nets having a large number of wirings and sequentially selected as inspection targets with a high priority. The board inspection apparatus according to claim 1,
The inspection object selection means for selecting the wiring pattern is further arranged in an arrangement table in which the wiring patterns to be inspected are rearranged in order to align the inspection time required for each of the wiring patterns to be simultaneously inspected for each inspection order. A substrate inspection apparatus implemented based on the above. This is a substrate inspection method in which a plurality of (M) wiring patterns forming a plurality of nets (L) are processed in parallel in units of simultaneously inspectable objects (number N) when conducting a continuity inspection of circuit board wiring patterns. And
For each inspection order, a plurality (N) of wiring patterns to be subjected to simultaneous inspection are selected based on the layout table,
An inspection voltage is applied to each of the multiple (N) wiring patterns,
After a predetermined time, currents flowing through the plurality of (N) wiring patterns are detected,
From the inspection voltage value and the detected current value, the individual resistance values of the multiple (N) wiring patterns are calculated,
Comparing the calculated resistance value with a reference resistance value, and determining whether the wiring pattern is good or bad,
In the substrate inspection method, the arrangement table assigns priorities to the simultaneously inspectable objects (number N), and selects a wiring pattern of a net having a large number of wirings as an inspection object having a high priority. The substrate inspection method according to claim 4,
Further, the arrangement table is an arrangement table in which the wiring patterns to be inspected are rearranged in order to arrange the inspection time required for each of the wiring patterns to be inspected simultaneously for each inspection order. In the board | substrate inspection method of Claim 4 or 5,
A substrate inspection method in which an inspection time is set in advance for each inspection order, and the inspection time is determined according to the longest wiring pattern length among the wiring patterns that can be simultaneously inspected.

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