JP2008147472A5 - - Google Patents

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Publication number
JP2008147472A5
JP2008147472A5 JP2006333998A JP2006333998A JP2008147472A5 JP 2008147472 A5 JP2008147472 A5 JP 2008147472A5 JP 2006333998 A JP2006333998 A JP 2006333998A JP 2006333998 A JP2006333998 A JP 2006333998A JP 2008147472 A5 JP2008147472 A5 JP 2008147472A5
Authority
JP
Japan
Prior art keywords
semiconductor device
pad
lower package
fiducial mark
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006333998A
Other languages
English (en)
Other versions
JP5049573B2 (ja
JP2008147472A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from JP2006333998A external-priority patent/JP5049573B2/ja
Priority to JP2006333998A priority Critical patent/JP5049573B2/ja
Priority to KR1020070125260A priority patent/KR101571075B1/ko
Priority to US11/951,816 priority patent/US7642662B2/en
Priority to CN2007101990827A priority patent/CN101202262B/zh
Priority to TW096147388A priority patent/TWI453839B/zh
Publication of JP2008147472A publication Critical patent/JP2008147472A/ja
Publication of JP2008147472A5 publication Critical patent/JP2008147472A5/ja
Publication of JP5049573B2 publication Critical patent/JP5049573B2/ja
Application granted granted Critical
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Claims (4)

  1. 上パッケージのはんだボールと下パッケージのパッドとを直接接続させて形成される半導体装置において、
    前記パッドの一部がフィデューシャルマークを兼用し、
    前記フィデューシャルマークを兼用するパッドと、その他のパッドとは、形状が相違し、かつ面積が実質的に等しく形成されること
    を特徴とする半導体装置。
  2. 前記フィデューシャルマークを兼用するパッドが、前記下パッケージにおける対角位置に二箇所設けられること
    を特徴とする請求項１記載の半導体装置。
  3. 前記フィデューシャルマークを兼用するパッドが、前記下パッケージにおいて三角形を構成する位置に三箇所設けられること
    を特徴とする請求項１記載の半導体装置。
  4. キャリアに収納された下パッケージの位置を、下パッケージに設けられたフィデューシャルマークを兼用するパッドによって認識し、
    前記認識位置に基づいて、上パッケージのはんだボールと、下パッケージのパッドとの位置合わせを行い、それらを直接接続させて、半導体装置を形成すること
    を特徴とする半導体装置の製造方法。
JP2006333998A 2006-12-12 2006-12-12 半導体装置 Active JP5049573B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2006333998A JP5049573B2 (ja) 2006-12-12 2006-12-12 半導体装置
KR1020070125260A KR101571075B1 (ko) 2006-12-12 2007-12-05 반도체 장치 및 그 제조 방법
US11/951,816 US7642662B2 (en) 2006-12-12 2007-12-06 Semiconductor device and method of manufacturing the same
TW096147388A TWI453839B (zh) 2006-12-12 2007-12-12 半導體裝置及其製造方法
CN2007101990827A CN101202262B (zh) 2006-12-12 2007-12-12 半导体装置及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006333998A JP5049573B2 (ja) 2006-12-12 2006-12-12 半導体装置

Publications (3)

Publication Number Publication Date
JP2008147472A JP2008147472A (ja) 2008-06-26
JP2008147472A5 true JP2008147472A5 (ja) 2009-10-08
JP5049573B2 JP5049573B2 (ja) 2012-10-17

Family

ID=39517324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006333998A Active JP5049573B2 (ja) 2006-12-12 2006-12-12 半導体装置

Country Status (5)

Country Link
US (1) US7642662B2 (ja)
JP (1) JP5049573B2 (ja)
KR (1) KR101571075B1 (ja)
CN (1) CN101202262B (ja)
TW (1) TWI453839B (ja)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8618669B2 (en) * 2008-01-09 2013-12-31 Ibiden Co., Ltd. Combination substrate
US8415792B2 (en) * 2010-08-04 2013-04-09 International Business Machines Corporation Electrical contact alignment posts
JP5795196B2 (ja) 2011-06-09 2015-10-14 新光電気工業株式会社 半導体パッケージ
JP6207190B2 (ja) * 2013-03-22 2017-10-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9343386B2 (en) 2013-06-19 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment in the packaging of integrated circuits
KR102274742B1 (ko) * 2014-10-06 2021-07-07 삼성전자주식회사 패키지 온 패키지와 이를 포함하는 컴퓨팅 장치
US9953963B2 (en) * 2015-11-06 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit process having alignment marks for underfill
US11456259B2 (en) * 2019-03-27 2022-09-27 Pyxis Cf Pte. Ltd. Panel level packaging for devices
US11393759B2 (en) * 2019-10-04 2022-07-19 International Business Machines Corporation Alignment carrier for interconnect bridge assembly

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2833174B2 (ja) * 1990-08-22 1998-12-09 セイコーエプソン株式会社 半導体素子及びその実装方法
JP3284048B2 (ja) 1996-05-31 2002-05-20 東芝マイクロエレクトロニクス株式会社 半導体装置およびその製造方法
JP3535683B2 (ja) * 1997-01-09 2004-06-07 株式会社ルネサステクノロジ 位置認識用マーク付半導体装置
US6278193B1 (en) * 1998-12-07 2001-08-21 International Business Machines Corporation Optical sensing method to place flip chips
TW457545B (en) * 2000-09-28 2001-10-01 Advanced Semiconductor Eng Substrate to form electronic package
US6668449B2 (en) * 2001-06-25 2003-12-30 Micron Technology, Inc. Method of making a semiconductor device having an opening in a solder mask
KR100416000B1 (ko) * 2001-07-11 2004-01-24 삼성전자주식회사 다수의 핀을 갖는 부품이 실장되는 인쇄회로기판
US6570263B1 (en) * 2002-06-06 2003-05-27 Vate Technology Co., Ltd. Structure of plated wire of fiducial marks for die-dicing package
JP4168331B2 (ja) * 2003-02-21 2008-10-22 ソニー株式会社 半導体装置及びその製造方法
JP3804649B2 (ja) 2003-09-19 2006-08-02 株式会社村田製作所 電子回路装置の製造方法および電子回路装置

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