JP2008124256A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2008124256A JP2008124256A JP2006306677A JP2006306677A JP2008124256A JP 2008124256 A JP2008124256 A JP 2008124256A JP 2006306677 A JP2006306677 A JP 2006306677A JP 2006306677 A JP2006306677 A JP 2006306677A JP 2008124256 A JP2008124256 A JP 2008124256A
- Authority
- JP
- Japan
- Prior art keywords
- memory chip
- bonding
- chip
- electrodes
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
【解決手段】配線基板7上に搭載された制御用チップ5上に積層されるメモリチップ1及びメモリチップ2と、メモリチップ3及びメモリチップ4とがそれぞれ接続されるボンディング電極7cのボンディング電極列に応じて90°方向を変えて積層され、かつ交互に積層されていることにより、同一方向の上下のワイヤ間で、間に介在するチップ厚の分ワイヤクリアランスを大きくとることができる。その結果、上下のワイヤ間で十分なワイヤクリアランスを確保することができる。
【選択図】図3
Description
図1は本発明の実施の形態の半導体装置の構造の一例を樹脂体を透過して示す平面図、図2は図1に示すA−A線に沿って切断した構造の一例を示す断面図、図3は図1に示すB−B線に沿って切断した構造の一例を示す断面図である。また、図4は本発明の実施の形態の変形例の半導体装置の構造を樹脂体を透過して示す平面図、図5は図4に示すA−A線に沿って切断した構造を示す断面図、図6は図4に示すB−B線に沿って切断した構造を示す断面図、図7は本発明の実施の形態の他の変形例の半導体装置の構造を樹脂体を透過して示す平面図である。さらに、図8は比較例の半導体装置の構造を樹脂体を透過して示す平面図、図9は図8に示すA−A線に沿って切断した構造を示す断面図、図10は図8に示すB−B線に沿って切断した構造を示す断面図、図11は他の比較例の半導体装置の構造を樹脂体を透過して示す平面図である。
1a 主面(表面)
1b 裏面
1c 電極パッド
2 メモリチップ(第1メモリチップ)
2a 主面(表面)
2b 裏面
2c 電極パッド
3 メモリチップ(第2メモリチップ)
3a 主面(表面)
3b 裏面
3c 電極パッド
4 メモリチップ(第2メモリチップ)
4a 主面(表面)
4b 裏面
4c 電極パッド
5 制御用チップ
5a 主面(表面)
5b 裏面
5c 電極パッド
5d メモリインターフェイス用電極列
6 半田ボール(外部端子)
7 配線基板
7a 主面
7b 裏面
7c ボンディング電極
7d 第1のボンディング電極列
7e 第2のボンディング電極列
7f 内部配線
7g 内部配線
8 ワイヤ
9 樹脂体
10 SIP(半導体装置)
11 金バンプ
12 アンダーフィル材
13 SIP(半導体装置)
14 SIP(半導体装置)
15 基板中心
16 チップ中心
20 SIP
30 SIP
Claims (5)
- 複数の半導体チップを有する半導体装置であって、
主面とこれに対向する裏面を有し、前記主面上に複数のボンディング電極が設けられた配線基板と、
前記配線基板の主面上に搭載され、表面に複数の電極が設けられた制御用チップと、
前記制御用チップ上に積層され、それぞれの表面に複数の電極が設けられた複数のメモリチップと、
前記配線基板のボンディング電極と前記制御用チップの電極とを、及び前記配線基板のボンディング電極と前記メモリチップの電極とを電気的に接続する複数のワイヤと、
前記配線基板の裏面に設けられた複数の外部端子とを有し、
前記配線基板の複数のボンディング電極は、前記配線基板の主面の交差する2つの辺の何れか一方と他方に沿って並ぶ第1のボンディング電極列と第2のボンディング電極列を形成し、
前記複数のメモリチップは、前記第1のボンディング電極列のボンディング電極に前記ワイヤを介して接続する第1メモリチップと、前記第2のボンディング電極列のボンディング電極に前記ワイヤを介して接続する第2メモリチップとを含み、前記第1メモリチップと前記第2メモリチップとがそれぞれ接続されるボンディング電極のボンディング電極列に応じて方向を変えて積層され、かつ交互に積層されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記第1メモリチップと前記第2メモリチップは、平面方向に沿って90°向きを変えて積層されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1メモリチップ及び前記第2メモリチップがそれぞれ2つずつ搭載され、それぞれが交互に積層されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記制御用チップの電極のうち、前記配線基板の前記第1のボンディング電極列のボンディング電極に接続される電極の列は、前記第1のボンディング電極列に沿って並び、かつ前記第2のボンディング電極列のボンディング電極に接続される電極の列は、前記第2のボンディング電極列に沿って並んでいることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記制御用チップ及び前記複数のメモリチップの中心が、前記配線基板の平面方向に対して同一の角部に向かって偏心して配置されていることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006306677A JP5096730B2 (ja) | 2006-11-13 | 2006-11-13 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006306677A JP5096730B2 (ja) | 2006-11-13 | 2006-11-13 | 半導体装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2008124256A true JP2008124256A (ja) | 2008-05-29 |
JP2008124256A5 JP2008124256A5 (ja) | 2009-12-24 |
JP5096730B2 JP5096730B2 (ja) | 2012-12-12 |
Family
ID=39508687
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006306677A Expired - Fee Related JP5096730B2 (ja) | 2006-11-13 | 2006-11-13 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5096730B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9583452B2 (en) | 2013-03-13 | 2017-02-28 | Apple Inc. | Systems and methods for high-speed, low-profile memory packages and pinout designs |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000156464A (ja) * | 1998-11-20 | 2000-06-06 | Hitachi Ltd | 半導体装置の製造方法 |
JP2002217356A (ja) * | 2001-01-19 | 2002-08-02 | Nec Corp | 半導体装置及びその製造方法 |
JP2004063579A (ja) * | 2002-07-25 | 2004-02-26 | Renesas Technology Corp | 積層型半導体装置 |
JP2006156909A (ja) * | 2004-12-01 | 2006-06-15 | Renesas Technology Corp | マルチチップモジュール |
-
2006
- 2006-11-13 JP JP2006306677A patent/JP5096730B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000156464A (ja) * | 1998-11-20 | 2000-06-06 | Hitachi Ltd | 半導体装置の製造方法 |
JP2002217356A (ja) * | 2001-01-19 | 2002-08-02 | Nec Corp | 半導体装置及びその製造方法 |
JP2004063579A (ja) * | 2002-07-25 | 2004-02-26 | Renesas Technology Corp | 積層型半導体装置 |
JP2006156909A (ja) * | 2004-12-01 | 2006-06-15 | Renesas Technology Corp | マルチチップモジュール |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9583452B2 (en) | 2013-03-13 | 2017-02-28 | Apple Inc. | Systems and methods for high-speed, low-profile memory packages and pinout designs |
KR101774415B1 (ko) * | 2013-03-13 | 2017-09-04 | 애플 인크. | 적층형 메모리 패키지, 그의 제조 방법, 및 ic 패키지 기판의 핀아웃 설계 |
US9853016B2 (en) | 2013-03-13 | 2017-12-26 | Apple Inc. | Systems and methods for high-speed, low-profile memory packages and pinout designs |
Also Published As
Publication number | Publication date |
---|---|
JP5096730B2 (ja) | 2012-12-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4751351B2 (ja) | 半導体装置とそれを用いた半導体モジュール | |
US9093291B2 (en) | Flip-chip, face-up and face-down wirebond combination package | |
KR102005830B1 (ko) | 플립-칩, 페이스-업 및 페이스-다운 센터본드 메모리 와이어본드 어셈블리 | |
US7598617B2 (en) | Stack package utilizing through vias and re-distribution lines | |
US8866284B2 (en) | Semiconductor device comprising an extended semiconductor chip having an extension | |
US8873245B2 (en) | Embedded chip-on-chip package and package-on-package comprising same | |
JP2005175423A (ja) | 半導体パッケージ | |
KR20040014156A (ko) | 반도체장치 | |
WO2011086613A1 (ja) | 半導体装置及びその製造方法 | |
US20140246781A1 (en) | Semiconductor device, method of forming a packaged chip device and chip package | |
US20110115100A1 (en) | Semiconductor device | |
US20100237491A1 (en) | Semiconductor package with reduced internal stress | |
JP2005260053A (ja) | 半導体装置及び半導体装置の製造方法 | |
JP4538830B2 (ja) | 半導体装置 | |
US9219050B2 (en) | Microelectronic unit and package with positional reversal | |
US20120205797A1 (en) | Bump and semiconductor device having the same | |
JP5096730B2 (ja) | 半導体装置 | |
US20070170571A1 (en) | Low profile semiconductor system having a partial-cavity substrate | |
CN115241171A (zh) | 具有双层封装结构的Micro-LED微显示芯片 | |
US8441129B2 (en) | Semiconductor device | |
JP2005197538A (ja) | 半導体装置 | |
JP2014027145A (ja) | 半導体装置 | |
KR101169688B1 (ko) | 반도체 장치 및 적층 반도체 패키지 | |
JP4657581B2 (ja) | 半導体装置 | |
KR20110016028A (ko) | 적층 반도체 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091105 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20091105 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20100528 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110824 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110830 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111026 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120605 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120803 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120828 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120921 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150928 Year of fee payment: 3 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |