JP2008067411A5 - - Google Patents
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- Publication number
- JP2008067411A5 JP2008067411A5 JP2007293520A JP2007293520A JP2008067411A5 JP 2008067411 A5 JP2008067411 A5 JP 2008067411A5 JP 2007293520 A JP2007293520 A JP 2007293520A JP 2007293520 A JP2007293520 A JP 2007293520A JP 2008067411 A5 JP2008067411 A5 JP 2008067411A5
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- channel mos
- mos transistor
- supply potential
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007293520A JP4603030B2 (ja) | 2007-11-12 | 2007-11-12 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007293520A JP4603030B2 (ja) | 2007-11-12 | 2007-11-12 | 半導体装置 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34526198A Division JP4063982B2 (ja) | 1998-12-04 | 1998-12-04 | レベルシフタ回路およびそれを用いた半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008067411A JP2008067411A (ja) | 2008-03-21 |
| JP2008067411A5 true JP2008067411A5 (enExample) | 2008-05-01 |
| JP4603030B2 JP4603030B2 (ja) | 2010-12-22 |
Family
ID=39289619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007293520A Expired - Fee Related JP4603030B2 (ja) | 2007-11-12 | 2007-11-12 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4603030B2 (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8487658B2 (en) * | 2011-07-12 | 2013-07-16 | Qualcomm Incorporated | Compact and robust level shifter layout design |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09153551A (ja) * | 1995-11-30 | 1997-06-10 | Seiko Epson Corp | 半導体装置 |
| JP3369382B2 (ja) * | 1995-12-11 | 2003-01-20 | 東芝マイクロエレクトロニクス株式会社 | 半導体装置 |
| JPH1084274A (ja) * | 1996-09-09 | 1998-03-31 | Matsushita Electric Ind Co Ltd | 半導体論理回路および回路レイアウト構造 |
-
2007
- 2007-11-12 JP JP2007293520A patent/JP4603030B2/ja not_active Expired - Fee Related
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