JP2008041811A - Wiring circuit board, multiple-chip wiring circuit board, and method for manufacturing the wiring board - Google Patents

Wiring circuit board, multiple-chip wiring circuit board, and method for manufacturing the wiring board Download PDF

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JP2008041811A
JP2008041811A JP2006211978A JP2006211978A JP2008041811A JP 2008041811 A JP2008041811 A JP 2008041811A JP 2006211978 A JP2006211978 A JP 2006211978A JP 2006211978 A JP2006211978 A JP 2006211978A JP 2008041811 A JP2008041811 A JP 2008041811A
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layer
wiring board
cavity
wiring
conductor
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Makoto Nagai
誠 永井
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring circuit board including a conductor for surely and rigidly mounting electronic components and an element such as a light emitting element, and also to provide a multiple-chip wiring circuit board and a method for manufacturing the wiring circuit board. <P>SOLUTION: The wiring circuit board 1a is provided with a substrate body 2 having a front surface 3 and a rear surface 4 formed of ceramic (insulating material) layers s1 to s3, and a conductor 10 formed at the bottom surface 6 of a cavity 5 opening to the front surface 3 of the substrate body 2, including an Au-Sn alloy layer 14 in a thickness of 2 μm or larger at the front surface thereof. This conductor 10 partly includes an element mounting part a. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、基板本体の表面またはキャビティの底面に電子部品や発光素子などの素子を搭載するための導体部を有する配線基板および多数個取り配線基板ならびに上記配線基板の製造方法に関する。   The present invention relates to a wiring board having a conductor portion for mounting an element such as an electronic component or a light emitting element on the surface of a substrate body or the bottom surface of a cavity, a multi-piece wiring board, and a method for manufacturing the wiring board.

セラミックからなる基体の上面の中央に半田を介して発光素子を搭載する搭載部を形成し、上記基体の上面の外周部に前記搭載部を囲み且つ内周面が上側に向かって広がるように傾斜した枠体を設け、上記ハンダは、Au−Sn合金からなり、その外周端を搭載する発光素子の側面の下端よりも外側に全周にわたって延出させた発光素子収納用パッケージが提案されている(例えば、特許文献1参照)。
上記発光素子収納用パッケージによれば、上記ハンダによる発光素子の光に対する反射率が40%以上であるため、かかる発光素子の側面の下端に影(暗部)を発生させず、高輝度の発光装置を作成することが可能となる。
A mounting portion for mounting a light emitting element is formed at the center of the upper surface of the base made of ceramic via solder, and is inclined so that the outer peripheral portion of the upper surface of the base surrounds the mounting portion and the inner peripheral surface extends upward. There has been proposed a light emitting element storage package in which the frame is provided, and the solder is made of an Au-Sn alloy, and the outer peripheral end of the solder extends outside the lower end of the side surface of the light emitting element. (For example, refer to Patent Document 1).
According to the light emitting element storage package, since the reflectance of the light emitting element by the solder is 40% or more, a light emitting device with high brightness does not generate a shadow (dark part) at the lower end of the side surface of the light emitting element. Can be created.

特開2004−319598号公報(第1〜6頁、図1)JP 2004-319598 A (pages 1 to 6, FIG. 1)

ところで、発光素子を搭載するためのAu−Sn合金からなる前記ハンダは、Wなどからなるメタライズ層の表面上に載置すべく、予めプリフォームされたシートからなるため、搭載時の工数が増え且つ煩雑になる、という問題があった。
一方、発光素子の底面に予め装着されたプリフォームシートのハンダの厚みは、これまで2μm以下であった。このように、ハンダの厚みが2μm以下であると、セラミックからなる前記基体の反り、もしくは、メタライズ層の表面またはAgメッキ層の表面が粗いことに起因する凹凸形状を吸収しにくくなる。このため、かかるハンダと共に発光素子を搭載して加熱(リフロー)した際に、当該発光素子の底面に装着されていた上記Au−Sn合金からなるハンダとAgメッキ層の表面との間や、上記ハンダの内部に気泡や気孔が生じる。その結果、かかる発光素子と搭載部との密着強度が低下すると共に、かかる発光素子と搭載部との間における伝熱性が低下し、導通も不安定になり易くなる、という問題があった。
By the way, the solder made of an Au—Sn alloy for mounting a light emitting element is made of a pre-formed sheet so as to be placed on the surface of a metallized layer made of W or the like. In addition, there is a problem that it becomes complicated.
On the other hand, the solder thickness of the preform sheet previously mounted on the bottom surface of the light emitting element has been 2 μm or less. Thus, when the thickness of the solder is 2 μm or less, it becomes difficult to absorb the warp of the substrate made of ceramic, or the uneven shape resulting from the rough surface of the metallized layer or the surface of the Ag plating layer. For this reason, when a light emitting element is mounted with such solder and heated (reflowed), between the solder made of the Au—Sn alloy attached to the bottom surface of the light emitting element and the surface of the Ag plating layer, or Bubbles and pores are generated inside the solder. As a result, there is a problem in that the adhesion strength between the light emitting element and the mounting portion is lowered, the heat transfer property between the light emitting element and the mounting portion is lowered, and conduction is likely to be unstable.

本発明は、背景技術において説明した問題点を解決し、電子部品や発光素子などの素子を強固で確実に搭載できる導体部を有する配線基板および多数個取り配線基板ならびに上記配線基板の製造方法を提供する、ことを課題とする。   The present invention solves the problems described in the background art, and provides a wiring board having a conductor portion that can securely and securely mount elements such as electronic components and light emitting elements, a multi-piece wiring board, and a method of manufacturing the wiring board. The issue is to provide.

課題を解決するための手段および発明の効果Means for Solving the Problems and Effects of the Invention

本発明は、前記課題を解決するため、素子を搭載部に密着させるためのAg−Sn合金層の厚みを適正化することによって得られたものである。
即ち、本発明の配線基板(請求項1)は、絶縁材からなり、表面および裏面を有する基板本体と、かかる基板本体の表面に形成され、表層に厚みが2μm超のAu−Sn合金層を有する導体部と、を備え、前記導体部は、素子搭載部であるか、かかる素子搭載部を一部に含む、ことを特徴とする。
上記Au−Sn合金層の厚みの上限値は、15μmである。
The present invention has been obtained by optimizing the thickness of an Ag-Sn alloy layer for bringing an element into close contact with a mounting portion in order to solve the above-described problems.
That is, the wiring board of the present invention (Claim 1) is made of an insulating material, and has a substrate body having a front surface and a back surface, and an Au—Sn alloy layer having a thickness of more than 2 μm formed on the surface of the substrate body. A conductor portion, and the conductor portion is an element mounting portion or includes the element mounting portion in part.
The upper limit of the thickness of the Au—Sn alloy layer is 15 μm.

これによれば、基板本体の表面に、表層に厚みが2μm超のAu−Sn合金層(ハンダ)を有する導体部が形成されているため、かかるAu−Sn層上の素子搭載部に発光素子や電子部品などの素子を搭載して加熱(リフロー)しても、かかる素子などの底面と上記Au−Sn合金層との間やかかるAu−Sn合金層の内部に気泡や気孔が生じにくくなる。従って、別途にプリフォームされたハンダを用意することなく、素子を導体部の搭載部上に搭載でき、かかる素子と搭載部との密着強度が向上し、且つ素子から導体部への熱伝達性が向上すると共に、かかる素子と導通部との導通も安定させることが可能となる。   According to this, since a conductor portion having an Au—Sn alloy layer (solder) having a thickness of more than 2 μm is formed on the surface of the substrate body, a light emitting element is formed on the element mounting portion on the Au—Sn layer. Even when an element such as an electronic component is mounted and heated (reflowed), bubbles or pores are less likely to be generated between the bottom surface of the element and the Au-Sn alloy layer or in the Au-Sn alloy layer. . Therefore, the element can be mounted on the mounting portion of the conductor portion without preparing separately preformed solder, the adhesion strength between the element and the mounting portion is improved, and heat transfer from the element to the conductor portion is improved. In addition, the conduction between the element and the conduction portion can be stabilized.

尚、前記絶縁材には、アルミナなどの高温焼成セラミック、ガラス−セラミックなどの低温焼成セラミック、あるいは、エポキシ系などの樹脂が含まれる。
また、基板本体の表面は、かかる表面に開口するキャビティの底面も含む。
更に、前記Au−Sn合金層の望ましい厚みは、5〜10μmの範囲である。
また、前記Au−Sn合金層は、かかる合金のメッキ層からなる。
更に、前記導体部は、例えば、W、Mo、Cuからなるメタライズ層、その表面に形成したNiメッキ層、その表面に形成したAuメッキ層、およびその表面に形成した前記Au−Sn合金層からなるものである。
また、前記導体部が素子搭載部を一部に含む形態とは、例えば、平面視で、発光素子を一部に搭載する素子搭載部と、かかる搭載部を除いた導体部の表面が発光素子からの光を反射する反射面とからなる。
The insulating material includes a high-temperature fired ceramic such as alumina, a low-temperature fired ceramic such as glass-ceramic, or an epoxy resin.
The surface of the substrate body also includes a bottom surface of a cavity that opens to the surface.
Furthermore, the desirable thickness of the Au—Sn alloy layer is in the range of 5 to 10 μm.
The Au—Sn alloy layer is made of a plated layer of such an alloy.
Further, the conductor portion is made of, for example, a metallized layer made of W, Mo, Cu, a Ni plated layer formed on the surface, an Au plated layer formed on the surface, and the Au—Sn alloy layer formed on the surface. It will be.
The form in which the conductor part includes the element mounting part is, for example, an element mounting part in which the light emitting element is partially mounted in plan view, and the surface of the conductor part excluding the mounting part is the light emitting element. And a reflecting surface that reflects light from the surface.

また、本発明には、前記基板本体の表面は、かかる表面に開口するキャビティの底面であると共に、前記導体部は、上記キャビティの底面に形成され、一部に素子搭載部を含む、配線基板(請求項2)も含まれる。
これによれば、キャビティの底面に、表層に厚みが2μm超のAu−Sn合金層を有する導体部が形成されているため、かかるAu−Sn合金層上の素子搭載部に発光素子や電子部品などを搭載して加熱(リフロー)しても、かかる素子の底面と上記Au−Sn合金層との間やかかるAu−Sn合金層の内部に気泡や気孔が生じにくくなる。従って、別途にハンダを用意する必要がなく、搭載する素子と搭載部との密着強度が向上し、且つかかる素子から導体部への熱伝達性が向上すると共に、素子と導体部との導通も安定させることが可能となる。
尚、上記キャビティには、平面視が円形の底面で且つほぼ円錐形状の側面、平面視が長円形の底面で且つ側面がほぼ長円錐形の側面、あるいは、平面視が楕円形の底面で且つほぼ楕円錐形状の側面からなる形態などが含まれる。
According to the present invention, the surface of the substrate body is a bottom surface of a cavity that opens to the surface, and the conductor portion is formed on the bottom surface of the cavity, and partly includes an element mounting portion. (Claim 2) is also included.
According to this, since the conductor portion having the Au—Sn alloy layer having a thickness of more than 2 μm is formed on the bottom surface of the cavity, the light emitting element and the electronic component are formed on the element mounting portion on the Au—Sn alloy layer. Even if it is mounted and heated (reflowed), bubbles and pores are hardly generated between the bottom surface of the element and the Au—Sn alloy layer or inside the Au—Sn alloy layer. Accordingly, it is not necessary to prepare a separate solder, the adhesion strength between the mounted element and the mounting portion is improved, the heat transfer from the element to the conductor portion is improved, and the conduction between the element and the conductor portion is also improved. It becomes possible to stabilize.
The cavity has a circular bottom surface and a substantially conical side surface in plan view, an elliptical bottom surface and a substantially conical side surface in plan view, or an elliptical bottom surface in plan view. The form which consists of a side surface of a substantially elliptical cone shape is included.

更に、本発明には、前記配線基板を縦横に複数個配列した製品領域と、かかる製品領域の周囲に位置し、前記絶縁材からなる耳部と、を備えている、多数個取り配線基板(請求項3)も含まれる。
これによれば、素子搭載部を含む前記導体部を表面またはキャビティの底面に設けた複数の配線基板を、縦横の平面方向に沿って併有した多数個取り配線基板であるため、隣接する配線基板の間および配線基板と耳部との間を区画する切断予定面に沿って切断加工することで、多数の配線基板を効率良く提供可能となる。尚、前記耳部は、製品領域の周囲の一辺または二辺にのみ隣接する形態も含まれる。
Furthermore, in the present invention, a multi-piece wiring board comprising a product region in which a plurality of wiring boards are arranged vertically and horizontally, and an ear portion made of the insulating material located around the product region ( Claim 3) is also included.
According to this, since it is a multi-piece wiring substrate having a plurality of wiring substrates provided with the conductor portion including the element mounting portion on the surface or the bottom surface of the cavity along the vertical and horizontal plane directions, adjacent wiring A large number of wiring boards can be efficiently provided by performing a cutting process along the planned cutting surfaces that divide between the boards and between the wiring boards and the ears. In addition, the form which the said ear | edge part adjoins only to the one side or two sides around a product area | region is also contained.

一方、本発明による配線基板の製造方法(請求項4)は、絶縁材からなり、表面および裏面を有する基板本体を形成する工程と、かかる基板本体の表面に、メタライズ層を形成する工程と、かかるメタライズ層に電解メッキを施して、厚みが2μm超のAu−Sn合金層を形成する工程と、を含む、ことを特徴とする。
これによれば、搭載する素子との密着性が高い素子搭載部を含む前記導体部を表面またはキャビティの底面に設けた前記配線基板を、確実に製造することが可能となる。尚、上記各工程により前記多数個取り基板を作成した後、個々の配線基板に分割する製造方法としても良い。
On the other hand, a method for manufacturing a wiring board according to the present invention (Claim 4) includes a step of forming a substrate body made of an insulating material and having a front surface and a back surface, a step of forming a metallized layer on the surface of the substrate body, And applying a metal plating layer to the metallized layer to form an Au—Sn alloy layer having a thickness of more than 2 μm.
According to this, it is possible to reliably manufacture the wiring board in which the conductor part including the element mounting part having high adhesion with the element to be mounted is provided on the surface or the bottom surface of the cavity. In addition, it is good also as a manufacturing method which divides | segments into each wiring board, after producing the said multi-piece substrate by said each process.

以下において、本発明を実施するための最良の形態について説明する。
図1は、本発明による発光素子を搭載するための配線基板1aを示す平面図、図2は、図1中のX−X線の矢視に沿った垂直断面図、図3は、図2中の一点鎖線部分Yの部分拡大図である。
配線基板1aは、図1,図2に示すように、平面視がほぼ正方形で表面3および裏面4を有する基板本体2と、かかる基板本体2の表面3に開口し、平面視が円形の底面6およびかかる底面6から表面3に向かってほぼ円錐形状に広がる側面7を有するキャビティ5と、かかるキャビティ5の底面6に形成されたパッド15と、当該パッド15付近を除くキャビティ5の底面6に形成された平面視がほぼ半円形の導体部10aと、を備えている。尚、キャビティ5の側面7の仰角は、例えば、約30度から70度の範囲である。
In the following, the best mode for carrying out the present invention will be described.
FIG. 1 is a plan view showing a wiring board 1a for mounting a light emitting device according to the present invention, FIG. 2 is a vertical sectional view taken along line XX in FIG. 1, and FIG. It is the elements on larger scale of the dashed-dotted line part Y in the inside.
As shown in FIGS. 1 and 2, the wiring board 1a has a substrate body 2 having a substantially square shape in plan view and having a front surface 3 and a back surface 4, and an opening in the front surface 3 of the substrate body 2. The bottom surface has a circular shape in plan view. 6 and a cavity 5 having a side surface 7 extending in a substantially conical shape from the bottom surface 6 toward the surface 3, a pad 15 formed on the bottom surface 6 of the cavity 5, and a bottom surface 6 of the cavity 5 excluding the vicinity of the pad 15. The formed plan view includes a substantially semicircular conductor portion 10a. The elevation angle of the side surface 7 of the cavity 5 is, for example, in the range of about 30 degrees to 70 degrees.

基板本体2は、図2に示すように、例えばアルミナ(セラミック:絶縁材)または低温焼成セラミックの一種であるガラス−セラミックからなるセラミック層s1〜s3を一体に積層した絶縁材からなり、例えば、約5×5×1mmのサイズである。
また、導体部10aは、図3に示すように、メタライズ層11の表面に、上記同様の厚みのNiメッキ層12およびAuメッキ層13を介して、表層に厚みが2超〜15μmのAu−Sn合金層(ハンダ)14を電解メッキで形成したものである。上記メタライズ層11は、厚みが数10μmのW、Mo、またはCuからなり、Niメッキ層12の厚みは約2〜15μm、Auメッキ層13の厚みは約0.5〜4μmである。尚、上記Au−Sn合金は、例えば、80wt%Au−20wt%Snの組成である。
As shown in FIG. 2, the substrate body 2 is made of an insulating material in which ceramic layers s1 to s3 made of glass-ceramic, which is a kind of alumina (ceramic: insulating material) or a low-temperature fired ceramic, are integrally laminated. The size is about 5 × 5 × 1 mm.
Further, as shown in FIG. 3, the conductor portion 10a is formed on the surface of the metallized layer 11 with a Ni plating layer 12 and an Au plating layer 13 having the same thickness as described above, and an Au- A Sn alloy layer (solder) 14 is formed by electrolytic plating. The metallized layer 11 is made of W, Mo or Cu having a thickness of several tens of μm, the Ni plating layer 12 has a thickness of about 2 to 15 μm, and the Au plating layer 13 has a thickness of about 0.5 to 4 μm. The Au—Sn alloy has a composition of, for example, 80 wt% Au-20 wt% Sn.

上記導体部10aにおけるキャビティ5の底面6の中央付近には、図1,図2中の一点鎖線で示す発光ダイオード(発光素子:以下、単にLEDという)9を、搭載する平面視が矩形の素子搭載部aが位置している。かかるLED9の素子搭載部aを除いた導体部10aのうち、上記Au−Sn合金層14が露出する部分は、当該LED9が発光する光を反射して、外部に放射する光反射面を形成している。
一方、パッド15は、図3に示すように、キャビティ5の底面6に形成された前記同様の厚みのメタライズ層16の表面に、前記同様の厚みのNiメッキ層17を介して表層に前記同様のAuメッキ層18を形成したものである。
更に、キャビティ5の側面7には、前記同様の厚みのメタライズ層、Niメッキ層、Auメッキ層、およびAgメッキ層からなる光反射層8が形成されている。
In the vicinity of the center of the bottom surface 6 of the cavity 5 in the conductor portion 10a, a light emitting diode (light emitting element: hereinafter simply referred to as LED) 9 indicated by a one-dot chain line in FIGS. The mounting part a is located. Of the conductor portion 10a excluding the element mounting portion a of the LED 9, the portion where the Au—Sn alloy layer 14 is exposed forms a light reflecting surface that reflects the light emitted by the LED 9 and emits it to the outside. ing.
On the other hand, as shown in FIG. 3, the pad 15 is formed on the surface of the metallized layer 16 having the same thickness formed on the bottom surface 6 of the cavity 5 as described above on the surface layer through the Ni plating layer 17 having the same thickness. The Au plating layer 18 is formed.
Further, on the side surface 7 of the cavity 5, a light reflecting layer 8 made of a metallized layer, a Ni plated layer, an Au plated layer, and an Ag plated layer having the same thickness as described above is formed.

図2に示すように、セラミック層s2,s3間には、Wなどからなり所定パターンを有する複数の配線層20が形成され、基板本体2の裏面4には、Wなどからなる複数の接続端子19が形成されている。前記導体部10aおよびパッド15は、セラミック層s2,s3を貫通するビア導体vを介して、それぞれ何れかの配線層20および接続端子19と導通可能とされている。尚、接続端子19は、本配線基板1aを実装する図示しないマザーボードとの導通に用いられる。
導体部10aの上に前記Au−Sn合金層14を介し且つ導通可能に搭載されるLED9は、図2中の破線で示すワイヤwを介して、パッド15とボンディングされる。即ち、導体部10aおよびパッド15は、LED9が本配線基板1aと導通するための電極でもある。
尚、LED9は、上記ボンディング用のワイヤwを介して、導体部10aの表面にも接続する形態としても良い。上記LED9が搭載され且つワイヤwがボンディング(接続)された後で、キャビティ5内には、固化前の封止樹脂(図示せず)が充填され、基板本体2の表面3とほぼ同じレベルにして固化される。
As shown in FIG. 2, a plurality of wiring layers 20 made of W or the like and having a predetermined pattern are formed between the ceramic layers s2 and s3, and a plurality of connection terminals made of W or the like are formed on the back surface 4 of the substrate body 2. 19 is formed. The conductor portion 10a and the pad 15 can be electrically connected to any one of the wiring layers 20 and the connection terminals 19 through via conductors v penetrating the ceramic layers s2 and s3. The connection terminal 19 is used for conduction with a mother board (not shown) on which the wiring board 1a is mounted.
The LED 9 mounted on the conductor portion 10a through the Au-Sn alloy layer 14 so as to be conductive is bonded to the pad 15 through a wire w indicated by a broken line in FIG. That is, the conductor part 10a and the pad 15 are also electrodes for the LED 9 to be electrically connected to the wiring board 1a.
The LED 9 may be connected to the surface of the conductor portion 10a via the bonding wire w. After the LED 9 is mounted and the wire w is bonded (connected), the cavity 5 is filled with a sealing resin (not shown) before solidification, and the level is almost the same as the surface 3 of the substrate body 2. Solidified.

図4は、異なる形態の配線基板1bを示す前記図1と同様な平面図である。
配線基板1bは、図4に示すように、前記配線基板1aと同様の基板本体2、キャビティ5、および光反射層8などを有している。
かかる配線基板1bが前記配線基板1aと相違する点は、キャビティ5の底面に左右一対のパッド15a,15bが形成され、これらの間に平面視がほぼ長円形である導体部10bが底面6の中心部を通過するように形成されている。かかる導体部10bも、前記導体部10aと同様なメタライズ層11、Niメッキ層12、Auメッキ層13、および厚みが2μm超〜15μmのAu−Sn合金層14を有している。
上記導体部10bの中央付近の素子搭載部aに搭載されるLED9とパッド15a,15bとの間は、個別に前記ワイヤwによりボンディングされる。このため、導体部10bは、LED9とは直に導通されていない。
FIG. 4 is a plan view similar to FIG. 1, showing a different form of the wiring board 1b.
As shown in FIG. 4, the wiring board 1b includes a substrate body 2, a cavity 5, and a light reflecting layer 8 similar to the wiring board 1a.
The wiring board 1b is different from the wiring board 1a in that a pair of left and right pads 15a and 15b are formed on the bottom surface of the cavity 5, and a conductor portion 10b having a substantially oval shape in plan view is formed between them. It is formed so as to pass through the center. The conductor portion 10b also has the same metallized layer 11, Ni plating layer 12, Au plating layer 13, and Au—Sn alloy layer 14 having a thickness of more than 2 μm to 15 μm as the conductor portion 10a.
The LED 9 mounted on the element mounting portion a near the center of the conductor portion 10b and the pads 15a and 15b are individually bonded by the wire w. For this reason, the conductor portion 10b is not directly conducted to the LED 9.

図5は、前記配線基板1aの応用形態である配線基板1cを示す平面図である。かかる配線基板1cも、図5に示すように、基板本体2、キャビティ5、および導体部10aなどとを備えている。かかる配線基板1cが前記配線基板1aと相違する点は、キャビティ5の側面7に前記光反射層8がなく、アルミナ系の白色を呈する側面7自体が光反射面となって露出している。
また、図6は、前記配線基板1bの応用形態である配線基板1dを示す平面図である。かかる配線基板1dも、図6に示すように、基板本体2、キャビティ5、および導体部10bなどとを備えている。かかる配線基板1dが前記配線基板1bと相違する点も、キャビティ5の側面7に前記光反射層8がなく、アルミナ系の白色を呈する側面7自体が光反射面となって露出している。
以上のような配線基板1b,1c,1dによれば、厚みが2μm超〜15μmのAu−Sn合金層14を有する導体部10a,10bが形成されているため、かかるハンダ層14上の素子搭載部aにLED9を搭載して加熱しても、当該LED9の底面と上記ハンダ14との間やハンダ14中に気泡や気孔が生じにくくなる。従って、別途にハンダを用意する必要がなく、LED9と素子搭載部aとの密着強度を向上させ、導体部10a,10bへの抜熱も容易にすることができる。
FIG. 5 is a plan view showing a wiring board 1c which is an applied form of the wiring board 1a. As shown in FIG. 5, the wiring board 1c also includes a board body 2, a cavity 5, a conductor portion 10a, and the like. The wiring board 1c is different from the wiring board 1a in that the light reflecting layer 8 is not provided on the side surface 7 of the cavity 5, and the alumina-based white side surface 7 itself is exposed as a light reflecting surface.
FIG. 6 is a plan view showing a wiring board 1d which is an applied form of the wiring board 1b. As shown in FIG. 6, the wiring board 1d also includes a board body 2, a cavity 5, a conductor portion 10b, and the like. The wiring board 1d is different from the wiring board 1b in that the light reflecting layer 8 is not provided on the side surface 7 of the cavity 5, and the alumina-based white side surface 7 itself is exposed as a light reflecting surface.
According to the wiring boards 1b, 1c, and 1d as described above, since the conductor portions 10a and 10b having the Au—Sn alloy layer 14 with a thickness of more than 2 μm to 15 μm are formed, the element mounting on the solder layer 14 is performed. Even if the LED 9 is mounted on the part a and heated, bubbles or pores are hardly generated between the bottom surface of the LED 9 and the solder 14 or in the solder 14. Accordingly, it is not necessary to prepare a separate solder, the adhesion strength between the LED 9 and the element mounting portion a can be improved, and heat removal to the conductor portions 10a and 10b can be facilitated.

前記配線基板1a,1bは、以下のようにして製造した。
予め、アルミナを主成分とする平面視がほぼ長方形である3層の大版用グリーンシートを用意した。そのうちの1層の大版用グリーンシートに対し、所定のクリアランスを有するパンチとダイの受入孔とによる打ち抜き加工を、複数の箇所に対して行うことで、当該グリーンシートの表面と裏面との厚み方向に沿って、全体がほぼ円錐形の貫通孔を縦横方向に沿って複数個形成した。
また、残り2層の大版用グリーンシートに対し、クリアランスが最少のパンチとダイの受入孔とによる打ち抜き加工を、複数の箇所に対して行うことで、複数のビアホールを形成し、且つ各ビアボールごとにWまたはMo粉末粒子を含む導電性ペーストを充填して、ビア導体vを各箇所ごとに形成した。
The wiring boards 1a and 1b were manufactured as follows.
In advance, a three-layer green plate for large plates having alumina as a main component and having a substantially rectangular plan view was prepared. The thickness of the front surface and the back surface of the green sheet is obtained by punching a plurality of portions of the green sheet for a large plate with a punch having a predetermined clearance and a receiving hole of the die. A plurality of substantially conical through-holes were formed along the vertical and horizontal directions along the direction.
In addition, the remaining two layers of large green sheets are punched into a plurality of locations by punching with the smallest clearance punch and die receiving holes to form a plurality of via holes, and each via ball Each was filled with a conductive paste containing W or Mo powder particles, and a via conductor v was formed at each location.

更に、前記1層の大版用グリーンシートに形成したほぼ円錐形を呈する複数の貫通孔と、上記2層の大版用グリーンシートの表面および裏面の少なくとも一方における複数の箇所に対し、所定パターンに倣って、WまたはMo粉末粒子を含む導電性ペーストをスクリーン印刷して、前記メタライズ層11,16,配線層20,接続端子19を複数組ずつ形成した。この際、メタライズ層11,16,配線層20,および接続端子19は、それぞれビア導体vを介して接続された。
次に、前記ほぼ円錐形の貫通孔を複数個形成した大版用グリーンシートと、前記メタライズ層11,16や配線層20などが複数組形成された2層の大版用グリーンシートと、を積層・圧着して大版のグリーンシート積層体を形成し、かかる積層体を所定の温度帯に加熱して焼成した。
その結果、前記セラミック層s1〜s3なり、表面3に開口するキャビティ5と、その底面6にメタライズ層11,16とが形成された基板本体2が、縦横方向に沿って複数個配列して得られた。各キャビティ5の側面7には、前記メタライズに覆われていた。
Furthermore, a predetermined pattern is formed on a plurality of through-holes having a substantially conical shape formed in the one-layer large plate green sheet and a plurality of locations on at least one of the front and back surfaces of the two-layer large plate green sheet. Following this, a conductive paste containing W or Mo powder particles was screen-printed to form a plurality of sets of the metallized layers 11, 16, wiring layers 20, and connection terminals 19. At this time, the metallized layers 11, 16, the wiring layer 20, and the connection terminal 19 were connected via the via conductors v, respectively.
Next, a large plate green sheet in which a plurality of substantially conical through holes are formed, and a two-layer large plate green sheet in which a plurality of sets of the metallized layers 11, 16, wiring layers 20, and the like are formed, Lamination and pressure bonding were performed to form a large green sheet laminate, and this laminate was heated to a predetermined temperature zone and fired.
As a result, a plurality of substrate bodies 2 formed of the ceramic layers s1 to s3 and having the cavity 5 opened on the surface 3 and the metallized layers 11 and 16 formed on the bottom surface 6 are arranged in the vertical and horizontal directions. It was. The side surface 7 of each cavity 5 was covered with the metallization.

更に、各組ごとのメタライズ層11,16およびに対し、電解Niメッキおよび電解Auメッキをそれぞれ施し、更にメタライズ層11には、Au−Sn合金の電解メッキを施した。加えて、キャビティ5の側面7における前記メタライズに対し、電解Niメッキ、電解Auメッキ、および電解Agメッキを施した。
その結果、図7の平面図で示すように、配線基板1aを縦横に複数個配列した製品領域Aと、その周囲に位置し、前記セラミック層s1〜s3からなる耳部mと、を備えた多数個取り配線基板K1が得られた。
また、前記と同様な各工程を経ることで、図8の平面図で示すように、配線基板1bを縦横に複数個配列した製品領域Aと、その周囲に位置し、前記セラミック層s1〜s3からなる耳部mと、を備えた多数個取り配線基板K2が得られた。
尚、図7,図8中の破線は、配線基板1a,1a間または配線基板1b,1b間や、配線基板1a,1bと耳部mとを区画する仮想の切断予定面cを示す。
Further, electrolytic Ni plating and electrolytic Au plating were respectively applied to the metallized layers 11 and 16 of each group, and further, the metallized layer 11 was subjected to electrolytic plating of an Au—Sn alloy. In addition, the metallization on the side surface 7 of the cavity 5 was subjected to electrolytic Ni plating, electrolytic Au plating, and electrolytic Ag plating.
As a result, as shown in the plan view of FIG. 7, a product region A in which a plurality of wiring boards 1 a are arranged vertically and horizontally, and an ear m formed of the ceramic layers s <b> 1 to s <b> 3 are provided around the product region A. A multi-cavity wiring board K1 was obtained.
Further, through the same steps as described above, as shown in the plan view of FIG. 8, the ceramic regions s1 to s3 are located around the product region A in which a plurality of wiring boards 1b are arranged vertically and horizontally and the periphery thereof. Thus, a multi-cavity wiring board K2 provided with the ear part m is obtained.
The broken lines in FIGS. 7 and 8 indicate virtual cutting planes c that divide the wiring boards 1a and 1a, the wiring boards 1b and 1b, and the wiring boards 1a and 1b and the ear m.

図7,図8に示すように、個々の配線基板1a,1bにおけるキャビティ5の底面6には、メタライズ層11の表面にNiメッキ層12、Auメッキ層13、および厚みが5〜15μmのAu−Sn合金層14を被覆した導体部10a,10bと、メタライズ層16の表面にNiメッキ層17およびAuメッキ層18を被覆したパッド15,15a,15bと、が形成されると共に、キャビティ5の側面7には、光反射層8が形成されていた。
そして、多数個取り配線基板K1,K2を前記切断予定面cに沿ってカッタ(図示せず)などにより、厚み方向に切断加工することで、前記図1〜3,図4で示したように、複数個の配線基板1a,1bを得ることができた。
尚、配線基板1a,1bにおける導体部10a,10bの素子搭載部a上にLED9を搭載し、かかるLED9とパッド15,15a,15bとをボンディングワイヤwで接続した後で、キャビティ5内には、固化前の封止樹脂が基板本体2の表面3とほぼ同じレベルまで、充填され且つ固化される。
As shown in FIGS. 7 and 8, on the bottom surface 6 of the cavity 5 in each wiring substrate 1a, 1b, a Ni plating layer 12, an Au plating layer 13, and Au having a thickness of 5 to 15 μm are formed on the surface of the metallization layer 11. -The conductor portions 10a and 10b coated with the Sn alloy layer 14 and the pads 15, 15a and 15b coated with the Ni plating layer 17 and the Au plating layer 18 on the surface of the metallized layer 16 are formed. A light reflecting layer 8 was formed on the side surface 7.
Then, by cutting the multi-piece wiring boards K1 and K2 in the thickness direction with a cutter (not shown) along the planned cutting surface c, as shown in FIGS. A plurality of wiring boards 1a and 1b could be obtained.
The LED 9 is mounted on the element mounting portion a of the conductor portions 10a and 10b on the wiring boards 1a and 1b, and after the LED 9 and the pads 15, 15a and 15b are connected by the bonding wires w, The sealing resin before solidification is filled and solidified to almost the same level as the surface 3 of the substrate body 2.

以上のような配線基板1a,1bによれば、基板本体2の表面3に開口するキャビティ5の底面6に、表層に厚みが2μm超〜15μmのAu−Sn合金層14を有する導体部10a,10bが形成されている。このため、かかるAu−Sn合金層14上の素子搭載部aにLED9を搭載して加熱(リフロー)しても、かかるLED9の底面と上記ハンダ層14との間やハンダ層14中に気泡や気孔が生じにくくなる。従って、別途にハンダを用意することなく、搭載すべきLED9と素子搭載部aとの密着強度が向上し、LED9から導体部10a,10bへの伝熱性が向上すると共に、かかるLED9と導体部10との間における導通を安定させることも可能となる。
尚、前記多数個取り配線基板K1,K2において、配線基板1a,1bごとのキャビティ5の側面7に光反射層8を形成せず、かかる側面7を露出させることで、前記配線基板1c,1dを縦横に複数個配列した多数個取り配線基板を形成できると共に、これらを分割することで複数個の配線基板1c,1dが得られた。
According to the wiring boards 1a and 1b as described above, the conductor portion 10a having the Au—Sn alloy layer 14 having a thickness of more than 2 μm to 15 μm on the bottom surface 6 of the cavity 5 opened on the surface 3 of the substrate body 2; 10b is formed. For this reason, even if the LED 9 is mounted on the element mounting portion a on the Au—Sn alloy layer 14 and heated (reflowed), there are bubbles or bubbles between the bottom surface of the LED 9 and the solder layer 14 or in the solder layer 14. It becomes difficult to produce pores. Accordingly, the adhesion strength between the LED 9 to be mounted and the element mounting portion a is improved without separately preparing solder, the heat transfer from the LED 9 to the conductor portions 10a and 10b is improved, and the LED 9 and the conductor portion 10 are also improved. It is also possible to stabilize the conduction between the two.
In the multi-piece wiring boards K1 and K2, the light reflecting layer 8 is not formed on the side face 7 of the cavity 5 for each of the wiring boards 1a and 1b, but the side face 7 is exposed, so that the wiring boards 1c and 1d are exposed. A plurality of wiring boards in which a plurality of wiring boards are arranged vertically and horizontally can be formed, and a plurality of wiring boards 1c and 1d can be obtained by dividing them.

ここで、本発明の具体的な実施例について、比較例と併せて説明する。
アルミナからなり同じ厚みの複数のグリーンシートを用意し、その表面にW粉末粒子を含む導電性ペーストをスクリーン印刷して、同じパターンのメタライズ層を形成した。かかる複数のグリーンシートを所定の温度帯に加熱・焼成して、セラミック層とした。
焼成後の上記メタライズ層11の表面に対し、同じ条件で電解Niメッキおよび電解Auメッキをそれぞれ施して、同じ厚みのNiメッキ層12およびAuメッキ層13を形成した。かかるAuメッキ層13の表面粗さ(Ra)は、0.4μmとして統一した。
Here, specific examples of the present invention will be described together with comparative examples.
A plurality of green sheets made of alumina and having the same thickness were prepared, and a conductive paste containing W powder particles on the surface thereof was screen-printed to form a metallized layer having the same pattern. The plurality of green sheets were heated and fired at a predetermined temperature range to form a ceramic layer.
The surface of the metallized layer 11 after firing was subjected to electrolytic Ni plating and electrolytic Au plating under the same conditions to form a Ni plating layer 12 and an Au plating layer 13 having the same thickness. The surface roughness (Ra) of the Au plating layer 13 was unified as 0.4 μm.

次に、各セラミック層ごとの上記Auメッキ層13の表面に対し、表1に示す厚みが2.0〜20.0μmのAu−Sn合金層14を電解メッキによって、各厚みごとにそれぞれ10個ずつに形成した。
更に、上記Au−Sn合金層14が形成された複数のセラミック層において、かかるAu−Sn合金層14の上に同じLED9を載置し、当該Au−Sn合金の融点直上の温度帯に同じ時間で加熱(リフロー)した。
加熱後における各セラミック層をLED9の直下で切断し、目視によりAu−Sn合金層14の内部またはAu−Sn合金層14とLED9との間に気または気孔の有無を調べ、1個でも見つかった組には「有」、10個全てにおいて見つからなかった組には「なし」として、表1中において示した。
Next, on the surface of the Au plating layer 13 for each ceramic layer, 10 Au—Sn alloy layers 14 having a thickness of 2.0 to 20.0 μm shown in Table 1 are provided for each thickness by electrolytic plating. Formed one by one.
Further, in the plurality of ceramic layers on which the Au—Sn alloy layer 14 is formed, the same LED 9 is placed on the Au—Sn alloy layer 14 and the same time is kept in the temperature zone immediately above the melting point of the Au—Sn alloy. (Reflow).
Each of the ceramic layers after heating was cut directly under the LED 9, and the inside of the Au—Sn alloy layer 14 or between the Au—Sn alloy layer 14 and the LED 9 was visually checked to see if there was even one. It was shown in Table 1 as “Yes” for the group and “None” for the group that was not found in all 10 groups.

Figure 2008041811
Figure 2008041811

表1によれば、Au−Sn合金層14の厚みが3.0〜15.0μmの実施例と20.0μmの比較例では、気泡や気孔が生じていなかった。一方、Au−Sn合金層14の厚みが2.0μmの比較例では、気泡や気孔が生じていた。これは、Au−Sn合金層14の厚みが厚くなるに従い、その表面が平滑になり、セラミック層の反りなどの影響を吸収し易くなるため、Au−Sn合金層14の内部やLED9と当該Au−Sn合金層14との間で気泡や気孔が生じなかった、ものと推定される。
更に、表1中の下段に示すように、Au−Sn合金層14の厚みが20.0μmであると、メッキコストが高くなった(×印)のに対し、15.0μm以下であれば、通常のメッキコストと大差がない(○印)ことも分かった。更に、Au−Sn合金層14の厚みが15.0μm以下とすることで、隣接するパッド15との短絡を防ぎ易くなり、ファインピッチ性にも対応し易くなることが判明した。
According to Table 1, no bubbles or pores were generated in the examples in which the thickness of the Au—Sn alloy layer 14 was 3.0 to 15.0 μm and the comparative example in which the thickness was 20.0 μm. On the other hand, in the comparative example in which the thickness of the Au—Sn alloy layer 14 was 2.0 μm, bubbles and pores were generated. This is because the surface of the Au—Sn alloy layer 14 becomes smooth as the thickness of the Au—Sn alloy layer 14 increases, and it becomes easy to absorb the influence of warpage of the ceramic layer. Therefore, the inside of the Au—Sn alloy layer 14 and the LED 9 and the Au It is presumed that no bubbles or pores were generated between the alloy layer 14 and the Sn alloy layer 14.
Furthermore, as shown in the lower part of Table 1, when the thickness of the Au—Sn alloy layer 14 was 20.0 μm, the plating cost was high (marked with ×), whereas if it was 15.0 μm or less, It was also found that there was no significant difference from the normal plating cost (○ mark). Furthermore, it has been found that when the thickness of the Au—Sn alloy layer 14 is 15.0 μm or less, it is easy to prevent a short circuit with the adjacent pad 15 and to cope with fine pitch properties.

かかる結果から、前記導体部10a,10bの表層に形成するAu−Sn合金層14の厚みは、3.0(2μm超)〜15.0μmとすることで、気泡などの発生を防ぎ、且つ隣接するパッド15との短絡を容易に防止できると共に、コスト的にも支障が少ないことが判明した。
以上の実施例の結果から、本発明の効果が裏付けられた。
From these results, the thickness of the Au—Sn alloy layer 14 formed on the surface layer of the conductor portions 10a and 10b is set to 3.0 (over 2 μm) to 15.0 μm to prevent generation of bubbles and the like. It has been found that a short circuit with the pad 15 to be performed can be easily prevented, and that there are few problems in terms of cost.
From the results of the above examples, the effect of the present invention was confirmed.

図9は、異なる形態の配線基板21を示す平面図、図10は、図9中のZ−Z線の矢視に沿った垂直断面図である。
配線基板21は、図9,図10に示すように、平面視が長方形で表面23および裏面24を有する前記同様の複数のセラミック層s4〜s6からなる基板本体22と、かかる基板本体22の表面23に開口し、平面視がほぼ長円形の底面26および上記表面23に向かってほぼ長円錐形状に広がる側面27を有するキャビティ25と、を備えている。かかるキャビティ25の底面26における短軸方向に沿って、3つの導体部30a,30b,30cが帯状に形成されている。
このうち、中央の導体部30bは、底面26の一方の長辺から離れ、他の導体部30a,30cよりもやや短い。かかる導体部30a,30b,30cも、前記同様のメタライズ層、Niメッキ層、Auメッキ層、およびAu−Sn合金からなり厚みが2μm超〜15μmのAu−Sn合金層から形成されている。
FIG. 9 is a plan view showing a wiring board 21 of a different form, and FIG. 10 is a vertical cross-sectional view taken along the line ZZ in FIG.
As shown in FIGS. 9 and 10, the wiring substrate 21 includes a substrate body 22 composed of a plurality of ceramic layers s <b> 4 to s <b> 6 similar to the above and having a front surface 23 and a back surface 24 in a plan view and a surface of the substrate body 22. And a cavity 25 having a bottom surface 26 that is substantially oval in plan view and a side surface 27 that extends in a substantially conical shape toward the surface 23. Three conductor portions 30a, 30b, 30c are formed in a strip shape along the short axis direction of the bottom surface 26 of the cavity 25.
Among these, the central conductor portion 30b is separated from one long side of the bottom surface 26 and is slightly shorter than the other conductor portions 30a and 30c. The conductor portions 30a, 30b, and 30c are also formed of the same metallized layer, Ni plated layer, Au plated layer, and Au—Sn alloy, and an Au—Sn alloy layer having a thickness of more than 2 μm to 15 μm.

また、図9,図10に示すように、キャビティ25の底面26における長軸方向の両端付近と中央付近とには、3個のパッド31〜33が形成され、これらは、前記同様のメタライズ層の表面に、前記同様のNiメッキ層およびAuメッキ層を形成したもので、セラミック層s5内のビア導体vと個別に接続されている。
導体部30a,30b,30cには、LED(素子)29を搭載するための素子搭載部aを一部に含み、表層の前記ハンダ層を加熱(リフロー)することで、LED29を搭載できる。導体部30a,30b,30cごとに搭載されたLED29とパッド31〜33との間は、個別に図10中の二点差線で示すワイヤwによりボンディングされる。尚、素子搭載部aを除いた導体部30a〜30cのAu−Sn合金層からなる表面は、LED29の光を反射する光反射面を形成している。
Also, as shown in FIGS. 9 and 10, three pads 31 to 33 are formed near both ends and the center of the bottom surface 26 of the cavity 25 in the same manner as described above. The same Ni plating layer and Au plating layer as described above are formed on the surface, and are individually connected to the via conductors v in the ceramic layer s5.
The conductor portions 30a, 30b, and 30c partially include an element mounting portion a for mounting the LED (element) 29, and the LED 29 can be mounted by heating (reflowing) the solder layer on the surface layer. The LED 29 mounted on each of the conductor portions 30a, 30b, and 30c and the pads 31 to 33 are individually bonded by wires w indicated by two-dot chain lines in FIG. In addition, the surface which consists of Au-Sn alloy layer of the conductor parts 30a-30c except the element mounting part a forms the light reflection surface which reflects the light of LED29.

更に、図10に示すように、セラミック層s5,s6間には、Wなどからなり所定パターンを有する複数の配線層34が形成され、基板本体22の裏面24には、Wなどからなる複数の接続端子36,38が形成されている。
前記導体部30a〜30cおよびパッド31〜33は、セラミック層s5,s6を貫通するビア導体vを介して、それぞれ何れかの配線層34および接続端子36,38と導通可能とされている。尚、接続端子36,38は、本配線基板21を実装する図示しないマザーボードとの導通に用いられる。
Furthermore, as shown in FIG. 10, a plurality of wiring layers 34 made of W or the like and having a predetermined pattern are formed between the ceramic layers s5 and s6, and a plurality of wiring layers 34 made of W or the like are formed on the back surface 24 of the substrate body 22. Connection terminals 36 and 38 are formed.
The conductor portions 30a to 30c and the pads 31 to 33 can be electrically connected to any one of the wiring layers 34 and the connection terminals 36 and 38 through via conductors v penetrating the ceramic layers s5 and s6. The connection terminals 36 and 38 are used for electrical connection with a mother board (not shown) on which the wiring board 21 is mounted.

以上のような配線基板22によれば、別途にハンダを用意することなく、導体部30a〜30cごとの素子搭載部aにLED29を高い実装強度で搭載でき、且つ伝熱性も高められる。しかも、かかる3個のLED29に、赤(R)、緑(G)、青(B)の光を発光するものを用いることで、フルカラーの光を発光させ、かかる光を導体体部30a〜30cの光反射面およびキャビティ25の側面27に反射させ、外部に効率良く放射することも可能となる。
尚、上記配線基板22におけるキャビティ25の側面27全体に前記同様の光反射層を形成することで、更に広い面積により、フルカラーの光を反射させ且つ外部に一層効率良く放射することが可能となる。また、配線基板22は、前記同様の製造工程を経ることで得られる多数個取り配線基板を、切断・分割することで、効率良く確実に製造することが可能である。
According to the wiring board 22 as described above, the LED 29 can be mounted with high mounting strength on the element mounting portion a for each of the conductor portions 30a to 30c without separately preparing solder, and heat conductivity is also improved. In addition, by using those three LEDs 29 that emit red (R), green (G), and blue (B) light, full-color light is emitted and the light is transmitted through the conductor bodies 30a to 30c. It is also possible to reflect the light on the light reflecting surface and the side surface 27 of the cavity 25 and efficiently radiate to the outside.
By forming a light reflecting layer similar to the above on the entire side surface 27 of the cavity 25 in the wiring substrate 22, it is possible to reflect full-color light and radiate the outside more efficiently with a wider area. . In addition, the wiring board 22 can be efficiently and reliably manufactured by cutting and dividing a multi-piece wiring board obtained through the same manufacturing process as described above.

本発明は、前記各形態に限定されるものではない。
例えば、基板本体は、ガラス−セラミックのような低温焼成セラミックからなる形態や、エポキシ系などの樹脂層を複数積層して接着した形態としても良い。
また、前記基板本体は、キャビティがなく、平坦な表面を有すると共に、かかる表面に前記導体部およびパッドを形成した形態としても良い。
更に、前記導体部は、平面視で素子搭載部のみからなる(重複する)形態や、平面視で素子搭載部の周囲に僅かに延出するほぼ相似形の形態としても良い。
また、キャビティの側面は、基板本体の厚み方向に沿った垂直な面としても良く、アルミナのような白色系のセラミックが露出する形態では、そのままで光を反射させたり、前記光反射層を形成した形態としても良い。
更に、キャビティの側面における基板本体の表面側には、前記封止樹脂の浮き上がりを防ぐ突起または突条を、キャビティの中心部に向って単数または複数で突設するようにしても良い。
また、前記導体部の素子搭載部に搭載する素子には、ICチップなどのような電子部品も含まれる。
加えて、前記多数個取り配線基板は、そのままの形態または数個に分割した形態で、複数の配線基板ごとにおける各導体部の素子搭載部にLEDを搭載することで、比較的大型の発光装置として、活用することも可能である。
The present invention is not limited to the above embodiments.
For example, the substrate body may have a form made of a low-temperature fired ceramic such as glass-ceramic or a form in which a plurality of epoxy-based resin layers are laminated and bonded.
The substrate body may have a flat surface without a cavity, and the conductor and the pad may be formed on the surface.
Further, the conductor portion may be configured to include only (overlapping) the element mounting portion in a plan view, or may have a substantially similar shape that slightly extends around the element mounting portion in a plan view.
Further, the side surface of the cavity may be a vertical surface along the thickness direction of the substrate body. In the form in which a white ceramic such as alumina is exposed, light is reflected as it is or the light reflecting layer is formed. It is good also as the form which did.
Furthermore, one or a plurality of protrusions or ridges for preventing the sealing resin from floating may be provided on the surface side of the substrate body on the side surface of the cavity toward the center of the cavity.
The elements mounted on the element mounting portion of the conductor portion include electronic components such as an IC chip.
In addition, the multi-cavity wiring board is in a form as it is or divided into several parts, and an LED is mounted on the element mounting part of each conductor part in each of the plurality of wiring boards, so that a relatively large light emitting device It is also possible to utilize it.

本発明の配線基板を示す平面図。The top view which shows the wiring board of this invention. 図1中のX−X線の矢視に沿った垂直断面図。FIG. 2 is a vertical sectional view taken along line XX in FIG. 1. 図2中の一点鎖線部分Yの部分拡大図。The elements on larger scale of the dashed-dotted line part Y in FIG. 異なる形態の配線基板を示す平面図。The top view which shows the wiring board of a different form. 図1〜3の配線基板の応用形態を示す垂直断面図。FIG. 4 is a vertical sectional view showing an application form of the wiring board of FIGS. 図4の配線基板の応用形態を示す垂直断面図Vertical sectional view showing an application form of the wiring board of FIG. 図1〜3の配線基板を得るための多数個取り配線基板を示す平面図。The top view which shows the multi-piece wiring board for obtaining the wiring board of FIGS. 図4の配線基板を得るための多数個取り配線基板を示す平面図。FIG. 5 is a plan view showing a multi-cavity wiring board for obtaining the wiring board of FIG. 4. 更に異なる形態の配線基板を示す平面図。Furthermore, the top view which shows the wiring board of a different form. 図9中のZ−Z線の矢視に沿った垂直断面図。FIG. 10 is a vertical sectional view taken along the line ZZ in FIG. 9;

符号の説明Explanation of symbols

1a〜1d,21…………………………………配線基板
2,22……………………………………………基板本体
3,23……………………………………………表面
4,24……………………………………………裏面
5,25……………………………………………キャビティ
6,26……………………………………………底面
7,27……………………………………………側面
9,29……………………………………………発光ダイオード(素子)
10a,10b,30a〜30c………………導体部
11…………………………………………………メタライズ層
14…………………………………………………Au−Sn合金層
s1〜s6…………………………………………セラミック層(絶縁材)
a……………………………………………………素子搭載部
K1,K2…………………………………………多数個取り配線基板
A……………………………………………………製品領域
m……………………………………………………耳部
1a to 1d, 21 ………………………………… Wiring board 2,22 …………………………………………… Board body 3,23 …………… ……………………………… Front 4,24 …………………………………………… Back 5,25 ………………………………… ………… Cavity 6,26 …………………………………………… Bottom 7,27 …………………………………………… Side 9,29 …………………………………………… Light-emitting diode (element)
10a, 10b, 30a-30c ……………… Conductor 11 ………………………………………………… Metalized layer 14 ……………………………… ………………… Au—Sn alloy layer s1 to s6 ………………………………………… Ceramic layer (insulating material)
a …………………………………………………… Element mounting part K1, K2 ………………………………………… Multiple wiring board A… ………………………………………………… Product area m …………………………………………………… Ear

Claims (4)

絶縁材からなり、表面および裏面を有する基板本体と、
上記基板本体の表面に形成され、表層に厚みが2μm超のAu−Sn合金層を有する導体部と、を備え、
上記導体部は、素子搭載部であるか、かかる素子搭載部を一部に含む、
ことを特徴とする配線基板。
A substrate body made of an insulating material and having a front surface and a back surface;
A conductor part formed on the surface of the substrate body and having an Au-Sn alloy layer with a thickness of more than 2 μm on the surface layer;
The conductor part is an element mounting part or includes the element mounting part in part.
A wiring board characterized by that.
前記基板本体の表面は、かかる表面に開口するキャビティの底面であると共に、
前記導体部は、上記キャビティの底面に形成され、一部に素子搭載部を含む、
ことを特徴とする請求項1に記載の配線基板。
The surface of the substrate body is a bottom surface of a cavity that opens to the surface,
The conductor portion is formed on the bottom surface of the cavity and includes an element mounting portion in part.
The wiring board according to claim 1.
請求項1または2に記載の前記配線基板を縦横に複数個配列した製品領域と、
上記製品領域の周囲に位置し、前記絶縁材からなる耳部と、を備えている、
ことを特徴とする多数個取り配線基板。
A product region in which a plurality of the wiring boards according to claim 1 or 2 are arranged vertically and horizontally;
Located around the product area, and comprising ears made of the insulating material,
A multi-piece wiring board characterized by that.
絶縁材からなり、表面および裏面を有する基板本体を形成する工程と、
上記基板本体の表面に、メタライズ層を形成する工程と、
上記メタライズ層に電解メッキを施して、厚みが2μm超のAu−Sn合金層を形成する工程と、を含む、
ことを特徴とする配線基板の製造方法。
A step of forming a substrate body made of an insulating material and having a front surface and a back surface;
Forming a metallized layer on the surface of the substrate body;
Applying electroplating to the metallized layer to form an Au—Sn alloy layer having a thickness of more than 2 μm.
A method for manufacturing a wiring board.
JP2006211978A 2006-08-03 2006-08-03 Wiring circuit board, multiple-chip wiring circuit board, and method for manufacturing the wiring board Pending JP2008041811A (en)

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