JP2008028337A - Method of manufacturing electronic component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture an electronic component such that conductive material is embedded into a via hole formed in a substrate by using a plating method with favorable embedding characteristics. <P>SOLUTION: The manufacturing method includes: a plating step of embedding conductive material with a plating method by making current flow to a conductive layer used for power supply of electrolytic plating which is arranged so as to plug up two or more via holes formed in a substrate, and to a dummy conductive layer arranged in the substrate so as to control the current value passing through the conductive layer concerned by a constant current source; and a conductive pattern formation step of forming a conductive pattern connected to the above conductive material. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing an electronic component including a step of embedding a conductive material by an electrolytic plating method.

  When manufacturing various electronic components such as a wiring board and a semiconductor device, a plating process in which a via hole penetrating the board is embedded with a conductive material by a plating method may be used. The plating method has a feature that a conductive material can be easily embedded in a via hole at a high film formation rate.

  1A to 1B are diagrams schematically showing a method of manufacturing an electronic component using a plating method. First, in the step shown in FIG. 1A, a via hole 2A is formed in the insulating layer 2 formed on the core substrate 1, and a conductive layer 2B serving as a power feeding layer for electrolytic plating is formed by electroless plating. In this case, the conductive layer 2B is formed on the bottom surface of the via hole 2A (exposed insulating layer 2), the side wall surface of the via hole 2A, and further on the insulating layer 2.

Next, in the step shown in FIG. 1B, the via hole 2A is buried with the conductive material 3 by electrolytic plating using the conductive layer 2B formed in the step of FIG. 1A as a power feeding layer.
JP 2002-16357 A

  However, according to the above method, there is a problem that the void 3A is likely to be generated when the conductive material is embedded. For example, when the power feeding layer (electroconductive layer 2B) for electroplating is formed by electroless plating, the power feeding layer is formed not only on the bottom surface of the via hole 2A but also on the side wall surface of the via hole and further on the outside of the via hole. It will be. For this reason, the growth of electrolytic plating occurs not only from the bottom of the via hole, but also from the side wall surface of the via hole and the outside of the via hole (near the opening), so that the opening of the via hole is blocked and the plating coverage is reduced and voids are generated. There was a case.

  In the above-described method, voids tend to be easily generated particularly when the aspect ratio of the via hole is increased. For example, in the above method, it has been difficult to embed a conductive material in a void-free manner in a via hole having an aspect ratio of 1 or more.

  Further, in the above method, there is a problem that voids are easily generated when the growth rate of plating is increased, and it has been difficult to embed a conductive material with good embedment characteristics (coverage, embedment speed, etc.).

  In view of this, the present invention has a general object to provide a new and useful method of manufacturing an electronic component that solves the above-described problems.

  A specific problem of the present invention is to manufacture an electronic component by embedding a conductive material in a via hole formed in a substrate with a good embedding characteristic by a plating method.

  The present invention solves the above-described problem in order to control a current value flowing through the conductive layer, and a conductive layer used for power supply of electrolytic plating, which is installed so as to block a plurality of through holes formed in the substrate. A plating process in which a conductive material is embedded in the through hole by electrolytic plating by passing a current through a dummy conductive layer installed on the substrate by a constant current source, and a conductive pattern that forms a conductive pattern connected to the conductive material. It solves by the manufacturing method of the electronic component characterized by having a pattern formation process.

  According to the present invention, an electronic component can be manufactured by embedding a conductive material in a via hole formed in a substrate by a plating method with good embedding characteristics.

  In addition, it is preferable that the conductive layer and the dummy conductive layer are connected in parallel because it is easy to control the growth rate of the plating formed by the conductive layer.

  Further, it is preferable that the dummy conductive layer is provided at the peripheral portion of the substrate because the productivity of electronic parts is improved.

  The conductive layer and the dummy conductive layer may be bonded to the substrate with an adhesive layer.

  Moreover, you may further have the process of mounting a semiconductor chip in the said conductive pattern.

  According to the present invention, an electronic component can be manufactured by embedding a conductive material in a via hole formed in a substrate by a plating method with good embedding characteristics.

  FIG. 2 is a cross-sectional view for explaining the outline of the method of manufacturing an electronic component according to the present invention. The method for manufacturing an electronic component according to the present invention includes a step of burying a conductive material in a via hole (through hole) 102 formed in the substrate 101 by a plating method to form a via plug.

  In the manufacturing method described above, a conductive material is embedded in the via hole 102 by using the conductive layer 104 provided so as to close the plurality of via holes 102 formed in the substrate 101 as a power supply layer of an electrolytic plating method.

  In this case, since the power feeding layer (conductive layer 104) is formed only on the bottom surface of the via hole 102, the conductive material filled by electrolytic plating grows substantially only from the bottom surface of the via hole 102. For this reason, the embedding characteristic (coverage) of the plating becomes good, and it is possible to embed the conductive material while suppressing the generation of voids even when the aspect ratio of the via hole 102 is high.

  For example, in the electroplating method (FIGS. 1A to 1B) by forming a power feeding layer by electroless plating, it was difficult to bury a via hole having an aspect ratio of 1 or more in a void-free manner, A conductive material can be embedded in a fine via hole having an aspect ratio of about 1 to 20 while suppressing generation of voids.

  For example, in the above case, the conductive layer (feeding layer) 104 made of Cu is bonded to the substrate by the adhesive layer (adhesive material) 103 so as to close one end of the opening hole of the via hole 102 formed in the substrate 101 made of Si. 101 is attached. For example, in the above structure, a conductive material such as Cu can be embedded in the via hole 102 to form a via plug.

  In the above case, it is preferable to provide a dummy conductive layer on the substrate 101 in order to control the value of the current flowing through the conductive layer 104. In this case, when a current is supplied to the dummy conductive layer together with the conductive layer 104 using a constant current source, the value of the current flowing through the conductive layer 104 can be easily controlled. Further, the reason why the current value can be easily controlled by using the dummy conductive layer will be described later with reference to FIG.

  3A is a cross-sectional view schematically showing the whole of the substrate 101, the adhesive layer 103, the conductive layer 104, and the dummy conductive layer 104D described above with reference to FIG. 2, and FIG. It is a top view of the layer 104 and dummy conductive layer 104D. However, the same code | symbol is attached | subjected to the part demonstrated previously in FIG.

  3A and 3B, a conductive layer 104 is provided in a portion corresponding to the central portion of the substrate 101 where the via hole 102 is formed, and the periphery of the substrate 101 where the via hole 102 is not formed. A dummy conductive layer 104D is provided in a portion corresponding to the portion. Similar to the conductive layer 104, the dummy conductive layer 104 </ b> D is attached to the substrate 101 with the adhesive layer 103.

  In the above configuration, when the via hole 102 is embedded by electrolytic plating, the current value flowing through the conductive layer 104 is controlled by flowing a current through the dummy conductive layer 104D together with the conductive layer 104 using a constant current source. . For example, the conductive layer 104 is provided corresponding to a region where an electronic component (semiconductor chip) is formed on the substrate, and the dummy conductive layer 104D is formed corresponding to a region where no electronic component is formed on the substrate. preferable.

  FIG. 4 shows a specific example of a method for installing the conductive layer 104 and the dummy conductive layer 104D in the above case. FIG. 4 is an example showing the arrangement of electronic components formed on the substrate 101 and the installation of the conductive layer 104 and the dummy conductive layer 104D corresponding thereto.

  As shown in FIG. 4, in the manufacture of electronic components, a plurality of electronic components (semiconductor chips, illustrated in a square shape) are manufactured using a substrate 101, and the plurality of electronic components are separated in a later process (separated into individual pieces. There is a case. For example, in the case shown in this figure, electronic components are arranged in a lattice shape at the center of the substrate 101, and via holes (via plugs) used for the electronic components are formed in the substrate 101. The dummy conductive layer 104D is preferably disposed on the peripheral edge of the substrate 101 where no electronic component is formed.

  Further, the shape of the dummy conductive layer 104D is not limited to a donut shape as shown in the figure, and may be divided into a plurality of regions, for example. In addition, the shape of the dummy conductive layer in the case of being divided may be variously modified and changed such as a circle or a polygon.

  FIG. 5 is a diagram schematically showing a method of embedding a conductive material (Cu) in the via hole 102 of the substrate 101 shown in FIGS. 3A and 3B by electrolytic plating. However, the parts described above are denoted by the same reference numerals, and description thereof is omitted. In the drawing, the via hole 102 and the adhesive layer 103 are not shown.

  Referring to FIG. 5, a substrate (wafer) 101 serving as a cathode is supported by a jig and is immersed in a plating solution so as to face a Cu plate serving as an anode. The substrate 101 is provided with a dummy conductive layer 104D together with the conductive layer 104. The conductive layer 104 and the dummy conductive layer 104D are connected in parallel in a circuit in which a current for electrolytic plating flows. . A current is passed through the conductive layer 104 and the dummy conductive layer 104D by a power source (constant current power source).

  By connecting the dummy conductive layer 104D and the conductive layer 104 to the constant current power source in parallel as in the above configuration, the current flowing to the conductive layer 104 side is increased corresponding to the growth of the conductive material in the via hole 102. It becomes possible to make it.

  The above effect will be described using the equivalent circuits of FIGS. 6A and 6B. 6A is a diagram showing a simplified equivalent circuit in the conventional electrolytic plating, and FIG. 6B is a diagram showing a simplified equivalent circuit in the electrolytic plating shown in FIG. In the drawing, the conductive layer side where the via hole is formed is referred to as “product”, and the dummy conductive layer side where the via hole is not formed is referred to as “dummy”.

  First, referring to FIG. 6A, in the conventional plating method, when a constant current source (constant current power supply) is used, the current flowing through the conductive layer is constant regardless of the progress of plating in the via hole. is there.

  On the other hand, in the case of FIG. 6B, when the resistance value on the product side decreases, the current flowing by the constant current source increases on the product side. For example, when the conductive material embedded in the via hole is increased, the substantial aspect ratio of the via hole is reduced, and the efficiency of supplying the plating solution (ion) to the bottom of the via hole is improved. Therefore, on the product side, the resistance value gradually decreases as the plating grows, and the current value increases corresponding to the change in the resistance value.

  For this reason, according to the above plating, the growth rate of the plating gradually increases as the via hole burying progresses well and the probability of occurrence of voids decreases. That is, according to the above method, it is possible to increase the growth rate of plating while suppressing the generation of voids, and there is an effect of improving the embedment characteristics (coverage, embedment speed, etc.) of the conductive material. .

  As a result, the generation of voids in the via hole is suppressed, and the electrical reliability of the via plug formed in the via hole is improved. Furthermore, the efficiency (speed) for forming the via plug is also improved.

  Next, the details of the method for manufacturing the electronic component will be described step by step. However, the same reference numerals are given to the portions described above in the following drawings, and the description may be omitted.

  First, in the step shown in FIG. 7A, a substrate (wafer) 101 made of, for example, Si is thinned by back surface grinding so that the thickness becomes about 200 μm. Next, a plurality of via holes (through holes) 102 having a diameter of, for example, 60 μm are formed in the substrate 101 by dry etching using a mask pattern (not shown) formed by photolithography.

  Next, in the step shown in FIG. 7B, the surface of the substrate 101 is thermally oxidized to form an insulating film (thermal oxide film) 105. Further, the insulating film 105 may be partially peeled off as necessary. For example, in a later step, the insulating film 105 where anodic bonding is performed with respect to Si may be peeled off.

  Next, in the step shown in FIG. 7C, the conductive layer 104 made of Cu, for example, and the dummy conductive layer 104D (not shown in this drawing) are formed on the substrate 101 using the adhesive layer (layer made of an adhesive material) 103. paste. In this case, the conductive layer 104 is attached so as to close the opening on one side of the via hole 102. In addition, as described above, the dummy conductive layer 104D is preferably attached to the peripheral portion of the substrate 101 where no electronic component is formed.

  Next, in the step shown in FIG. 7D, the adhesive layer 103 at the bottom of the via hole 102 is removed to expose the conductive layer 104, and then the conductive material (in the via hole 102 is electroplated using the conductive layer 104 as a power feeding layer). Cu) is buried and a via plug 106 is formed.

  In this case, as previously described with reference to FIGS. 3A, 3B, 4 to 5, etc., the conductive layer 104 and the dummy conductive layer 104D connected in parallel using a constant current source (not shown in this figure) By passing a current through the via hole 102, the via hole 102 can be buried with good burying characteristics. That is, the generation of voids when the via hole 102 is buried is suppressed, and the time required for forming the via plug 106 is shortened.

  Next, in the step shown in FIG. 7E, the conductive layer 104 and the adhesive layer 103 are removed, and in the step shown in FIG. 7F, Cu protruding from the via hole 102 is removed by polishing.

  Next, in the step shown in FIG. 7G, the upper surface of the substrate 101 (the surface opposite to the side where the conductive layer 104 was placed, the same applies to the following) and the insulating layer 105 on the lower surface of the substrate 101 are electrically conductive. Layers 107 and 108 are formed.

  For example, the conductive layers 107 and 108 have a Cr (thickness 50 nm) / Cu (thickness 750 nm) structure (a stacked structure in which Cu is on the outside) and are formed by a sputtering method. These conductive layers 107 and 108 serve as a power feeding layer when a conductive pattern connected to the via plug 106 is formed by an electrolytic plating method in a later step.

  Next, in a step shown in FIG. 7H, a conductive pattern 109 made of Cu connected to the via plug 106 is formed on the lower surface of the substrate 101 by pattern plating using a plating resist (not shown). In the above electrolytic plating, the conductive layer 108 is used as a power feeding layer. Further, the conductive layer 108 exposed by peeling the plating resist after the formation of the conductive pattern 109 is peeled off by etching.

  Next, in the step shown in FIG. 7I, a protective layer (insulating layer) 111 covering the insulating film 105 is formed so as to expose a part of the conductive pattern 109. In addition, a connection layer 110 made of, for example, a Ni / Au structure (a laminated structure with Au on the outside) is formed on the conductive pattern 109 exposed from the protective layer 111 by electrolytic plating.

  Next, in a step shown in FIG. 7J, a conductive pattern 112 made of Cu connected to the via plug 106 is formed on the upper surface of the substrate 101 by pattern plating using a plating resist (not shown). In the above electrolytic plating, the conductive layer 107 is used as a power feeding layer. Furthermore, a connection layer 113 made of, for example, a Ni / Au structure is formed on the conductive pattern 112 by an electrolytic plating method. Further, the conductive layer 107 exposed by the plating resist peeling after the formation of the conductive pattern 112 and the connection layer 113 is peeled off by etching.

  In this manner, a wiring board (electronic component) having via plugs 106 penetrating the substrate 101 and conductive patterns 109 and 112 connected to the via plugs 106 can be manufactured. Further, a semiconductor chip may be further mounted on the above wiring board, and an electronic component having a structure in which the semiconductor chip is mounted may be configured.

  For example, in the step shown in FIG. 7K, the semiconductor chip 201 to which the bump 202 made of Au is connected is mounted on the connection layer 113. In this case, the semiconductor chip can be flip-chip mounted by bonding the bump 202 and the Au of the connection layer 113 using ultrasonic waves.

  Further, in the step shown in FIG. 7L, the substrate 101 is cut into pieces by dicing. Further, when the semiconductor chip 201 is made of an optical functional element such as a light emitting element or a light receiving element, a cover 203 made of a light transmissive material is bonded onto the substrate 101 as necessary, and the semiconductor chip 201 is sealed. It is good also as a structure. When the light transmissive material is made of glass, the cover 203 is bonded to the substrate 101 by anodic bonding. In this case, a convex portion of the cover 203 may be bonded to a portion where the insulating film 105 is peeled and Si is exposed. Further, solder balls 114 may be formed on the connection layer 110 as external connection terminals.

  In this way, an electronic component in which the semiconductor chip 201 is mounted on the substrate 101 can be manufactured.

  According to the above manufacturing method, when the via plug 106 penetrating the substrate 101 is formed, it is possible to increase the growth rate of plating while suppressing the generation of voids, and highly efficient electronic components with high efficiency can be obtained. It becomes possible to produce with.

  Further, in the above manufacturing method, when the via hole 102 of the substrate 101 is embedded by electrolytic plating, the growth of plating occurs substantially only from the bottom surface (conductive layer 104), so even for a via hole having a high aspect ratio, It is possible to bury the conductive material (form the via plug 106) while suppressing the generation of voids.

  For example, according to the above manufacturing method, a via hole having an aspect ratio of about 1 to 20 can be buried free of voids. The above manufacturing method can be applied to a via hole having a diameter of 10 to 200 μm. However, these numerical values are examples, and the present invention is not limited to these numerical values.

  It is also possible to form a multilayer wiring board by a so-called buildup method by forming conductive patterns and insulating layers in multiple layers on via plugs that penetrate the substrate.

  Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the specific embodiments described above, and various modifications and changes can be made within the scope described in the claims.

  According to the present invention, an electronic component can be manufactured by embedding a conductive material in a via hole formed in a substrate by a plating method with good embedding characteristics.

It is a figure (the 1) which shows the manufacturing method of the conventional electronic component. It is FIG. (2) which shows the manufacturing method of the conventional electronic component. 1 is a diagram showing an outline of a method for manufacturing an electronic component according to Example 1. FIG. It is FIG. (1) which shows an example of the installation method of a conductive layer. It is a top view of FIG. 3A. It is a figure (the 2) which shows an example of the installation method of a conductive layer. It is a figure which shows the control method of the electric current value of a conductive layer. It is FIG. (1) which shows the equivalent circuit of electrolytic plating. It is FIG. (2) which shows the equivalent circuit of electrolytic plating. FIG. 6 is a diagram (No. 1) illustrating a method for manufacturing an electronic component according to the first embodiment. FIG. 6 is a diagram (No. 2) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 3 is a diagram (No. 3) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 6 is a diagram (No. 4) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 10 is a diagram (No. 5) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 6 is a view (No. 6) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 7 is a view (No. 7) showing a method for manufacturing an electronic component according to Example 1. FIG. 8 is a view (No. 8) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 9 is a diagram (No. 9) illustrating a method for manufacturing an electronic component according to Example 1. FIG. 10 is a view (No. 10) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 11 is a view (No. 11) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 12 is a view (No. 12) illustrating the method for manufacturing the electronic component according to the first embodiment.

Explanation of symbols

101 Substrate 102 Via hole (through hole)
DESCRIPTION OF SYMBOLS 103 Adhesive layer 104 Conductive layer 104D Dummy conductive layer 105 Insulating film 106, 106A Via plug 107, 108 Conductive layer 109, 112 Conductive pattern 110, 113 Connection layer 111 Protective layer 114 Solder ball 201 Semiconductor chip 202 Bump 203 Cover

Claims (5)

A conductive layer used for power supply for electrolytic plating, installed so as to block a plurality of through-holes formed in the substrate, and a dummy conductive layer installed on the substrate to control a current value flowing through the conductive layer; A plating process in which a conductive material is embedded in the through hole by electrolytic plating by passing a current through a constant current source;
And a conductive pattern forming step of forming a conductive pattern connected to the conductive material.   The method of manufacturing an electronic component according to claim 1, wherein the conductive layer and the dummy conductive layer are connected in parallel.   The method of manufacturing an electronic component according to claim 1, wherein the dummy conductive layer is disposed on a peripheral portion of the substrate.   The method of manufacturing an electronic component according to claim 1, wherein the conductive layer and the dummy conductive layer are bonded to the substrate by an adhesive layer.   The method of manufacturing an electronic component according to claim 1, further comprising a step of mounting a semiconductor chip on the conductive pattern.

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