JP2008016814A - 不揮発性メモリ素子及びその製造方法 - Google Patents
不揮発性メモリ素子及びその製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 230000000903 blocking effect Effects 0.000 claims abstract description 65
- 238000000034 method Methods 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 150000004767 nitrides Chemical class 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910021193 La 2 O 3 Inorganic materials 0.000 claims description 2
- 229910019899 RuO Inorganic materials 0.000 claims description 2
- 229910002367 SrTiO Inorganic materials 0.000 claims description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 229910052741 iridium Inorganic materials 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 229910052707 ruthenium Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 2
- -1 tungsten nitride Chemical class 0.000 claims description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 2
- 238000009279 wet oxidation reaction Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000007740 vapor deposition Methods 0.000 claims 1
- 238000009826 distribution Methods 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- SJHPCNCNNSSLPL-CSKARUKUSA-N (4e)-4-(ethoxymethylidene)-2-phenyl-1,3-oxazol-5-one Chemical compound O1C(=O)C(=C/OCC)\N=C1C1=CC=CC=C1 SJHPCNCNNSSLPL-CSKARUKUSA-N 0.000 description 1
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- LPQOADBMXVRBNX-UHFFFAOYSA-N ac1ldcw0 Chemical compound Cl.C1CN(C)CCN1C1=C(F)C=C2C(=O)C(C(O)=O)=CN3CCSC1=C32 LPQOADBMXVRBNX-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
【解決手段】SONOS構造のチャージトラップ膜102とブロッキング絶縁膜104の間に伝導体層103を形成し、ゲートに電圧を印加した場合、伝導体層103が電圧分配をするようにしてブロッキング絶縁膜104のEOT(EquivalentOxide Thickness)とチャージトラップ膜102とトンネル絶縁膜101のEOT調節により所望の水準の電圧をブロッキング絶縁膜104とチャージトラップ膜102及びトンネル絶縁膜101にそれぞれ印加されるようにしてセルの消去速度を改善する。
【選択図】図8
Description
= C×V/[C3×T3]
(厚さ)T=T1(トンネル絶縁膜)+T2(チャージトラップ膜)+ T3(ブロッキング絶縁膜)
1/C =(1/C1 + 1/C2 + 1/ C3)
:C1(トンネル絶縁膜cap)、C2(チャージトラップ膜cap)、C3(ブロッキング絶縁膜cap)
101 :トンネル絶縁膜
102 :チャージトラップ膜
103 : ブロッキングゲート
104 : ブロッキング絶縁膜
105 :キャッピングポリシリコン膜
106 :コンタクトマスク
107 :開口
108 :ポリシリコン膜
109 :金属膜
110 :ハードマスク
120 :ゲート電極
Claims (18)
- 半導体基板上に形成されたトンネル絶縁膜;
上記トンネル絶縁膜上に形成されたチャージトラップ(charge trap)膜;
上記チャージトラップ膜上に形成されたブロッキングゲート;
上記ブロッキングゲート上に形成されたブロッキング絶縁膜;及び
上記ブロッキング絶縁膜上に形成されたゲート電極と、
を含む不揮発性メモリ素子。 - 上記ゲート電極及び上記ブロッキングゲートは開口を通じて連結される請求項1に記載の不揮発性メモリ素子。
- 上記ブロッキングゲートは、ポリシリコン及び金属を含む導電物質で形成される請求項1に記載の不揮発性メモリ素子。
- 半導体基板上にトンネル絶縁膜を形成する段階;
上記トンネル絶縁膜上にチャージトラップ膜を形成する段階;
上記チャージトラップ膜上にブロッキングゲートを形成する段階;
上記ブロッキングゲート上にブロッキング絶縁膜を形成する段階;及び
上記ブロッキング絶縁膜上にゲート電極を形成する段階と、
を含む不揮発性メモリ素子の製造方法。 - 上記ブロッキング絶縁膜を形成した後、上記ブロッキングゲートと上記ゲート電極を連結させるためにソース選択トランジスタ及びドレイン選択トランジスタが形成される領域の上記ブロッキング絶縁膜の所定領域をエッチングして上記ブロッキングゲートを露出させる開口を形成する段階をさらに含む請求項4に記載の不揮発性メモリ素子の製造方法。
- 上記トンネル絶縁膜、チャージトラップ膜、ブロッキング絶縁膜はそれぞれ2〜500Åの厚さで形成する請求項4に記載の不揮発性メモリ素子の製造方法。
- 上記トンネル絶縁膜は、湿式酸化方式またはラジカル酸化方式で形成する請求項4に記載の不揮発性メモリ素子の製造方法。
- 上記チャージトラップ膜はALD、PE-ALDまたはCVD蒸着技法を用いて形成する請求項4に記載の不揮発性メモリ素子の製造方法。
- 上記ブロッキングゲートは、ポリシリコン及び金属を含む導電物質である請求項4に記載の不揮発性メモリ素子の製造方法。
- 上記ブロッキング絶縁膜は、高誘電率を有する酸化膜で形成する請求項4に記載の不揮発性メモリ素子の製造方法。
- 上記高誘電率を有する酸化膜はAl2O3、HfO2、ZrO3、Al2O3-HfO2の混合体、SrTiO3、La2O3、(Ba、Sr)TiO3からなるグループより選択して形成する請求項10に記載の不揮発性メモリ素子の製造方法。
- 上記ブロッキング絶縁膜はALD、PE-ALDまたはCVD蒸着技法で形成した後、RTA工程を追加で進行する請求項10に記載の不揮発性メモリ素子の製造方法。
- 上記ブロッキング絶縁膜は、蒸着温度を200〜1000℃の温度で形成する請求項12に記載の不揮発性メモリ素子の製造方法。
- 上記ブロッキング絶縁膜は、上記蒸着温度より高い温度で上記RTA工程を進行し、この時、昇温速度を1〜100℃/secで実施する請求項13に記載の不揮発性メモリ素子の製造方法。
- 上記ブロッキング絶縁膜の代わりにSiN膜を用いる請求項4に記載の不揮発性メモリ素子の製造方法。
- 上記開口形成工程はエッチングマスクを用いたエッチング工程で形成し、上記エッチングマスクは窒化膜、酸化膜、非晶質カーボン、またはフォトレジストを用いて形成する請求項5に記載の不揮発性メモリ素子の製造方法。
- 上記ゲート電極は、ポリシリコン膜あるいはポリシリコン膜上に金属膜を積層して形成する請求項4に記載のSONOS構造を有するフラッシュメモリ素子の製造方法。
- 上記金属膜はタングステン、タングステンシリサイド、タングステン窒化膜、Ru、Ir、RuO2、IrO2、Ptを用いて形成する請求項17に記載の不揮発性メモリ素子の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020060063134A KR100771808B1 (ko) | 2006-07-05 | 2006-07-05 | Sonos 구조를 갖는 플래시 메모리 소자 및 그것의제조 방법 |
Publications (1)
Publication Number | Publication Date |
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JP2008016814A true JP2008016814A (ja) | 2008-01-24 |
Family
ID=38816419
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2007062781A Pending JP2008016814A (ja) | 2006-07-05 | 2007-03-13 | 不揮発性メモリ素子及びその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7566618B2 (ja) |
JP (1) | JP2008016814A (ja) |
KR (1) | KR100771808B1 (ja) |
CN (1) | CN100547809C (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8129775B2 (en) | 2008-12-15 | 2012-03-06 | Tokyo Electron Limited | Semiconductor device and method of manufacturing the same |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7955960B2 (en) | 2007-03-22 | 2011-06-07 | Hynix Semiconductor Inc. | Nonvolatile memory device and method of fabricating the same |
KR101017506B1 (ko) * | 2007-05-03 | 2011-02-25 | 주식회사 하이닉스반도체 | 반도체 메모리 소자 및 이의 제조 방법 |
CN100578669C (zh) * | 2008-01-28 | 2010-01-06 | 南京航空航天大学 | 一种非易失存储器 |
JP2010067854A (ja) * | 2008-09-11 | 2010-03-25 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
WO2010046873A1 (en) * | 2008-10-23 | 2010-04-29 | Nxp B.V. | Multi-transistor memory cell |
KR101036744B1 (ko) * | 2009-01-29 | 2011-05-24 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 제조 방법 |
KR101146872B1 (ko) * | 2009-05-21 | 2012-05-17 | 에스케이하이닉스 주식회사 | 불휘발성 메모리 소자의 제조 방법 |
KR20130023994A (ko) * | 2011-08-30 | 2013-03-08 | 에스케이하이닉스 주식회사 | 반도체 소자 및 이의 제조방법 |
KR102275051B1 (ko) * | 2014-01-21 | 2021-07-07 | 어플라이드 머티어리얼스, 인코포레이티드 | 3d 플래시 메모리 애플리케이션을 위한 유전체-금속 스택 |
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-
2006
- 2006-07-05 KR KR1020060063134A patent/KR100771808B1/ko not_active IP Right Cessation
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2007
- 2007-03-08 US US11/683,718 patent/US7566618B2/en not_active Expired - Fee Related
- 2007-03-13 JP JP2007062781A patent/JP2008016814A/ja active Pending
- 2007-03-27 CN CNB2007100869750A patent/CN100547809C/zh not_active Expired - Fee Related
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2009
- 2009-06-23 US US12/489,785 patent/US8044454B2/en not_active Expired - Fee Related
Patent Citations (4)
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---|---|---|---|---|
JPS5955071A (ja) * | 1982-09-24 | 1984-03-29 | Hitachi Micro Comput Eng Ltd | 不揮発性半導体装置 |
JPH11289021A (ja) * | 1998-04-02 | 1999-10-19 | Hitachi Ltd | 半導体集積回路装置およびその製造方法ならびにマイクロコンピュータ |
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US20060131633A1 (en) * | 2004-12-21 | 2006-06-22 | Micron Technology, Inc. | Integrated two device non-volatile memory |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US8129775B2 (en) | 2008-12-15 | 2012-03-06 | Tokyo Electron Limited | Semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
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CN100547809C (zh) | 2009-10-07 |
KR100771808B1 (ko) | 2007-10-30 |
US20080006873A1 (en) | 2008-01-10 |
US8044454B2 (en) | 2011-10-25 |
US20090261404A1 (en) | 2009-10-22 |
CN101101925A (zh) | 2008-01-09 |
US7566618B2 (en) | 2009-07-28 |
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