JP2008016785A - 樹脂封止回路装置 - Google Patents
樹脂封止回路装置 Download PDFInfo
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- JP2008016785A JP2008016785A JP2006207092A JP2006207092A JP2008016785A JP 2008016785 A JP2008016785 A JP 2008016785A JP 2006207092 A JP2006207092 A JP 2006207092A JP 2006207092 A JP2006207092 A JP 2006207092A JP 2008016785 A JP2008016785 A JP 2008016785A
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- solder
- semiconductor device
- chip electronic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
【解決手段】半導体装置3と配線基板2との接合は半田バンプ8で行われ、またはアンダーフィル6が形成されている部分のチップ電子部品4と配線基板2との接合は半田9によって行われる。半田バンプ8及び半田9に用いる材料に1度目の加熱による溶融温度よりも再度加熱した時の溶融温度が高くなる半田を用いる。
【選択図】図1
Description
2、12 配線基板
3、13 半導体装置
4、14 チップ電子部品
5、15 外装樹脂
6、16 アンダーフィル
7、17 ランド
8 バンプ
9、19 半田
10 半田の溶融流出
18 ワイヤ
Claims (2)
- 配線基板と、前記配線基板上に実装された半導体装置と、前記半導体装置の周囲に配置されたランドに半田接合された1つ以上のチップ電子部品と、前記半導体装置及び前記チップ電子部品を被覆する外装樹脂と、を有する樹脂封止回路装置において、
前記半導体装置の下面と前記配線基板との空間と、前記チップ電子部品の少なくとも一部に接する部分と、にアンダーフィルが形成されており、
前記アンダーフィルが形成されている部分の前記チップ電子部品の半田接合に、1度目の加熱による溶融温度よりも再度加熱した時の溶融温度が高くなる半田が用いられていることを特徴とする樹脂封止回路装置。 - 配線基板と、前記配線基板上のランドに半田接合された1つ以上のチップ電子部品と、前記チップ電子部品の一部の上に実装された半導体装置と、前記半導体装置及び前記チップ電子部品を被覆する外装樹脂と、を有する樹脂封止回路装置において、
前記半導体装置の下面と前記配線基板との間にアンダーフィルが形成されており、
前記アンダーフィルが形成されている部分の前記チップ電子部品の半田接合に、1度目の加熱による溶融温度よりも再度加熱した時の溶融温度が高くなる半田が用いられていることを特徴とする樹脂封止回路装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006207092A JP4963890B2 (ja) | 2006-06-30 | 2006-06-30 | 樹脂封止回路装置 |
Applications Claiming Priority (1)
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JP2006207092A JP4963890B2 (ja) | 2006-06-30 | 2006-06-30 | 樹脂封止回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008016785A true JP2008016785A (ja) | 2008-01-24 |
JP4963890B2 JP4963890B2 (ja) | 2012-06-27 |
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JP2006207092A Expired - Fee Related JP4963890B2 (ja) | 2006-06-30 | 2006-06-30 | 樹脂封止回路装置 |
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JP (1) | JP4963890B2 (ja) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001267473A (ja) * | 2000-03-17 | 2001-09-28 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2002254195A (ja) * | 2000-12-25 | 2002-09-10 | Tdk Corp | はんだ付け用組成物及びはんだ付け方法 |
JP2004128288A (ja) * | 2002-10-04 | 2004-04-22 | Renesas Technology Corp | 半導体装置および電子装置 |
JP2004247637A (ja) * | 2003-02-17 | 2004-09-02 | Nec Saitama Ltd | 電子部品の三次元実装構造および方法 |
-
2006
- 2006-06-30 JP JP2006207092A patent/JP4963890B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001267473A (ja) * | 2000-03-17 | 2001-09-28 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2002254195A (ja) * | 2000-12-25 | 2002-09-10 | Tdk Corp | はんだ付け用組成物及びはんだ付け方法 |
JP2004128288A (ja) * | 2002-10-04 | 2004-04-22 | Renesas Technology Corp | 半導体装置および電子装置 |
JP2004247637A (ja) * | 2003-02-17 | 2004-09-02 | Nec Saitama Ltd | 電子部品の三次元実装構造および方法 |
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JP4963890B2 (ja) | 2012-06-27 |
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