JP2008010632A - Method for manufacturing semiconductor device, semiconductor device manufactured thereby, and sheet to be used therein - Google Patents

Method for manufacturing semiconductor device, semiconductor device manufactured thereby, and sheet to be used therein Download PDF

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JP2008010632A
JP2008010632A JP2006179591A JP2006179591A JP2008010632A JP 2008010632 A JP2008010632 A JP 2008010632A JP 2006179591 A JP2006179591 A JP 2006179591A JP 2006179591 A JP2006179591 A JP 2006179591A JP 2008010632 A JP2008010632 A JP 2008010632A
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die pad
semiconductor element
opening
semiconductor device
external electrode
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JP4549318B2 (en
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Daisuke Takao
大輔 高尾
Masahiro Tomiya
正博 富家
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Aoi Electronics Co Ltd
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Aoi Electronics Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of omitting an independent process for forming a through-hole to prevent a defect from being generated in re-flow. <P>SOLUTION: A die pad 4b having an opening 6 is formed on a metallic plate. A die bonding material 5 is coated on the Ag layer 24 of the die pad, and a semiconductor element 2 is mounted on the die pad 4b so as to clog the opening 6 of the die pad 4b. Then, sealing is performed with a resin 8. Even when resin sealing is performed, the opening 6 is clogged by the semiconductor element 2, so that the resin does not invade the opening 6. When the metallic plate is separated from the resin 8 after the sealing is terminated with the resin 8, the bottom surface of the semiconductor element 2 is exposed in the opening 6 of the die pad 4b. Thus, the through-hole is formed for preventing the defect from being generated in re-flow. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

本発明は、半導体装置の製造方法、その製造方法で製造した半導体装置およびその製造方法に用いるシートに関する。   The present invention relates to a semiconductor device manufacturing method, a semiconductor device manufactured by the manufacturing method, and a sheet used for the manufacturing method.

はんだリフロー時のパッケージクラック、剥離、ふくれ発生などの不良発生を防止するために、半導体チップを搭載する絶縁性基板に貫通孔を設ける半導体パッケージが従来技術として知られている(たとえば、特許文献1)。
特開平10−223795号公報
A semiconductor package in which a through hole is provided in an insulating substrate on which a semiconductor chip is mounted is known as a prior art in order to prevent occurrence of defects such as package cracking, peeling, and blistering during solder reflow (for example, Patent Document 1). ).
Japanese Patent Laid-Open No. 10-223795

上記特許文献1に記載されているような従来の半導体パッケージでは、パッケージクラックなどの不良発生を防止するための貫通孔を設けるには、ドリル加工やパンチングなどの機械加工、エキシマレーザや炭酸ガスレーザなどのレーザ加工などを行わなくてはならず、貫通孔の形成が面倒であるという問題点がある。   In the conventional semiconductor package described in Patent Document 1, in order to provide a through hole for preventing the occurrence of defects such as package cracks, machining such as drilling or punching, excimer laser, carbon dioxide gas laser, etc. However, there is a problem that the formation of the through hole is troublesome.

(1)請求項1の発明の半導体装置は、半導体素子と、開口部を有し、開口部を塞ぐように半導体素子を搭載するダイパッドと、半導体素子とワイヤにより電気的に接続している外部電極とを備え、ダイパッドおよび外部電極は電鋳によって形成され、ダイパッドと外部電極が底面において露出するように半導体素子とダイパッドとワイヤと外部電極とを樹脂により封止し、半導体素子が開口部において露出していることを特徴とする。
(2)請求項2の発明は、請求項1に記載の半導体装置において、半導体素子をダイパッドにAgペースト、絶縁ペーストおよび接着フィルムのうちのいずれかを使用して固定することを特徴とする。
(3)請求項3の発明は、請求項2に記載の半導体装置において、開口部の形状は、略十字型であることを特徴とする。
(4)請求項4の発明の半導体装置は、半導体素子と、開口部を有し、半導体素子を搭載するダイパッドと、開口部を塞ぐようにダイパッドに貼付され、ダイパッドに半導体素子を貼着する接着フィルムと、半導体素子とワイヤにより電気的に接続している外部電極とを備え、ダイパッドおよび外部電極は電鋳によって形成され、ダイパッドと外部電極が底面において露出するように半導体素子と前記ダイパッドとワイヤと前記外部電極とを樹脂により封止し、接着フィルムが開口部において露出していることを特徴とする。
(5)請求項5の発明の半導体装置の製造方法は、開口部を有するダイパッドと、ダイパッドの外側に配設される外部電極とからなる一組の金属層を可撓性シートに複数隣接配置して形成する金属層形成工程と、開口部を塞ぐように、ダイパッドに半導体素子を搭載し、半導体素子と外部電極とを電気的に接続する半導体素子実装工程と、金属層および半導体素子を樹脂封止する樹脂封止工程と、可撓性シートを剥離して樹脂封止体を得る剥離工程と、樹脂封止体を切断して、個々の半導体装置に分割する分割工程とを備えることを特徴とする。
(6)請求項6の発明の半導体装置作製用シートは、可撓性を有する金属板と、金属板上に電鋳によって形成され、開口部を有し、半導体素子が搭載されるダイパッドと、同じく電鋳によって形成され、半導体素子とワイヤにより電気的に接続される外部電極とを備えることを特徴とする。
(1) The semiconductor device of the invention of claim 1 includes a semiconductor element, a die pad having an opening, and a semiconductor element mounted so as to close the opening, and an external electrically connected to the semiconductor element by a wire. The die pad and the external electrode are formed by electroforming, and the semiconductor element, the die pad, the wire, and the external electrode are sealed with a resin so that the die pad and the external electrode are exposed on the bottom surface, and the semiconductor element is in the opening It is exposed.
(2) The invention of claim 2 is characterized in that, in the semiconductor device of claim 1, the semiconductor element is fixed to the die pad using any one of Ag paste, insulating paste and adhesive film.
(3) The invention of claim 3 is the semiconductor device according to claim 2, wherein the shape of the opening is substantially cross-shaped.
(4) The semiconductor device of the invention of claim 4 has a semiconductor element, an opening, a die pad on which the semiconductor element is mounted, affixed to the die pad so as to close the opening, and a semiconductor element is adhered to the die pad. An adhesive film; and an external electrode electrically connected to the semiconductor element by a wire. The die pad and the external electrode are formed by electroforming, and the semiconductor element and the die pad are exposed so that the die pad and the external electrode are exposed on the bottom surface. The wire and the external electrode are sealed with resin, and the adhesive film is exposed at the opening.
(5) In the method of manufacturing a semiconductor device according to the fifth aspect of the present invention, a plurality of metal layers each including a die pad having an opening and an external electrode disposed outside the die pad are disposed adjacent to the flexible sheet. Forming the metal layer, mounting the semiconductor element on the die pad so as to close the opening, and electrically connecting the semiconductor element and the external electrode; and the metal layer and the semiconductor element as a resin A resin sealing step for sealing, a peeling step for peeling the flexible sheet to obtain a resin sealing body, and a dividing step for cutting the resin sealing body and dividing it into individual semiconductor devices. Features.
(6) A semiconductor device manufacturing sheet of the invention of claim 6 is a metal plate having flexibility, a die pad formed on the metal plate by electroforming, having an opening, and on which a semiconductor element is mounted, It is also formed by electroforming, and includes an external electrode electrically connected by a semiconductor element and a wire.

本発明によれば、半導体素子を搭載するダイパッドを電鋳によって開口部を設けて形成したので、貫通孔を形成するために別段の工程を設ける必要がない。   According to the present invention, since the die pad for mounting the semiconductor element is formed by providing the opening by electroforming, it is not necessary to provide a separate step for forming the through hole.

本発明の実施形態の半導体装置について図1を参照して説明する。図1(a)は半導体装置1Aの裏面図であり、図1(b)は図1(a)のA−A’線断面図、図1(c)は図1(a)のB−B’線断面図である。   A semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 1A is a rear view of the semiconductor device 1A, FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. 1A, and FIG. 1C is a cross-sectional view taken along line BB of FIG. FIG.

図1において、符号1Aは平面視矩形形状の半導体装置、2はAgペーストから成るダイボンディング材5によりダイパッド4bの上面に実装された半導体素子である。ダイパッド4bには開口部6が設けられており、半導体素子2の底面が露出している。ダイパッド4bの外側には外部電極3bが配設されている。また、半導体装置1Aの4隅には補強パッド9bが配設されている。   In FIG. 1, reference numeral 1A denotes a semiconductor device having a rectangular shape in plan view, and 2 denotes a semiconductor element mounted on the upper surface of a die pad 4b by a die bonding material 5 made of Ag paste. The die pad 4b is provided with an opening 6 and the bottom surface of the semiconductor element 2 is exposed. An external electrode 3b is disposed outside the die pad 4b. Reinforcing pads 9b are disposed at the four corners of the semiconductor device 1A.

外部電極3b、ダイパッド4bおよび補強パッド9bの各上面にはAg層3a,4a,9aが、外部電極3b、ダイパッド4bおよび補強パッド9bの各下面にはAu層3c,4c,9cがそれぞれ形成されている。図1(a)には全てのAu層3c,4cおよび9cが示されている。以下、本発明の実施形態による半導体装置1Aを詳細に説明する。   Ag layers 3a, 4a and 9a are formed on the upper surfaces of the external electrode 3b, die pad 4b and reinforcing pad 9b, and Au layers 3c, 4c and 9c are formed on the lower surfaces of the external electrode 3b, die pad 4b and reinforcing pad 9b, respectively. ing. FIG. 1A shows all the Au layers 3c, 4c and 9c. Hereinafter, a semiconductor device 1A according to an embodiment of the present invention will be described in detail.

外部電極3bおよびダイパッド4bはニッケル電鋳(Ni電鋳)から成り、半導体装置1Aの底面に設けられている。したがって、この半導体装置1Aはいわゆるリードフレームレスタイプである。ここで、外部電極3bとは、半導体素子2と半導体装置1Aを実装する回路基板との電気的接続をとるための電極である。ダイパッド4bは半導体素子2を搭載するための電極である。外部電極3bおよびダイパッド4bの上面側には、Ag層3a,4aが形成される。外部電極3bの上面側のAg層3aはワイヤボインディングの接続性改善のために設けられたものであり、ダイパッド4bの上面側のAg層4aは、外部電極3bの上面側のAg層3aを形成する際に一緒に設けられたものである。一方、外部電極3bおよびダイパッド4bの下面側には、Au層3c,4cが形成される。Au層は半田濡れ性改善のために設けられる。   The external electrode 3b and the die pad 4b are made of nickel electroforming (Ni electroforming), and are provided on the bottom surface of the semiconductor device 1A. Therefore, this semiconductor device 1A is a so-called lead frameless type. Here, the external electrode 3b is an electrode for establishing electrical connection between the semiconductor element 2 and a circuit board on which the semiconductor device 1A is mounted. The die pad 4 b is an electrode for mounting the semiconductor element 2. Ag layers 3a and 4a are formed on the upper surfaces of the external electrode 3b and the die pad 4b. The Ag layer 3a on the upper surface side of the external electrode 3b is provided for improving the connectivity of wire bonding, and the Ag layer 4a on the upper surface side of the die pad 4b is replaced with the Ag layer 3a on the upper surface side of the external electrode 3b. It was provided together when forming. On the other hand, Au layers 3c and 4c are formed on the lower surfaces of the external electrode 3b and the die pad 4b. The Au layer is provided to improve solder wettability.

半導体装置1Aの底面には、その四隅に、外部電極3bのほかに補強パッド9bが設けられている。補強パッド9bは、回路基板に対する半導体装置1Aの接着強度を上げるための電極であり、補強パッド9bは回路基板と半田を介して接続する。外部電極3bと同様に、補強パッド9bの上面側にはAg層9aが形成され、下面側にはAu層9cが形成されている。したがって、半導体装置1Aの底面ではAu層9cが露出している。   On the bottom surface of the semiconductor device 1A, reinforcing pads 9b are provided at the four corners in addition to the external electrodes 3b. The reinforcing pad 9b is an electrode for increasing the adhesive strength of the semiconductor device 1A to the circuit board, and the reinforcing pad 9b is connected to the circuit board via solder. Similar to the external electrode 3b, an Ag layer 9a is formed on the upper surface side of the reinforcing pad 9b, and an Au layer 9c is formed on the lower surface side. Therefore, the Au layer 9c is exposed on the bottom surface of the semiconductor device 1A.

図1(b)に示すように、半導体素子2と外部電極3bとはAuのワイヤ7によって電気的に接続している。半導体素子2、ワイヤ7、外部電極3b、ダイパッド4bおよび補強パッド9bは、エポキシ樹脂などからなる樹脂8によって封止される。このような半導体装置1Aは、その底面を半田ペーストが塗布された回路基板上に配設し、リフロー炉で半田をリフローすることにより、Au層3c,4c,9cを介して半田により回路基板上に接合して実装される。   As shown in FIG. 1B, the semiconductor element 2 and the external electrode 3b are electrically connected by an Au wire 7. The semiconductor element 2, the wire 7, the external electrode 3b, the die pad 4b, and the reinforcing pad 9b are sealed with a resin 8 made of an epoxy resin or the like. Such a semiconductor device 1A has a bottom surface disposed on a circuit board coated with a solder paste, and reflows the solder in a reflow furnace, so that the solder is passed through the Au layers 3c, 4c and 9c by solder. It is mounted and bonded to.

次に、上述した半導体装置1Aの製造方法について、図2〜図4を参照して説明する。この製造方法は、金属層形成工程と、半導体素子実装工程と、樹脂封止工程と、金属板剥離工程と、分割工程とを含み、1つの金属板上に複数の半導体装置1Aを同時に作製する。以下、各工程を工程順に説明する。   Next, a method for manufacturing the semiconductor device 1A described above will be described with reference to FIGS. This manufacturing method includes a metal layer forming step, a semiconductor element mounting step, a resin sealing step, a metal plate peeling step, and a dividing step, and simultaneously produces a plurality of semiconductor devices 1A on one metal plate. . Hereinafter, each process will be described in the order of processes.

(イ)金属層形成工程
金属層形成工程について、図2(a)〜(d)を参照して説明する。
図2(a)に示すように、可撓性を有する金属板21の両面にレジスト22を塗布またはラミネートする。金属板21は、厚さ約0.1mmの平板状のJIS規格のSUSステンレス鋼板またはCu板などの金属薄板からなる。次に、アクリルフィルムベースのパターンマスクフィルムを密着させ、紫外線により露光する。そして、現像し、図2(b)に示すように、外部電極3b、ダイパッド4bおよび補強パッド9bを形成する部分のレジスト22を除去する。ここで、ダイパッド4bの開口部6が形成される部分のレジスト22−6は残される。金属板21の一方の面には金属層を形成しないので、レジスト22によって全面が覆われる。
(A) Metal layer formation process
The metal layer forming step will be described with reference to FIGS.
As shown in FIG. 2A, a resist 22 is applied or laminated on both surfaces of a flexible metal plate 21. The metal plate 21 is made of a thin metal plate such as a flat JIS standard SUS stainless steel plate or Cu plate having a thickness of about 0.1 mm. Next, an acrylic film-based pattern mask film is brought into intimate contact and exposed to ultraviolet rays. Then, development is performed, and as shown in FIG. 2B, a portion of the resist 22 where the external electrode 3b, the die pad 4b, and the reinforcing pad 9b are to be formed is removed. Here, the resist 22-6 in the portion where the opening 6 of the die pad 4b is formed is left. Since no metal layer is formed on one surface of the metal plate 21, the entire surface is covered with the resist 22.

次に、金属板21をAuメッキ溶液に浸漬して金属板21に電力を供給して電鋳を行い、金属板21上にAu層23を形成する。次にAu層23を形成した金属板21をNiめっき溶液に浸漬して電鋳を行い、Ni層24を形成する。さらに、Agめっき溶液に金属板21を浸漬して金属板21に電力を供給することにより、Ni層24の上にAg層25を形成する。このようにして、図2(c)に示すように、金属板21に金属層として、パターニングされたAu層23とNi層24とAg層25とを形成する。金属層を形成後、図2(d)に示すように、レジスト22を金属板21から剥離する。   Next, the metal plate 21 is immersed in an Au plating solution, electric power is supplied to the metal plate 21 and electroforming is performed, and the Au layer 23 is formed on the metal plate 21. Next, the metal plate 21 on which the Au layer 23 is formed is immersed in a Ni plating solution and electroformed to form the Ni layer 24. Furthermore, the Ag layer 25 is formed on the Ni layer 24 by immersing the metal plate 21 in the Ag plating solution and supplying power to the metal plate 21. In this way, as shown in FIG. 2C, the patterned Au layer 23, Ni layer 24, and Ag layer 25 are formed on the metal plate 21 as metal layers. After forming the metal layer, the resist 22 is peeled from the metal plate 21 as shown in FIG.

(ロ)半導体素子実装工程
半導体素子実装工程について、図2(e),(f)を参照して説明する。
図2(e)に示すように、ダイパッド4bのAg層4aに相当するAg層25にダイボンディング材5を塗布する。ダイボンディング材5はAgペーストから成る。そして図2(f)に示すように、ダイパッド4bの開口部6を塞ぐように半導体素子2を搭載する。図2では省略しているが、金属板21には、パターニングされたNi層24が複数並列配置されており、それぞれのパターンニングされたNi層24上に半導体素子2が隣接して搭載される。半導体素子2を搭載した後、ダイボンディング材5を加熱処理する。そして、ワイヤボンディングによって、半導体素子2の周縁領域に設けられた端子と、外部電極3bのAg層3aに相当するAg層25とをワイヤ7によって接続する。
(B) Semiconductor element mounting process The semiconductor element mounting process will be described with reference to FIGS.
As shown in FIG. 2E, the die bonding material 5 is applied to the Ag layer 25 corresponding to the Ag layer 4a of the die pad 4b. The die bonding material 5 is made of Ag paste. Then, as shown in FIG. 2F, the semiconductor element 2 is mounted so as to close the opening 6 of the die pad 4b. Although omitted in FIG. 2, a plurality of patterned Ni layers 24 are arranged in parallel on the metal plate 21, and the semiconductor element 2 is mounted adjacently on each patterned Ni layer 24. . After mounting the semiconductor element 2, the die bonding material 5 is heated. Then, the terminals provided in the peripheral region of the semiconductor element 2 and the Ag layer 25 corresponding to the Ag layer 3a of the external electrode 3b are connected by the wire 7 by wire bonding.

(ハ)樹脂封止工程
樹脂封止工程について、図3(a)および図4を参照して説明する。
樹脂封止工程では、図3(a)に示すように半導体素子2、ワイヤ7、Au層23、Ni層24およびAg層25を樹脂8によって封止する。樹脂封止は次のようにして行う。図4に示すように、金属板21の半導体素子2が実装されている面に金型41を被せる。そして、樹脂8を金型41内に注入し、金属板21に実装された複数の半導体素子2などを一括に封止する。この樹脂封止工程では、金型41は上型の役割を果たし、金属板21は下型の役割を果たす。開口部6は半導体素子2によって塞がれているので、開口部6には樹脂8は浸入しない。
(C) Resin sealing process The resin sealing process is demonstrated with reference to Fig.3 (a) and FIG.
In the resin sealing step, the semiconductor element 2, the wire 7, the Au layer 23, the Ni layer 24, and the Ag layer 25 are sealed with the resin 8 as shown in FIG. Resin sealing is performed as follows. As shown in FIG. 4, a mold 41 is placed on the surface of the metal plate 21 on which the semiconductor element 2 is mounted. Then, the resin 8 is injected into the mold 41, and the plurality of semiconductor elements 2 mounted on the metal plate 21 are sealed together. In this resin sealing step, the mold 41 serves as an upper mold, and the metal plate 21 serves as a lower mold. Since the opening 6 is blocked by the semiconductor element 2, the resin 8 does not enter the opening 6.

(ニ)金属板剥離工程
金属板剥離工程について、図3(b)を参照して説明する。
樹脂8による封止が完了した後は、図3(b)に示すように、Ni層24や樹脂8から金属板21を剥離する。金属板21は可撓性を有するので、容易に剥離することができる。開口部6には、樹脂8は侵入しないので、金属板21を剥離すると、半導体素子2の底面のAu層23が露出する。この金属板21を剥離したものを以下、樹脂封止体30Aと呼ぶ。
(D) Metal plate peeling process A metal plate peeling process is demonstrated with reference to FIG.3 (b).
After the sealing with the resin 8 is completed, the metal plate 21 is peeled from the Ni layer 24 and the resin 8 as shown in FIG. Since the metal plate 21 has flexibility, it can be easily peeled off. Since the resin 8 does not enter the opening 6, the Au layer 23 on the bottom surface of the semiconductor element 2 is exposed when the metal plate 21 is peeled off. Hereinafter, the metal plate 21 is peeled off and is referred to as a resin sealing body 30A.

(ホ)分割工程
分割工程について、図3(b),(c)を参照して説明する。
図3(b)の点線34に沿って、ダイヤモンドブレード・ダイシング法で樹脂封止体30Aをダイシングする。そして、図3(c)に示すように、一つの樹脂封止体30Aが分割され、半導体装置1Aが完成する。
(E) Division Step The division step will be described with reference to FIGS. 3 (b) and 3 (c).
The resin sealing body 30A is diced by a diamond blade dicing method along the dotted line 34 in FIG. And as shown in FIG.3 (c), one resin sealing body 30A is divided | segmented and the semiconductor device 1A is completed.

以上の本発明の第1の実施形態による半導体装置1Aは次のような作用効果を奏する。
(1)半導体素子2が搭載されるダイパッド4bに開口部6を設け、リフロー時の不良発生を防止するための貫通孔とした。したがって、貫通孔を形成するために、新たに別の工程、たとえば、機械加工やレーザ加工の工程が必要ない。
The semiconductor device 1A according to the first embodiment of the present invention described above has the following operational effects.
(1) An opening 6 is provided in the die pad 4b on which the semiconductor element 2 is mounted to form a through hole for preventing a defect from occurring during reflow. Therefore, in order to form the through hole, another new process, for example, a machining process or a laser machining process is not necessary.

(2)電鋳によってダイパッド4bを形成するようにしたので、電鋳作製時のマスクを変更してダイパッド4bの開口部6の大きさや形状を自由に変えることができる。したがって、はんだリフロー時のパッケージクラック、剥離、ふくれ発生などの不良発生を効果的に防止するように開口部6の形状を適宜選択することができる。ダイパッド4bによる半導体素子2の放熱性の観点から見ると、開口部6の面積は小さければ小さいほどよい。 (2) Since the die pad 4b is formed by electroforming, the size and shape of the opening 6 of the die pad 4b can be freely changed by changing the mask at the time of electroforming. Therefore, the shape of the opening 6 can be appropriately selected so as to effectively prevent the occurrence of defects such as package cracking, peeling, and blistering during solder reflow. From the viewpoint of heat dissipation of the semiconductor element 2 by the die pad 4b, the smaller the area of the opening 6, the better.

(3)ダイボンディング材5にAgペーストを使用するので、半導体素子2から発生する熱をダイパッド4bに速やかに伝導させることができる。 (3) Since Ag paste is used for the die bonding material 5, heat generated from the semiconductor element 2 can be quickly conducted to the die pad 4b.

(4)開口部6を塞ぐように半導体素子2をダイパッド4bに搭載するようにしたので、樹脂封止工程で樹脂8が開口部6に侵入しない。したがって、樹脂8が開口部6に侵入しないようにする部材を別途設ける必要がない。 (4) Since the semiconductor element 2 is mounted on the die pad 4b so as to close the opening 6, the resin 8 does not enter the opening 6 in the resin sealing step. Therefore, it is not necessary to separately provide a member that prevents the resin 8 from entering the opening 6.

以上の実施の形態の半導体装置1Aを次のように変形することができる。
(1)半導体装置1Aにおけるダイパッド4bの開口部6の形状は実施形態に限定されない。たとえば、図5に示すように半導体装置1Bにおけるダイパッド4bの開口部6の形状を略十字型にしてもよい。開口部6の形状を略十字型にし、図6に示すようにダイボンディング材5を4箇所塗布することによって、開口部6の形状を円形にした場合に比べて、ダイボンディング材5が開口部6にはみ出にくくすることができる。
The semiconductor device 1A of the above embodiment can be modified as follows.
(1) The shape of the opening 6 of the die pad 4b in the semiconductor device 1A is not limited to the embodiment. For example, as shown in FIG. 5, the shape of the opening 6 of the die pad 4b in the semiconductor device 1B may be a substantially cross shape. Compared to the case where the shape of the opening 6 is made circular by making the shape of the opening 6 substantially cross-shaped and applying the die bonding material 5 at four locations as shown in FIG. 6 can be made difficult to protrude.

(2)半導体装置1Aにおけるダイパッド4bの開口部6の数は実施形態のように1に限定されない。たとえば、図7に示すように半導体装置1Cにおけるダイパッド4bの開口部6の数を4つにしてもよい。 (2) The number of openings 6 of the die pad 4b in the semiconductor device 1A is not limited to 1 as in the embodiment. For example, as shown in FIG. 7, the number of openings 6 of the die pad 4b in the semiconductor device 1C may be four.

(3)外部電極3bはNiより形成したが、導電性を有する金属であればNiに限定されない。たとえば、電鋳で形成したCu電極やNi・Co合金電極であってもよい。 (3) Although the external electrode 3b is made of Ni, it is not limited to Ni as long as it is a conductive metal. For example, a Cu electrode or a Ni / Co alloy electrode formed by electroforming may be used.

(4)ワイヤ接続用の金属層や半田接続用の金属層をめっき法によって形成したが、真空蒸着法やCVD法によって形成してもよい。 (4) Although the metal layer for wire connection and the metal layer for solder connection are formed by plating, they may be formed by vacuum deposition or CVD.

(5)外部電極3bの上面側にAg層3aを形成しているが、ワイヤ7と外部電極3bとを接続できるようにするためのものであれば、Ag層に限定されない。たとえば、Au層を形成してもよい。また、ワイヤ7を直接外部電極3bに接続できる場合は、Ag層を形成しなくてもよい。 (5) Although the Ag layer 3a is formed on the upper surface side of the external electrode 3b, the Ag layer 3a is not limited to the Ag layer as long as the wire 7 and the external electrode 3b can be connected. For example, an Au layer may be formed. Further, when the wire 7 can be directly connected to the external electrode 3b, the Ag layer may not be formed.

(6)金属層形成工程においてAu層23を形成したが、外部電極4bと半田とを接合するための金属層であればAu層23に限定されず、たとえば、Sn層、Sn−Ag層、Sn−Cu層、Sn−Bi層またはSn−Pb層を形成してもよい。また、直接外部電極4bと半田とを接合する場合は、Ni層24の下面側に金属層を設けなくてもよい。 (6) Although the Au layer 23 is formed in the metal layer forming step, the Au layer 23 is not limited to the Au layer 23 as long as it is a metal layer for joining the external electrode 4b and the solder. For example, a Sn layer, a Sn—Ag layer, A Sn—Cu layer, a Sn—Bi layer, or a Sn—Pb layer may be formed. Further, when the external electrode 4b and the solder are directly joined, the metal layer may not be provided on the lower surface side of the Ni layer 24.

(7)以上の実施の形態では、可撓性を有する金属板21にNi層24やレジスト22などを形成したが、可撓性を有し、導電性を有する導電性基板であればSUSステンレス鋼板やCu板に限定されない。たとえば、SUSステンレス鋼板やCu板以外の金属薄板を使用してもよいし、導電性樹脂を使用してもよい。また、表面に導電膜を形成した基板を使用してもよい。 (7) In the above embodiment, the Ni layer 24 and the resist 22 are formed on the flexible metal plate 21, but SUS stainless steel can be used as long as it is flexible and conductive. It is not limited to a steel plate or a Cu plate. For example, a thin metal plate other than a SUS stainless steel plate or Cu plate may be used, or a conductive resin may be used. Alternatively, a substrate having a conductive film formed on the surface may be used.

(8)ダイボンディング材5は、はんだリフロー時のパッケージクラック、剥離、ふくれ発生などの不良発生を防止する効果を妨げるほど開口部6を塞がなければ、開口部6よりはみ出てもよい。 (8) The die bonding material 5 may protrude beyond the opening 6 as long as the opening 6 is not blocked so as to hinder the effect of preventing defects such as package cracking, peeling, and blistering during solder reflow.

(9)ダイボンディング材5としてAgペーストを使用したが、Agペーストのほかに絶縁ペーストを使用してもよい。 (9) Although the Ag paste is used as the die bonding material 5, an insulating paste may be used in addition to the Ag paste.

(10)ダイボンディング材5としてAgペーストを使用したが、Agペーストに代えてDAF(ダイアタッチフィルム)などの接着フィルムを使用してもよい。ダイボンディング材5として接着フィルム5Aを使用したときの半導体装置1Dを図8に示す。図8(a)は半導体装置1Dの裏面図であり、図8(b)は図1(a)のC−C’線断面図である。この場合、接着フィルム5Aはダイパッド4bの開口部6を塞ぐように貼り付けられ、その上に半導体素子2が接着される。したがって、図8(b)に示すように開口部6より半導体素子2の底面が露出せず、接着フィルム5Aが露出することになる。しかし、接着フィルム5Aを通して水分などが開放されるので、はんだリフロー時のパッケージクラック、剥離、ふくれ発生などの不良発生を防止することができる。 (10) Although the Ag paste is used as the die bonding material 5, an adhesive film such as DAF (die attach film) may be used instead of the Ag paste. A semiconductor device 1D when an adhesive film 5A is used as the die bonding material 5 is shown in FIG. FIG. 8A is a back view of the semiconductor device 1D, and FIG. 8B is a cross-sectional view taken along line C-C ′ of FIG. In this case, the adhesive film 5A is attached so as to close the opening 6 of the die pad 4b, and the semiconductor element 2 is bonded thereon. Therefore, as shown in FIG. 8B, the bottom surface of the semiconductor element 2 is not exposed from the opening 6, and the adhesive film 5A is exposed. However, since moisture and the like are released through the adhesive film 5A, it is possible to prevent occurrence of defects such as package cracking, peeling, and blistering during solder reflow.

本発明は、その特徴的構成を有していれば、以上説明した実施の形態になんら限定されない。   The present invention is not limited to the embodiment described above as long as it has the characteristic configuration.

本発明の実施形態の半導体装置の構造を示す図である。It is a figure which shows the structure of the semiconductor device of embodiment of this invention. 本発明の実施形態の半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device of embodiment of this invention. 本発明の実施形態の半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device of embodiment of this invention. 本発明の実施形態の半導体装置の製造方法における樹脂の封止を説明するための図である。It is a figure for demonstrating sealing of the resin in the manufacturing method of the semiconductor device of embodiment of this invention. 開口部の形状を十字型にした半導体装置を説明するための図である。It is a figure for demonstrating the semiconductor device which made the shape of the opening part the cross shape. 開口部の形状を十字型にした半導体装置のダイボンディング材の塗布を説明するための図である。It is a figure for demonstrating application | coating of the die bonding material of the semiconductor device which made the shape of the opening part the cross shape. 複数の開口部を備えた半導体装置を説明するための図である。It is a figure for demonstrating the semiconductor device provided with the several opening part. ダイボンディング材として接着フィルムを使用したときの半導体装置の構造を示す図である。It is a figure which shows the structure of a semiconductor device when an adhesive film is used as a die-bonding material.

符号の説明Explanation of symbols

1A,1B,1C,1D 半導体装置
2 半導体素子
3a,4a,9a,25 Ag層
3b 外部電極
3c,4c,9c,23 Au層
4b ダイパッド
5 ダイボンディング材
5A 接着フィルム
6 開口部
7 ワイヤ
8 樹脂
9b 補強パッド
21 金属板
22 レジスト
24 Ni層
30A 樹脂封止体
41 金型
1A, 1B, 1C, 1D Semiconductor device 2 Semiconductor elements 3a, 4a, 9a, 25 Ag layer 3b External electrodes 3c, 4c, 9c, 23 Au layer 4b Die pad 5 Die bonding material 5A Adhesive film 6 Opening 7 Wire 8 Resin 9b Reinforcing pad 21 Metal plate 22 Resist 24 Ni layer 30A Resin encapsulant 41 Mold

Claims (6)

半導体素子と、
開口部を有し、前記開口部を塞ぐように前記半導体素子を搭載するダイパッドと、
前記半導体素子とワイヤにより電気的に接続している外部電極とを備え、
前記ダイパッドおよび前記外部電極は電鋳によって形成され、
前記ダイパッドと前記外部電極が底面において露出するように前記半導体素子と前記ダイパッドと前記ワイヤと前記外部電極とを樹脂により封止し、前記半導体素子が前記開口部において露出していることを特徴とする半導体装置。
A semiconductor element;
A die pad having an opening and mounting the semiconductor element so as to close the opening;
An external electrode electrically connected to the semiconductor element by a wire;
The die pad and the external electrode are formed by electroforming,
The semiconductor element, the die pad, the wire, and the external electrode are sealed with a resin so that the die pad and the external electrode are exposed at the bottom surface, and the semiconductor element is exposed at the opening. Semiconductor device.
請求項1に記載の半導体装置において、
前記半導体素子を前記ダイパッドにAgペースト、または絶縁ペーストを使用して固定することを特徴とする半導体装置。
The semiconductor device according to claim 1,
A semiconductor device, wherein the semiconductor element is fixed to the die pad using Ag paste or insulating paste.
請求項2に記載の半導体装置において、
前記開口部の形状は、略十字型であることを特徴とする半導体装置。
The semiconductor device according to claim 2,
The semiconductor device according to claim 1, wherein the opening has a substantially cross shape.
半導体素子と、
開口部を有し、前記半導体素子を搭載するダイパッドと、
前記開口部を塞ぐように前記ダイパッドに貼付され、前記ダイパッドに半導体素子を貼着する接着フィルムと、
前記半導体素子とワイヤにより電気的に接続している外部電極とを備え、
前記ダイパッドおよび前記外部電極は電鋳によって形成され、
前記ダイパッドと前記外部電極が底面において露出するように前記半導体素子と前記ダイパッドと前記ワイヤと前記外部電極とを樹脂により封止し、前記接着フィルムが前記開口部において露出していることを特徴とする半導体装置。
A semiconductor element;
A die pad having an opening and mounting the semiconductor element;
An adhesive film that is affixed to the die pad so as to close the opening, and that adheres a semiconductor element to the die pad;
An external electrode electrically connected to the semiconductor element by a wire;
The die pad and the external electrode are formed by electroforming,
The semiconductor element, the die pad, the wire, and the external electrode are sealed with resin so that the die pad and the external electrode are exposed at the bottom surface, and the adhesive film is exposed at the opening. Semiconductor device.
開口部を有するダイパッドと、前記ダイパッドの外側に配設される外部電極とからなる一組の金属層を可撓性シートに複数隣接配置して形成する金属層形成工程と、
前記開口部を塞ぐように、前記ダイパッドに半導体素子を搭載し、前記半導体素子と前記外部電極とを電気的に接続する半導体素子実装工程と、
前記金属層および前記半導体素子を樹脂封止する樹脂封止工程と、
前記可撓性シートを剥離して樹脂封止体を得る剥離工程と、
前記樹脂封止体を切断して、個々の半導体装置に分割する分割工程とを備えることを特徴とする半導体装置の製造方法。
A metal layer forming step in which a plurality of metal layers each including a die pad having an opening and an external electrode disposed outside the die pad are disposed adjacent to the flexible sheet; and
Mounting a semiconductor element on the die pad so as to close the opening, and electrically connecting the semiconductor element and the external electrode; and
A resin sealing step of resin sealing the metal layer and the semiconductor element;
A peeling step of peeling the flexible sheet to obtain a resin sealing body;
A method of manufacturing a semiconductor device, comprising: a step of cutting the resin sealing body to divide into individual semiconductor devices.
可撓性を有する金属板と、
前記金属板上に電鋳によって形成され、開口部を有し、半導体素子が搭載されるダイパッドと、
前記金属板上に電鋳によって形成され、前記半導体素子とワイヤにより電気的に接続される外部電極とを備えることを特徴とする半導体装置作製用シート。
A flexible metal plate;
A die pad formed by electroforming on the metal plate, having an opening, and on which a semiconductor element is mounted;
A sheet for manufacturing a semiconductor device, comprising: an external electrode formed by electroforming on the metal plate and electrically connected to the semiconductor element by a wire.
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JP2002016181A (en) * 2000-04-25 2002-01-18 Torex Semiconductor Ltd Semiconductor device, manufacturing method thereof, and electrodeposition frame
JP2004063890A (en) * 2002-07-30 2004-02-26 Fujitsu Ltd Method for manufacturing semiconductor device
JP2004228167A (en) * 2003-01-20 2004-08-12 Sanyo Electric Co Ltd Lead frame and semiconductor device using it

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023058487A1 (en) * 2021-10-04 2023-04-13 ローム株式会社 Electronic device

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