JP2009231347A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
JP2009231347A
JP2009231347A JP2008071652A JP2008071652A JP2009231347A JP 2009231347 A JP2009231347 A JP 2009231347A JP 2008071652 A JP2008071652 A JP 2008071652A JP 2008071652 A JP2008071652 A JP 2008071652A JP 2009231347 A JP2009231347 A JP 2009231347A
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electrode layer
wire
lead frame
semiconductor device
sealing member
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Hiroshi Kimura
浩 木村
Osamu Tokuda
修 徳田
Hiroyuki Ishii
弘幸 石井
Noriyuki Nakamura
教之 中村
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Phenitec Semiconductor Corp
Torex Semiconductor Ltd
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Phenitec Semiconductor Corp
Torex Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the semiconductor device for preventing product defect such as fall of wires. <P>SOLUTION: A resist layer 7 is formed on the backside of a lead frame 2. Next, a semiconductor chip 3 is mounted on the surface of the lead frame 2 and the semiconductor chip 3 and the lead frame 2 are electrically connected with a wire 4. Thereafter, a sealing member 6 is formed to expose the backside of the resist layer 7 and cover the side surface of the resist layer. Moreover, after the resist layer 7 is removed, a plating layer 5 is formed on the backside of the lead frame 2. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は、半導体装置及び半導体装置の製造方法に係り、特に、第１の電極層と、前記第１の電極層の表面上に搭載されたチップ部品と、前記チップ部品の電極及び前記第１の電極層の表面間にワイヤボンダされた前記チップ部品及び前記第１の電極層を電気的に接続するワイヤと、前記第１の電極層、前記チップ部品、及び、前記ワイヤ、を封止する封止部材と、を備えた半導体装置及びその製造方法に関するものである。   The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and in particular, a first electrode layer, a chip component mounted on the surface of the first electrode layer, an electrode of the chip component, and the first A wire for electrically connecting the chip component and the first electrode layer wire-bonded between the surfaces of the electrode layer, and a seal for sealing the first electrode layer, the chip component, and the wire. The present invention relates to a semiconductor device including a stop member and a method for manufacturing the same.

従来より、半導体装置表面に設けた電極をプリント基板に直接半田付けする表面実装技術がある。この技術を用いることにより、ピン挿入方式で必要だったスルーホールが必要なくなり、部品の小型化、実装密度の増大、基板の小型化などが可能となった。   Conventionally, there is a surface mounting technique in which an electrode provided on the surface of a semiconductor device is directly soldered to a printed circuit board. By using this technology, the through-holes required for the pin insertion method are no longer necessary, and it is possible to reduce the size of components, increase the mounting density, and reduce the size of the substrate.

このような、表面実装型の半導体装置の製造方法として、例えば、図３に示されたようなものが提案されている（特許文献１）。まず、同図（Ａ）に示すように、板状のリードフレーム２（第１の電極層）の裏面に粘着材９によってポリイミドシート８を貼り付ける。その後、同図（Ｂ）に示すように、リードフレーム２のダイパッド２Ａの表面に半導体チップ３（チップ部品）を接着して搭載する。そして、半導体チップ３の電極パッド３Ａとリードフレーム２のボンディングパッド２Ｂとの間をワイヤ４によってワイヤボンダして接続する。   As a method for manufacturing such a surface-mount type semiconductor device, for example, a method as shown in FIG. 3 has been proposed (Patent Document 1). First, as shown in FIG. 2A, a polyimide sheet 8 is attached to the back surface of the plate-like lead frame 2 (first electrode layer) with an adhesive material 9. Thereafter, as shown in FIG. 5B, the semiconductor chip 3 (chip component) is bonded and mounted on the surface of the die pad 2A of the lead frame 2. The electrode pads 3 </ b> A of the semiconductor chip 3 and the bonding pads 2 </ b> B of the lead frame 2 are connected by wire bonding with wires 4.

次に、同図（Ｃ）に示すように、ワイヤ４で配線がなされた半導体チップ３を封止部材６で封止する。その後、同図（Ｄ）に示すように、ポリイミドシート８を剥がす。これにより、封止部材６の裏面からリードフレーム２の裏面が露出して半導体装置１が完成する。このように、ポリイミドシート８を設けることにより、封止部材６の形成時にリードフレーム２の裏面に封止部材６が付着して接続不良となることを防ぐ。   Next, as shown in FIG. 3C, the semiconductor chip 3 wired with the wires 4 is sealed with a sealing member 6. Thereafter, the polyimide sheet 8 is peeled off as shown in FIG. Thereby, the back surface of the lead frame 2 is exposed from the back surface of the sealing member 6 to complete the semiconductor device 1. Thus, by providing the polyimide sheet 8, the sealing member 6 is prevented from adhering to the back surface of the lead frame 2 when the sealing member 6 is formed, resulting in poor connection.

しかしながら、上述した従来の半導体装置の製造方法では、リードフレーム２の裏側に粘着材９でポリイミドシート８を貼り付けた状態でワイヤボンダを行っている。このため、ワイヤボンダ時に発生する熱により粘着材９が溶けてへこむ。その後、冷やされてへこんだ部分の粘着材９が盛り上がるとワイヤ４が倒れてしまう、という問題があった。そこで、例えばワイヤボンダを行った後にポリイミドシート８を貼り付けて封止することが考えられる。しかしながら、ワイヤ４がつぶれないようにリードフレーム２にポリイミドシート８を貼り付けることは非常に困難であった。   However, in the above-described conventional method for manufacturing a semiconductor device, the wire bonder is performed in a state where the polyimide sheet 8 is adhered to the back side of the lead frame 2 with the adhesive material 9. For this reason, the adhesive material 9 is melted and dented by the heat generated during the wire bonding. After that, there was a problem that the wire 4 would fall when the adhesive material 9 in the depressed portion was cooled. Therefore, for example, it is conceivable that the polyimide sheet 8 is attached and sealed after wire bonding. However, it is very difficult to attach the polyimide sheet 8 to the lead frame 2 so that the wire 4 is not crushed.

また、従来の半導体の製造方法では、リードフレーム２の裏側にポリイミドシート８を貼り付けている。このポリイミドシート８をシワなく貼り付けるのは非常に難しい。このポリイミドシート８にシワがよるとそのシワに封止部材６が入り込んでしまい、リードフレーム２の裏側に封止部材６が付着して接続不良となってしまう、という問題があった。
特公２００２−５１９８４８号公報 In the conventional semiconductor manufacturing method, the polyimide sheet 8 is attached to the back side of the lead frame 2. It is very difficult to apply the polyimide sheet 8 without wrinkles. If the polyimide sheet 8 is wrinkled, the sealing member 6 enters the wrinkle, and there is a problem that the sealing member 6 adheres to the back side of the lead frame 2 to cause poor connection.
Japanese Patent Publication No. 2002-51848

そこで、本発明は、上記のような問題点に着目し、ワイヤが倒れるなどの製品不良を防止した半導体装置及び半導体装置の製造方法を提供することを課題とする。   Accordingly, the present invention focuses on the above-described problems, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device in which product defects such as a wire falling are prevented.

上述した問題を解決するためになされた請求項１に記載した本発明は、第１の電極層と、前記第１の電極層の表面上に搭載されたチップ部品と、前記チップ部品の電極及び前記第１の電極層の表面間にワイヤボンダされた前記チップ部品及び前記第１の電極層を電気的に接続するワイヤと、前記第１の電極層、前記チップ部品、及び、前記ワイヤ、を封止する封止部材と、を備えた半導体装置において、前記第１の電極層の裏面上に設けられた前記第１の電極層とは別体に設けられた第２の電極層を備え、そして、前記封止部材が、前記第２の電極層の裏面を露出し、かつ、前記第２の電極層の側面を覆うように、設けられていることを特徴とする半導体装置に存する。   In order to solve the above-described problem, the present invention described in claim 1 includes a first electrode layer, a chip component mounted on a surface of the first electrode layer, an electrode of the chip component, and The chip component wire bonded between the surfaces of the first electrode layer and a wire for electrically connecting the first electrode layer, and the first electrode layer, the chip component, and the wire are sealed. A sealing member that stops, and a second electrode layer provided separately from the first electrode layer provided on the back surface of the first electrode layer, and In the semiconductor device, the sealing member is provided so as to expose a back surface of the second electrode layer and to cover a side surface of the second electrode layer.

請求項２記載の発明は、前記第２の電極層が、前記第１の電極層の周縁部の少なくとも一部を除くように前記第１の電極層の裏面上に設けられていることを特徴とする請求項１に記載の半導体装置に存する。   The invention according to claim 2 is characterized in that the second electrode layer is provided on the back surface of the first electrode layer so as to exclude at least a part of a peripheral portion of the first electrode layer. A semiconductor device according to claim 1.

請求項３記載の発明は、第１の電極層と、前記第１の電極層の表面上に搭載されたチップ部品と、前記チップ部品の電極及び前記第１の電極層の表面間にワイヤボンダされた前記チップ部品及び前記第１の電極層を電気的に接続するワイヤと、前記第１の電極層、前記チップ部品、及び、前記ワイヤ、を封止する封止部材と、を備えた半導体装置の製造方法であって、前記第１の電極層の裏面上にレジストを形成する工程と、前記第１の電極層の表面に前記チップ部材を搭載して前記ワイヤによって前記チップ部材及び前記第１の電極層を電気的に接続する工程と、前記レジストの裏面が露出され、かつ、前記レジストの側面が覆われるように、前記封止部材を形成する工程と、前記レジストを取り除く工程と、前記第１の電極層の裏面に第２の電極層を形成する工程と、を順次行うことを特徴とする半導体装置の製造方法に存する。   According to a third aspect of the present invention, a wire bonder is provided between the first electrode layer, the chip component mounted on the surface of the first electrode layer, and the electrode of the chip component and the surface of the first electrode layer. A semiconductor device comprising: a wire that electrically connects the chip component and the first electrode layer; and a sealing member that seals the first electrode layer, the chip component, and the wire. And a step of forming a resist on the back surface of the first electrode layer, mounting the chip member on the surface of the first electrode layer, and using the wire to insert the chip member and the first electrode. Electrically connecting the electrode layers, forming the sealing member so that a back surface of the resist is exposed and side surfaces of the resist are covered, removing the resist, On the back of the first electrode layer It lies forming an electrode layer that are sequentially performing the method of manufacturing a semiconductor device according to claim.

以上説明したように請求項１記載の発明によれば、第１の電極層の裏面上に、第１の電極層とは別体で第２の電極層が設けられている。封止部材が、第２の電極層の裏面を露出し、かつ、第２の電極層の側面を覆うように、設けられている。この構造によれば、第１の電極層の裏面にレジストを設けた後にワイヤボンダ、封止を行って、その後レジストを除いて第２の電極層を形成するように製造することができる。これにより、粘着材でポリイミドシートを貼り付ける必要がなく、ワイヤが倒れたり、第２の電極層の裏側に封止部材が回るなどの製品不良を防止することができる。   As described above, according to the first aspect of the present invention, the second electrode layer is provided separately from the first electrode layer on the back surface of the first electrode layer. A sealing member is provided so as to expose the back surface of the second electrode layer and to cover the side surface of the second electrode layer. According to this structure, a resist can be provided on the back surface of the first electrode layer, then wire bonder and sealing can be performed, and then the resist can be removed to form the second electrode layer. Thereby, it is not necessary to stick a polyimide sheet with an adhesive material, and it is possible to prevent product defects such as a wire falling or a sealing member turning around the back side of the second electrode layer.

請求項２記載の発明によれば、第２の電極層が、第１の電極層の周縁部の少なくとも一部を除くように第１の電極層の裏面上に設けられているので、第２の電極層が除かれた部分に設けられた封止部材により第１の電極層の裏面が支えられるため、封止部材から第１の電極層が抜け落ちにくくなる。   According to the second aspect of the present invention, the second electrode layer is provided on the back surface of the first electrode layer so as to exclude at least a part of the peripheral edge of the first electrode layer. Since the back surface of the first electrode layer is supported by the sealing member provided in the portion where the electrode layer is removed, the first electrode layer is unlikely to fall out of the sealing member.

請求項３記載の発明によれば、第１の電極層の裏面にレジストを設けた後にワイヤボンダ、封止を行って、その後レジストを除いて第２の電極層を形成するように製造することができる。これにより、粘着材でポリイミドシートを貼り付ける必要がなく、ワイヤが倒れたり、第１の電極層と第２の電極層との間や第２の電極層の裏面側に封止部材が回るなどの製品不良を防止することができる。   According to the third aspect of the present invention, it is possible to manufacture so as to form the second electrode layer by removing the resist and then performing wire bonding and sealing after providing the resist on the back surface of the first electrode layer. it can. Thereby, there is no need to stick a polyimide sheet with an adhesive material, the wire falls down, the sealing member rotates between the first electrode layer and the second electrode layer, or on the back side of the second electrode layer, etc. Product defects can be prevented.

以下、本発明の半導体装置及び半導体装置の製造方法について、図面を参照して説明する。図１に示すように、半導体装置１は、導電性のリードフレーム２（第１の電極層）と、半導体チップ（チップ部品）３と、ワイヤ４と、メッキ層５（第２の電極層）と、封止部材６と、を備えている。   Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device of the present invention will be described with reference to the drawings. As shown in FIG. 1, a semiconductor device 1 includes a conductive lead frame 2 (first electrode layer), a semiconductor chip (chip component) 3, a wire 4, and a plating layer 5 (second electrode layer). And a sealing member 6.

上記リードフレーム２は、ニッケル（Ｎｉ）、ニッケル・コバルト（Ｎｉ・Ｃｏ）又は銅（Ｃｕ）合金を形成したＮｉ母材層、Ｎｉ・Ｃｏ母材層又はＣｕ母材層と、これらの表面（図１上側）に形成されたワイヤ４の接続が可能な金（Ａｕ）又は銀（Ａｇ）薄膜層と、から構成される。その厚さは、Ｎｉ、Ｎｉ・Ｃｏ又はＣｕ合金を形成したＮｉ母材層、Ｎｉ・Ｃｏ母材層又はＣｕ母材層の厚さが０．１mm〜０．２mmであり、Ａｕ又はＡｇ薄膜層の厚さが０．０５〜１０μmである。   The lead frame 2 includes a Ni base layer, a Ni / Co base layer or a Cu base layer formed of nickel (Ni), nickel / cobalt (Ni / Co) or a copper (Cu) alloy, and surfaces thereof ( It is comprised from the gold | metal | money (Au) or silver (Ag) thin film layer which can connect the wire 4 formed in FIG. The thickness of the Ni base layer, the Ni / Co base layer or the Cu base layer formed with Ni, Ni.Co or Cu alloy is 0.1 mm to 0.2 mm, and the Au or Ag thin film. The layer thickness is 0.05 to 10 μm.

半導体チップ３は、リードフレーム２のダイパッド２Ａの表面上に搭載されている。半導体チップ３は、その表面に電極パッド３Ａ（電極）が設けられている。ワイヤ４は、例えばＡｕから形成されている。ワイヤ４は、半導体チップ３の電極パッド３Ａ及びリードフレーム２のボンディングパッド２Ｂの表面間にワイヤボンダされていて、半導体チップ３及びボンディングパッド２Ｂを電気的に接続する。   The semiconductor chip 3 is mounted on the surface of the die pad 2 </ b> A of the lead frame 2. The semiconductor chip 3 is provided with electrode pads 3A (electrodes) on the surface thereof. The wire 4 is made of, for example, Au. The wire 4 is wire-bonded between the surface of the electrode pad 3A of the semiconductor chip 3 and the bonding pad 2B of the lead frame 2, and electrically connects the semiconductor chip 3 and the bonding pad 2B.

メッキ層５は、リードフレーム２の裏側にメッキされて設けられている。即ち、メッキ層５は、リードフレーム２とは別体、即ち別の製造工程で形成されている。また、メッキ層５は、リードフレーム２の周縁を除いた中央部に設けられている。   The plated layer 5 is provided by being plated on the back side of the lead frame 2. That is, the plating layer 5 is formed separately from the lead frame 2, that is, in a different manufacturing process. Further, the plating layer 5 is provided in the central portion excluding the peripheral edge of the lead frame 2.

封止部材６は、樹脂などから構成され、上述したリードフレーム２、半導体チップ３、ワイヤ４及びメッキ層５を封止するように設けられている。封止部材６は、板状に形成されていて、その裏面からメッキ層５の裏面が露出するように設けられている。また、封止部材６は、メッキ層５のリードフレーム２側の側面を覆うように設けられている。即ち、封止部材６は、メッキ層５が設けられていないリードフレーム２裏側の全周縁部を覆うように設けられている。   The sealing member 6 is made of resin or the like and is provided so as to seal the lead frame 2, the semiconductor chip 3, the wires 4, and the plating layer 5 described above. The sealing member 6 is formed in a plate shape, and is provided so that the back surface of the plating layer 5 is exposed from the back surface. The sealing member 6 is provided so as to cover the side surface of the plating layer 5 on the lead frame 2 side. That is, the sealing member 6 is provided so as to cover the entire peripheral edge on the back side of the lead frame 2 where the plating layer 5 is not provided.

次に、上述した構成の半導体装置１の製造方法について、図２を参照して説明する。まず、同図（Ａ）に示すように、金属板をエッチング又はスタンピングでリードフレーム２を形成する。その後、リードフレーム２の裏面に印刷やフォトレジストなどによりレジスト層７（レジスト）を設ける。レジスト層７は、リードフレーム２の周縁部を除いた中央部に設けられる。その後、同図（Ｂ）に示すように、リードフレーム２のダイパッド２Ａ上に半導体チップ３を接着して搭載する。次に、ワイヤ４によって、半導体チップ３の電極パッド３Ａとボンディングパッド２Ｂとを電気的に接続する。ワイヤ４は、超音波ボンディングなどによって接続される。   Next, a method for manufacturing the semiconductor device 1 having the above-described configuration will be described with reference to FIG. First, as shown in FIG. 2A, a lead frame 2 is formed by etching or stamping a metal plate. Thereafter, a resist layer 7 (resist) is provided on the back surface of the lead frame 2 by printing, photoresist or the like. The resist layer 7 is provided at the central portion excluding the peripheral portion of the lead frame 2. Thereafter, as shown in FIG. 2B, the semiconductor chip 3 is mounted on the die pad 2A of the lead frame 2 by bonding. Next, the wire 4 electrically connects the electrode pad 3A of the semiconductor chip 3 and the bonding pad 2B. The wire 4 is connected by ultrasonic bonding or the like.

次に、同図（Ｂ）に示すように、半導体チップ３が搭載されて、ワイヤボンディングされた状態のリードフレーム２をモールド金型（図示せず）に装着される。モールド金型内には、樹脂がモールド金型に形成されたキャビティ（図示せず）により注入される。この工程により、図（Ｃ）に示すように、ワイヤ４で接続された半導体チップ３が封止部材６内に封止される。即ち、リードフレーム２、半導体チップ３及びワイヤ４が封止部材６内に封止される。このとき、封止部材６の裏側からレジスト層７が露出されている。また、レジスト層７の側面が封止部材６に覆われている。   Next, as shown in FIG. 5B, the semiconductor chip 3 is mounted and the lead frame 2 in a wire-bonded state is attached to a mold (not shown). Resin is injected into the mold through a cavity (not shown) formed in the mold. By this step, the semiconductor chip 3 connected by the wire 4 is sealed in the sealing member 6 as shown in FIG. That is, the lead frame 2, the semiconductor chip 3 and the wire 4 are sealed in the sealing member 6. At this time, the resist layer 7 is exposed from the back side of the sealing member 6. The side surface of the resist layer 7 is covered with the sealing member 6.

次に、同図（Ｄ）に示すように、レジスト層７を除去する。これにより、リードフレーム２の裏側が露出する。その後、同図（Ｅ）に示すように、リードフレーム２の裏側をメッキしてメッキ層５を設けて、完成する。   Next, as shown in FIG. 4D, the resist layer 7 is removed. Thereby, the back side of the lead frame 2 is exposed. Thereafter, as shown in FIG. 5E, the back side of the lead frame 2 is plated to provide a plating layer 5 to complete the process.

上述した半導体装置１によれば、リードフレーム２の裏面上に、リードフレーム２とは別体でメッキ層５が設けられている。封止部材６が、リードフレーム２の裏面を露出し、かつ、リードフレーム２の側面を覆うように、設けられている。この構造によれば、図２に示すように、リードフレーム２の裏面にレジスト層７を設けた後にワイヤボンダ、封止を行って、その後レジスト層７を除いてメッキ層５を形成するように製造することができる。これにより、レジスト層７は従来説明した粘着材９のようにワイヤボンダ時に発生する熱により溶けるものではない。このため、ワイヤ４が倒れる製品不良を防止することができる。また、レジスト層７は、粘着材９を用いなくても印刷などにより形成することができる。このため、シワがよる恐れがなく、リードフレーム２とメッキ層５との間に封止部材６が入り込む製品不良を防止することができる。また、封止部材６を形成した後に、メッキ層５を設けることができるので、メッキ層５の裏側に封止部材６が付着する製品不良を防止することができる。   According to the semiconductor device 1 described above, the plating layer 5 is provided on the back surface of the lead frame 2 separately from the lead frame 2. The sealing member 6 is provided so as to expose the back surface of the lead frame 2 and cover the side surface of the lead frame 2. According to this structure, as shown in FIG. 2, the resist layer 7 is provided on the back surface of the lead frame 2, and then wire bonding and sealing are performed, and then the plating layer 5 is formed by removing the resist layer 7. can do. As a result, the resist layer 7 is not melted by the heat generated at the time of wire bonding unlike the adhesive material 9 described above. For this reason, the product defect that the wire 4 falls can be prevented. The resist layer 7 can be formed by printing or the like without using the adhesive material 9. For this reason, there is no fear of wrinkles, and product defects in which the sealing member 6 enters between the lead frame 2 and the plating layer 5 can be prevented. Moreover, since the plating layer 5 can be provided after the sealing member 6 is formed, it is possible to prevent a product defect in which the sealing member 6 adheres to the back side of the plating layer 5.

また、上述した半導体装置１によれば、メッキ層５が、リードフレーム２の全周縁部を除くようにリードフレーム２の裏面上に設けられている。これにより、メッキ層５が除かれた部分に設けられた封止部材６によりリードフレーム２の裏面が支えられる。言い換えると、即ち、封止部材６は、メッキ層５が設けられていないリードフレーム２裏側の周縁部を覆うように設けられている。故に、封止部材６からリードフレーム２が抜け落ちにくくなる。   Moreover, according to the semiconductor device 1 described above, the plating layer 5 is provided on the back surface of the lead frame 2 so as to exclude the entire peripheral edge portion of the lead frame 2. Thereby, the back surface of the lead frame 2 is supported by the sealing member 6 provided in the portion where the plating layer 5 is removed. In other words, the sealing member 6 is provided so as to cover the peripheral portion on the back side of the lead frame 2 where the plating layer 5 is not provided. Therefore, it is difficult for the lead frame 2 to come off from the sealing member 6.

なお、上述した実施形態では、リードフレーム２の全周縁を除くようにメッキ層５、レジスト層７が設けられていたが、本発明はこれに限ったものではない。例えば、リードフレーム２の周縁の一部を除くようにメッキ層５、レジスト層７を設けてもよい。また、リードフレーム２の裏面全体を覆うようにメッキ層５、レジスト層７を設けてもよい。   In the embodiment described above, the plating layer 5 and the resist layer 7 are provided so as to exclude the entire periphery of the lead frame 2, but the present invention is not limited to this. For example, the plating layer 5 and the resist layer 7 may be provided so as to remove a part of the periphery of the lead frame 2. Further, a plating layer 5 and a resist layer 7 may be provided so as to cover the entire back surface of the lead frame 2.

また、上述した実施形態では、メッキ層５はメッキにより設けられていたが、本発明はこれに限ったものではない。例えば、印刷により設けてもよいし、半田付して設けてもよい。   In the embodiment described above, the plating layer 5 is provided by plating, but the present invention is not limited to this. For example, it may be provided by printing or may be provided by soldering.

また、前述した実施形態は本発明の代表的な形態を示したに過ぎず、本発明は、実施形態に限定されるものではない。即ち、本発明の骨子を逸脱しない範囲で種々変形して実施することができる。   Further, the above-described embodiments are merely representative forms of the present invention, and the present invention is not limited to the embodiments. That is, various modifications can be made without departing from the scope of the present invention.

本発明の半導体装置の一実施の形態を示す断面図である。It is sectional drawing which shows one Embodiment of the semiconductor device of this invention. 図１に示す半導体装置の製造方法を示す断面図である。FIG. 2 is a cross-sectional view showing a manufacturing method of the semiconductor device shown in FIG. 従来の半導体装置の製造方法を説明するための説明図である。It is explanatory drawing for demonstrating the manufacturing method of the conventional semiconductor device.

符号の説明Explanation of symbols

１ 半導体装置
２ リードフレーム（第１の電極層）
３ 半導体チップ（チップ部品）
４ ワイヤ
５ メッキ層（第２の電極層）
６ 封止部材
７ レジスト層（レジスト） DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Lead frame (1st electrode layer)
3 Semiconductor chip (chip parts)
4 Wire 5 Plating layer (second electrode layer)
6 Sealing member 7 Resist layer (resist)

Claims (3)

第１の電極層と、前記第１の電極層の表面上に搭載されたチップ部品と、前記チップ部品の電極及び前記第１の電極層の表面間にワイヤボンダされた前記チップ部品及び前記第１の電極層を電気的に接続するワイヤと、前記第１の電極層、前記チップ部品、及び、前記ワイヤ、を封止する封止部材と、を備えた半導体装置において、
前記第１の電極層の裏面上に設けられた前記第１の電極層とは別体に設けられた第２の電極層を備え、そして、
前記封止部材が、前記第２の電極層の裏面を露出し、かつ、前記第２の電極層の側面を覆うように、設けられている
ことを特徴とする半導体装置。 A first electrode layer; a chip component mounted on the surface of the first electrode layer; the chip component wire bonded between the electrode of the chip component and the surface of the first electrode layer; In a semiconductor device comprising: a wire for electrically connecting the electrode layer; and a sealing member for sealing the first electrode layer, the chip component, and the wire.
A second electrode layer provided separately from the first electrode layer provided on the back surface of the first electrode layer; and
The semiconductor device, wherein the sealing member is provided so as to expose a back surface of the second electrode layer and cover a side surface of the second electrode layer. 前記第２の電極層が、前記第１の電極層の周縁部の少なくとも一部を除くように前記第１の電極層の裏面上に設けられている
ことを特徴とする請求項１に記載の半導体装置。 The said 2nd electrode layer is provided on the back surface of the said 1st electrode layer so that at least one part of the peripheral part of the said 1st electrode layer may be remove | excluded. The Claim 1 characterized by the above-mentioned. Semiconductor device. 第１の電極層と、前記第１の電極層の表面上に搭載されたチップ部品と、前記チップ部品の電極及び前記第１の電極層の表面間にワイヤボンダされた前記チップ部品及び前記第１の電極層を電気的に接続するワイヤと、前記第１の電極層、前記チップ部品、及び、前記ワイヤ、を封止する封止部材と、を備えた半導体装置の製造方法であって、
前記第１の電極層の裏面上にレジストを形成する工程と、
前記第１の電極層の表面に前記チップ部材を搭載して前記ワイヤによって前記チップ部材及び前記第１の電極層を電気的に接続する工程と、
前記レジストの裏面が露出され、かつ、前記レジストの側面が覆われるように、前記封止部材を形成する工程と、
前記レジストを取り除く工程と、
前記第１の電極層の裏面に第２の電極層を形成する工程と、
を順次行うことを特徴とする半導体装置の製造方法。 A first electrode layer; a chip component mounted on the surface of the first electrode layer; the chip component wire bonded between the electrode of the chip component and the surface of the first electrode layer; A method of manufacturing a semiconductor device, comprising: a wire that electrically connects the electrode layers; and a sealing member that seals the first electrode layer, the chip component, and the wire,
Forming a resist on the back surface of the first electrode layer;
Mounting the chip member on the surface of the first electrode layer and electrically connecting the chip member and the first electrode layer with the wire;
Forming the sealing member such that the back surface of the resist is exposed and the side surfaces of the resist are covered;
Removing the resist;
Forming a second electrode layer on the back surface of the first electrode layer;
A method for manufacturing a semiconductor device, wherein the steps are sequentially performed.
JP2008071652A 2008-03-19 2008-03-19 Semiconductor device and method of manufacturing the same Withdrawn JP2009231347A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101234141B1 (en) * 2011-03-23 2013-02-22 엘지이노텍 주식회사 Structure for multi-row lead frame and semiconductor package thereof and manufacture method thereof
JP2016146455A (en) * 2015-02-04 2016-08-12 株式会社東芝 Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101234141B1 (en) * 2011-03-23 2013-02-22 엘지이노텍 주식회사 Structure for multi-row lead frame and semiconductor package thereof and manufacture method thereof
JP2016146455A (en) * 2015-02-04 2016-08-12 株式会社東芝 Semiconductor device and manufacturing method thereof

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