JP2007536724A - バイポーラ・デバイス、トランジスタ・デバイス、ならびにトランジスタおよびバイポーラ相補型金属酸化膜半導体(BiCMOS)デバイスを製造する方法 - Google Patents
バイポーラ・デバイス、トランジスタ・デバイス、ならびにトランジスタおよびバイポーラ相補型金属酸化膜半導体(BiCMOS)デバイスを製造する方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 81
- 230000000295 complement effect Effects 0.000 title claims abstract description 15
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 11
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 41
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 29
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 28
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 47
- 239000012212 insulator Substances 0.000 claims description 37
- 239000012535 impurity Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
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- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
- H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation
Abstract
バイポーラ・デバイス、トランジスタ・デバイス、ならびにトランジスタおよびバイポーラ相補型金属酸化膜半導体(BiCMOS)デバイスを製造する方法を提供することを目的とする。
【解決手段】
コレクタ(112)、コレクタの上方の真性ベース(118)、コレクタに隣接するシャロートレンチ分離領域(114)、真性ベースの上方の隆起外部ベース(202)、外部ベースの上方のT字形のエミッタ(800)、エミッタに隣接するスペーサ(700)、および、スペーサによりエミッタから分離されるシリサイド(400)層を有する、バイポーラ相補形金属酸化膜半導体(BiCMOS)またはNPN/PNPデバイスを開示する。
【選択図】 図8
Description
Claims (31)
- ベースと、
下部区域と、前記下部区域よりも幅が広い上部区域とを備えたT字形である、前記ベースの上方のエミッタと、
前記エミッタの前記下部区域に隣接し、かつ前記エミッタの前記上部区域の下方にあるスペーサと、
前記スペーサに隣接し、かつ前記エミッタの前記上部区域の下方にあるシリサイド層とを有する、バイポーラ・デバイス。 - 前記ベースの上方かつ前記スペーサの下方にある誘電体構造をさらに有する、請求項1に記載のデバイス。
- 前記ベースが前記誘電体構造よりも幅が広い、請求項2に記載のデバイス。
- 前記スペーサが、前記エミッタを前記シリサイドから分離する、請求項1に記載のデバイス。
- 前記ベースが、
真性ベースと、
前記真性ベースの上方の外因性ベースとを有する、請求項1に記載のデバイス。 - 前記スペーサが絶縁体を有する、請求項1に記載のデバイス。
- 前記シリサイド層がサリサイドを含む、請求項1に記載のデバイス。
- 第1の種類の不純物を有する下部半導体構造と、
前記第1の種類の不純物に対して相補的な第2の種類の不純物を有する、前記下部半導体構造の上方の中間半導体領域と、
下部区域と、前記下部区域よりも幅が広い上部区域とを備えたT字形である、前記中間半導体領域の上方の上部半導体構造と、
前記上部半導体構造の前記下部区域に隣接し、かつ前記上部半導体構造の前記上部区域の下方にあるスペーサと、
前記スペーサに隣接し、かつ前記上部半導体構造の前記上部区域の下方にあるシリサイド層とを有する、トランジスタ・デバイス。 - 前記中間半導体領域の上方かつ前記スペーサの下方にある誘電体構造をさらに有する、請求項8に記載のデバイス。
- 前記中間半導体領域が前記誘電体構造よりも幅が広い、請求項9に記載のデバイス。
- 前記スペーサが、前記上部半導体構造を前記シリサイドから分離する、請求項8に記載のデバイス。
- 前記中間半導体領域が、
真性中間半導体領域と、
前記真性中間半導体領域の上方の外因性中間半導体領域とを有する、請求項8に記載のデバイス。 - 前記スペーサが絶縁体を有する、請求項8に記載のデバイス。
- 前記シリサイドがサリサイドを含む、請求項8に記載のデバイス。
- 真性ベースの上方に外因性ベースを形成するプロセスと、
前記外因性ベースの中心部の上方に配置される犠牲的マスクを用いて、前記外因性ベースの一部分を保護するプロセスと、
前記外因性ベースの露出部分をシリサイド化するとともに、前記外因性ベースの前記中心部の上方に非シリサイド化部分を残すプロセスと、
前記外因性ベースの前記非シリサイド化部分の中心部を貫通してエミッタ開口部を形成するプロセスと、
前記エミッタ開口部内にスペーサを形成するプロセスと、
前記エミッタ開口部内にエミッタを形成するプロセスとを有し、
前記スペーサが、前記エミッタを前記外因性ベースのシリサイド化部分から分離する、トランジスタを製造する方法。 - 前記外因性ベースを形成する前に、
前記真性ベースの前記中心部の上方に絶縁体をパターン形成するプロセスと、
前記絶縁体および前記真性ベースの上方に前記外因性ベースをエピタキシャル成長させるプロセスとをさらに有する、請求項15に記載の方法。 - 前記外因性ベースをエピタキシャル成長させる前記プロセスが、前記絶縁体の上方にポリシリコンを成長させ、かつ前記真性ベースの露出部分の上方に単結晶シリコンを成長させる、請求項16に記載の方法。
- 前記スペーサが前記絶縁体上に形成される、請求項16に記載の方法。
- 前記シリサイド・プロセスが、前記非シリサイド化部分に水平方向に隣接して前記外因性ベースの前記シリサイド化部分を形成する、請求項15に記載の方法。
- 前記エミッタ開口部を形成する前に、前記外因性ベースの上方に絶縁体層を形成するプロセスをさらに有し、前記エミッタ開口部が、前記絶縁体層を貫通して形成される、請求項15に記載の方法。
- 第1の種類の不純物を有する下部半導体構造を形成するプロセスと、
前記第1の種類の不純物に対して相補的な第2の種類の不純物を有する、前記下部半導体構造の上方の中間半導体領域を形成するプロセスと、
前記中間半導体領域の中心部の上方に配置される犠牲的マスクを用いて、前記中間半導体領域の一部分を保護するプロセスと、
前記中間半導体領域の露出部分をシリサイド化するとともに、前記中間半導体領域の前記中心部の上方に非シリサイド化部分を残すプロセスと、
前記中間半導体領域の前記非シリサイド化部分の中心部を貫通して上部半導体構造開口部を形成するプロセスと、
前記上部半導体構造開口部内にスペーサを形成するプロセスと、
前記上部半導体構造開口部内に上部半導体構造を形成するプロセスとを有し、
前記スペーサが、前記上部半導体構造を前記中間半導体領域のシリサイド化部分から分離する、トランジスタを製造する方法。 - 前記中間半導体領域を形成する前に、
前記下部半導体構造の上方にシリコン層を形成するプロセスと、
前記シリコン層の前記中心部の上方に絶縁体をパターン形成するプロセスと、
前記絶縁体および前記シリコン層の上方に前記中間半導体領域をエピタキシャル成長させるプロセスとをさらに有する、請求項21に記載の方法。 - 前記中間半導体領域をエピタキシャル成長させる前記プロセスが、前記絶縁体の上方にポリシリコンを成長させ、かつ前記シリコン層の露出部分の上方に単結晶シリコンを成長させる、請求項22に記載の方法。
- 前記スペーサが前記絶縁体上に形成される、請求項21に記載の方法。
- 前記シリサイド・プロセスが、前記非シリサイド化部分に水平方向に隣接して前記中間半導体領域の前記シリサイド化部分を形成する、請求項21に記載の方法。
- 前記上部半導体構造開口部を形成する前に、前記中間半導体領域の上方に絶縁体層を形成するプロセスをさらに有し、前記上部半導体構造開口部が、前記絶縁体層を貫通して形成される、請求項21に記載の方法。
- コレクタを形成するプロセスと、
前記コレクタに隣接してシャロートレンチ分離領域を形成するプロセスと、
前記コレクタの上方に真性ベースを形成するプロセスと、
前記真性ベースの上方に隆起外因性ベースを形成するプロセスと、
前記外因性ベースの中心部の上方に配置される犠牲的マスクを用いて、前記外因性ベースの一部分を保護するプロセスと、
前記外因性ベースの露出部分をシリサイド化するとともに、前記外因性ベースの前記中心部の上方に非シリサイド化部分を残すプロセスと、
前記外因性ベースの前記非シリサイド化部分の中心部を貫通してエミッタ開口部を形成するプロセスと、
前記エミッタ開口部内にスペーサを形成するプロセスと、
前記エミッタ開口部内にエミッタを形成するプロセスとを有し、
前記スペーサが、前記エミッタを前記外因性ベースのシリサイド化部分から分離する、バイポーラ相補型金属酸化膜半導体(BiCMOS)デバイスを製造する方法。 - 前記外因性ベースを形成する前に、
前記真性ベースの前記中心部の上方に絶縁体をパターン形成するプロセスと、
前記絶縁体および前記真性ベースの上方に前記外因性ベースをエピタキシャル成長させるプロセスとをさらに有する、請求項27に記載の方法。 - 前記外因性ベースをエピタキシャル成長させる前記プロセスが、前記絶縁体の上方にポリシリコンを成長させ、かつ前記真性ベースの露出部分の上方に単結晶シリコンを成長させる、請求項28に記載の方法。
- 前記シリサイド・プロセスが、前記非シリサイド化部分に水平方向に隣接して前記外因性ベースの前記シリサイド化部分を形成する、請求項27に記載の方法。
- 前記スペーサが前記絶縁体上に形成される、請求項27に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/709,113 | 2004-04-14 | ||
US10/709,113 US6911681B1 (en) | 2004-04-14 | 2004-04-14 | Method of base formation in a BiCMOS process |
PCT/US2005/011711 WO2005104680A2 (en) | 2004-04-14 | 2005-04-06 | A method of base formation in a bicmos process |
Publications (3)
Publication Number | Publication Date |
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JP2007536724A true JP2007536724A (ja) | 2007-12-13 |
JP2007536724A5 JP2007536724A5 (ja) | 2008-05-15 |
JP5182797B2 JP5182797B2 (ja) | 2013-04-17 |
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JP (1) | JP5182797B2 (ja) |
KR (2) | KR20070003976A (ja) |
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US6911681B1 (en) | 2004-04-14 | 2005-06-28 | International Business Machines Corporation | Method of base formation in a BiCMOS process |
US7709338B2 (en) * | 2006-12-21 | 2010-05-04 | International Business Machines Corporation | BiCMOS devices with a self-aligned emitter and methods of fabricating such BiCMOS devices |
DE102008010323A1 (de) * | 2008-02-21 | 2009-09-10 | Texas Instruments Deutschland Gmbh | Verfahren zur Herstellung einer elektronischen Vorrichtung, die einen bipolaren PNP-Transistor umfasst |
US20090250785A1 (en) * | 2008-04-02 | 2009-10-08 | Thomas Joseph Krutsick | Methods of forming a shallow base region of a bipolar transistor |
US8853796B2 (en) * | 2011-05-19 | 2014-10-07 | GLOBALFOUNDIERS Singapore Pte. Ltd. | High-K metal gate device |
US20120313146A1 (en) | 2011-06-08 | 2012-12-13 | International Business Machines Corporation | Transistor and method of forming the transistor so as to have reduced base resistance |
US8546230B2 (en) | 2011-11-15 | 2013-10-01 | International Business Machines Corporation | Bipolar transistor with a collector having a protected outer edge portion for reduced based-collector junction capacitance and a method of forming the transistor |
US8603883B2 (en) | 2011-11-16 | 2013-12-10 | International Business Machines Corporation | Interface control in a bipolar junction transistor |
US20130277804A1 (en) * | 2012-04-20 | 2013-10-24 | International Business Machines Corporation | Bipolar junction transistors with reduced base-collector junction capacitance |
US9887278B2 (en) | 2015-09-28 | 2018-02-06 | International Business Machines Corporation | Semiconductor-on-insulator lateral heterojunction bipolar transistor having epitaxially grown intrinsic base and deposited extrinsic base |
US11508354B2 (en) * | 2020-05-04 | 2022-11-22 | Rovi Guides, Inc. | Method and apparatus for correcting failures in automated speech recognition systems |
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- 2005-04-06 JP JP2007508392A patent/JP5182797B2/ja not_active Expired - Fee Related
- 2005-04-06 KR KR1020067019999A patent/KR20070003976A/ko active IP Right Grant
- 2005-04-06 EP EP05736453A patent/EP1754253A4/en not_active Withdrawn
- 2005-04-06 KR KR1020117007280A patent/KR20110049896A/ko not_active Application Discontinuation
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Publication number | Publication date |
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JP5182797B2 (ja) | 2013-04-17 |
CN101076896A (zh) | 2007-11-21 |
EP1754253A2 (en) | 2007-02-21 |
KR20110049896A (ko) | 2011-05-12 |
TW200534401A (en) | 2005-10-16 |
EP1754253A4 (en) | 2008-10-22 |
US7625792B2 (en) | 2009-12-01 |
US20070207567A1 (en) | 2007-09-06 |
US6911681B1 (en) | 2005-06-28 |
TWI343605B (en) | 2011-06-11 |
WO2005104680A2 (en) | 2005-11-10 |
CN101076896B (zh) | 2011-07-13 |
KR20070003976A (ko) | 2007-01-05 |
WO2005104680A3 (en) | 2007-07-05 |
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