WO1999052138A1

WO1999052138A1 - A bipolar transistor having low extrinsic base resistance

Info

Publication number: WO1999052138A1
Application number: PCT/US1999/007644
Authority: WO
Inventors: Rick C. Jerome
Original assignee: Aeroflex Utmc Microelectronic Systems Inc.
Priority date: 1998-04-08
Filing date: 1999-04-07
Publication date: 1999-10-14

Abstract

A method is disclosed for forming a vertical bipolar transistor having a relatively low value of extrinsic base resistance. The method creates the transistor having a recessed emitter and a single polysilicon layer that functions as the emitter contact. The polysilicon emitter contact extends downward into a shallow trench formed in an upper portion of a layer of silicon that is heavily doped to form the extrinsic base regions on each side of the shallow trench. At the bottom of the shallow trench is the single crystal emitter region which overlies the intrinsic base region of the transistor. In turn, the intrinsic base region overlies the collector region.

Description

A Bipolar Transistor Having Low Extrinsic Base Resistance

Technical Field

This invention relates to integrated circuits ("ICs"), and more particularly to a method of forming a vertical bipolar transistor having an extrinsic base region with a relatively low resistance value.

Background Art

In the art of bipolar junction transistors ("BJTs"), it is known to utilize a vertical "stacked" structure for the active elements or regions of the transistor. A base region is formed on top of a collector region, while an emitter region is formed on top of the base region. The emitter, base and collector regions are all formed in a silicon substrate and are all appropriately doped to have the desired electrical conductivity type and dopant concentration. For example, the collector and emitter may both be doped P type, while the base is doped N type. In contrast, the collector and emitter may both be doped N type and the base doped P type. A relatively light dopant concentration is typically indicated by a minus symbol ("-") following the conductivity type (e.g., "P-"), while a relatively more heavy dopant concentration is indicated by a plus symbol ("+").

Typically, one or more polysilicon layers are deposited, patterned and etched to form electrical contacts to the active regions of the transistor. Various oxide regions act as insulators between the polysilicon contact layers. Other oxide regions isolate the bipolar transistor from other devices formed in or on the IC substrate. The polysilicon contact layers and oxide insulating regions are generally formed on the top surface of the substrate. The base region is typically divided into a central intrinsic region flanked on each side by an outer extrinsic region. The intrinsic base region is that portion of the base region over which the emitter region is located. On the other hand, the two extrinsic base regions are those regions to which the external polysilicon connection electrodes are connected. The intrinsic base region is connected to the two extrinsic base regions by a low resistivity, linking region. These linking regions are part of the corresponding extrinsic base regions. Typically, each linking region has a dopant concentration in between the dopant concentrations of the remainder of the corresponding extrinsic base region and that of the intrinsic base region.

It is a general trend in the integrated circuit industry to manufacture devices that are faster and smaller. Sizes of device elements have now been reduced to the sub-micron level. Advances in photolithography are largely responsible for these size reductions. On the other hand, increases in device speed are primarily due to the reduction of certain device resistance and capacitance values.

More specifically, a reduction in the switching speed of a vertical bipolar transistor is attributed to a reduction in the resistance value of the extrinsic base region. This reduced switching speed leads to a reduction in the gate delay of a digital circuit, or an increase inf_mΑX for analog circuits. There are various known approaches in the prior art to accomplishing this reduction in resistance value. These approaches include the use of a self-aligned suicide ("salicide") formed on the top surfaces of the extrinsic base regions, and altering the grain boundaries at the interface between the epitaxial silicon intrinsic base region and the polysilicon extrinsic base regions. These and other prior art approaches to reducing the value of the extrinsic base resistance are disclosed in U.S. Pat. Nos. 5616508, 5436180, 5139961, 5137840, 4857476, 4755476, 4735916 and 4236294, all of these patents being hereby incorporated by reference. It is also known in the prior art to form a vertical bipolar transistor with two separate regions or layers of polysilicon comprising the electrical contacts for the active device regions. A first polysilicon contact region functions as the emitter contact, while one or more additional polysilicon contact regions function as the extrinsic base region contacts. The electrically-conductive polysilicon contacts are typically separated by oxide insulating regions. This type of device is referred to as a "double polysilicon BJT", and is described and illustrated in the aforementioned U.S. Pat. No. 5616508. However, inherent problems exist with this type of vertical bipolar transistor.

Particularly, the use of two polysilicon contact regions, together with the associated oxide insulating layers, requires relatively complex, additional IC processing steps. These steps include those associated with the etching and diffusion of polysilicon. Also, non-planarities result in the active areas of the silicon substrate due to the anisotropic etching carried out on the polysilicon contact regions. That is, anisotropic etching inherently results in different etch rates in different directions. Typically, the vertical etch rate is greater than the lateral etch rate, which causes the aforementioned undesired overetching of the active areas of the silicon substrate. These problems with double polysilicon BJTs are discussed in the aforementioned U.S. Pat. No. 5616508. That patent discloses a double polysilicon BJT that purports to eliminate the overetching and damage to the active areas of the silicon substrate. It also describes a scheme for doping the base linking region, wherein the doping of the linking region is independent from the doping of the remainder of the extrinsic base region. Nevertheless, that patent describes a double polysilicon BJT whose formation involves relatively complex processing steps.

Disclosure of Invention

Objects of the invention include the provision of a method of forming a vertical bipolar transistor with a single polysilicon emitter contact layer and with relatively less complex manufacturing steps. Other objects of the method of the present invention include the formation of the vertical bipolar transistor having a relatively low value of extrinsic base resistance, thereby reducing the switching time of the transistor and improving the current handling ability of the transistor, which enables use of the transistor in high-speed analog or digital circuit applications.

According to the present invention, a method of forming a single polysilicon layer, vertical bipolar transistor ("single polysilicon BJT"), having a relatively low value of extrinsic base resistance, starts with a silicon substrate doped P-. An N+ buried layer is formed in the substrate. On the top surface of the buried layer is grown a lightly-doped, N- epitaxial silicon layer. Field oxide regions are formed on each side of the active device area of the substrate, thereby isolating that active device area from other active device areas formed in the substrate. Next, a thin layer of implant oxide is grown on the top surface of the N- epitaxial silicon layer. A heavily doped, P+ impurity region is formed on the top surface of the implant oxide layer. This region ultimately comprises the two extrinsic base regions of the transistor. The P+ region is annealed to activate the dopant for the P+ extrinsic base regions. The implant oxide is then removed. A layer of titanium is deposited on the top surface of the P+ extrinsic base region.

A layer of oxide is then deposited on the top surface of the titanium layer. A photoresist layer is deposited in predetermined locations on the top surface of the oxide layer. The photoresist layer is used as a pattern for the next step of etching of the oxide layer, the titanium layer and a portion of the P+ extrinsic base region layer. The result of the etch step is a shallow trench having steep sidewalls that extend down into the P+ extrinsic base region at a predetermined distance.

The next step is to remove the photoresist. A P- intrinsic base region is then implanted using a rotational implant. A layer of oxide is deposited and anisotropically etched to form oxide spacers at the bottom of the shallow trench and along the sidewalls of the shallow trench adjacent the P+ extrinsic base regions. This etch opens up the emitter contact to single crystal silicon. The oxide spacers merge with the layer of oxide formed on the top surface of the titanium layer. Next, a polysilicon emitter contact region is deposited entirely within the shallow trench and extending over the top surface of the oxide layer. The polysilicon emitter is then implanted with arsenic, to form an N+ region. The polysilicon emitter contact is patterned and etched. An anneal process is performed by which the arsenic implant diffuses downward to form a single crystal emitter region on top of the intrinsic base region. Finally, a layer of titanium is deposited on the top surface of the polysilicon emitter contact.

The above and other objects of this invention will become more readily apparent when the following description is read in conjunction with the accompanying drawings.

Brief Description of Drawings

Figs. 1-3 are cross-sectional illustrations of a silicon substrate having a single polysilicon layer, vertical bipolar transistor formed therein at various steps during the method of the present invention.

Best Mode for Carrying Out the Invention The method of the present invention comprises a multiple step process for forming a vertical bipolar transistor within a semiconductor substrate. As used herein, "vertical bipolar transistor" refers to the internal structure of the transistor formed in the substrate, wherein the active elements of the transistor (i.e., emitter, base and collector) are "stacked" on top of each other. Referring to Fig. 1, the method starts with a semiconductor substrate 100, preferably comprising silicon that is doped P-. However, other types of semiconductor material may be utilized. Also, the substrate 100 may have a different dopant concentration and/or type. Next, an N+ buried layer 104 is formed in the substrate 100. The buried layer 104 preferably has a thickness of approximately 1.5 to 2.0 microns. A lightly doped, N- epitaxial silicon layer 108 is grown on the top surface of the buried layer 104, and has a sheet resistance of less than twenty ohms per square. The epitaxial silicon layer 108 preferably has a thickness of approximately 0.6 to 1.0 microns, and has a doping concentration of lElό to 1E17 atoms/cm³. The N+ buried layer 104 and the N- epitaxial silicon layer 108 together form the collector region of the transistor. A field oxide region 112 is formed on each side of the active device area 116 in the substrate 100. The field oxide regions 112 isolate the active device area 116 from other active device areas (not shown) formed in the substrate 100. The field oxide regions 112 may be formed by the known, local oxidation of silicon ("LOCOS") process.

Next, a thin layer (e.g., 150 Angstroms) of implant oxide (not shown) is grown on the top surface of the N- epitaxial silicon layer 108. This oxide layer functions as a conventional screen oxide layer. A heavily doped, P+ impurity layer 120 is formed in the N- epitaxial layer 108. This impurity layer 120 is formed by a low energy (e.g., lOKeV) implantation of an impurity, preferably boron (e.g., BF₂), down through the top surface of the screen oxide layer and into the epitaxial layer 108. The preferred thickness of the P+ layer 120 is approximately 0.2 microns. The preferred peak dopant concentration of the boron impurity is 8E18 atoms/cm³, with the peak concentration occurring near the top surface of the P+ layer 120. As described in detail hereinafter, the P+ layer 120 is etched to ultimately form the two extrinsic base regions of the transistor. The P+ layer 120 is then annealed to activate the boron dopant. The boron dopant achieves the desired, relatively low value of resistivity for the P+ extrinsic base regions. The annealing step is preferably a known, rapid thermal anneal ("RTA") process, or a conventional anneal process at approximately 900 degrees C for approximately 15 minutes. Once the annealing step is completed, the implant screen oxide layer is removed. A layer 124 of titanium is then deposited on the top surface of the P+ layer 120. The titanium layer 124 forms a conventional, low resistance, suicide electrical contact to the P+ extrinsic base regions. The titanium layer 124 has a preferred thickness of approximately 600 to 1000 Angstroms.

-6- Referring to Fig. 2, a layer 128 of oxide is formed on the top surface of the titanium layer 124. The oxide layer 128 has a preferred thickness of approximately 2000 Angstroms. The oxide layer 128 may be formed by a known, plasma enhanced, chemical vapor deposition ("PECVD") process, or by a known, low temperature oxidation ("LTO") process. A mask layer 132 of photoresist is deposited on the top surface of the oxide layer 128 in a predetermined pattern. The photoresist layer 132 is deposited to leave a central opening 136 above the active device area 116 of the silicon substrate 100.

Next, a portion of each of the oxide layer 128, the titanium layer 124 and the P+ layer 120 is removed by etching at the central opening 136 defined by the photoresist mask layer 132. The etching in a vertical, downward direction completely removes both the oxide layer 128 and the titanium layer 124, and a portion of the P+ layer 120, at the opening 136. The etching step preferably comprises a known, reactive ion etch ("RIE") process. The result of the etching step is a shallow trench 140 with steep sidewalls, formed down in the P+ layer 120. The shallow trench 140 extends into the P+ layer 120 at a distance of approximately 0.15 microns. The shallow trench 140 defines the two P+ external base regions 144; one region 144 on each side of the shallow trench 140.

Referring to Fig. 3, the next step in the method of the present invention is to completely remove the photoresist layer 132. A P- intrinsic base region 148 is then implanted down into the N- epitaxial layer 108 using a known, rotational implant process. The preferred thickness of the P- intrinsic base region 148 is approximately 0.1 to 0.15 microns.

A layer of oxide 152 is deposited on top of the previously-formed oxide layer 128, as well as on the bottom and side surfaces of the shallow trench 140. The portion of the oxide layer 152 within the shallow trench 140 is anisotropically etched to form oxide spacers 156 along the sidewalls of the shallow trench and adjacent the

-7- P+ extrinsic base regions 144. The oxide spacers 156 merge with the oxide layers

128, 152 formed on the top surface of the titanium layer 124.

Next, a polysilicon emitter contact region 160 is deposited entirely within the shallow trench 140 and extending over the top surface of the oxide layer 152. The polysilicon emitter contact region 160 is then implanted with arsenic, thereby doping the region N+. The polysilicon emitter contact region 160 is patterned and etched.

An anneal process is performed which diffuses the arsenic implant downward into the remaining P+ layer 120 and the P- intrinsic base region 148. This diffusion forms a single crystal emitter region 164 on top of the P- intrinsic base region 148. The preferred thickness of the single crystal emitter region 164 is approximately

0.05 to 0.10 microns.

Finally, a layer 168 of titanium is deposited on the top surface of the polysilicon emitter contact region 160. The titanium layer 168 forms a conventional, low resistance, suicide electrical contact to the polysilicon emitter contact region 160. The titanium layer 168 has a preferred thickness of approximately 600 to 1000 Angstroms.

Although not shown, low resistivity metal electrical contacts may be made to the titanium layer 124 formed on top of the P+ extrinsic base regions 144. The contacts may be made by through corresponding openings (not shown) formed in the oxide layers 128, 152. The metal contacts take the place of the second layer or region of polysilicon, described hereinbefore with respect to prior art, "double polysilicon BJT" devices.

As described and illustrated herein, the method of the present invention involves the use of only a single layer of polysilicon (i.e., that of the emitter contact region 160). Also, this polysilicon region 160 does not require any anisotropic etching steps. Thus, the present invention eliminates the non-planarites associated with the aforementioned prior art patents that involve anisotropic etching of

-8- polysilicon, with the resultant undesired etching into the active device area in the substrate.

The method of the present invention has utility in that it forms a vertical bipolar transistor with a single polysilicon contact layer with relatively less manufacturing steps than prior art processes for manufacturing double polysilicon BJTs. Also, the method of the present invention forms the vertical bipolar transistor with a relatively low value of extrinsic base resistance, reduced collector-base junction capacitance, and reduced peripheral emitter junction capacitance. This reduces the switching time of the transistor and improves the current handling ability of the transistor. This allows use of the transistor in high-speed analog or digital circuit applications.

The method has been described for use in manufacturing a vertical NPN transistor. However, the invention is not limited as such. Instead, it should be obvious to one of ordinary skill in the art, in light of the teachings herein, that the method may be used to form a vertical PNP transistor. Also, it should be understood that certain ones of the process steps described and illustrated herein are purely exemplary. For example, the field oxide regions 112 may be formed by a process other than the known LOCOS process. These and other alternatives should be apparent to one of ordinary skill in the art, in light of the teachings herein. It should be understood by those skilled in the art that obvious structural modifications can be made, in light of the teachings herein, without departing from the scope of the invention. Accordingly, reference should be made primarily to the accompanying claims, rather than the foregoing specification, to determine the scope of the invention. Having thus described the invention, what is claimed is:

Claims

1. A method of forming a vertical bipolar transistor, comprising the steps of: providing a semiconductor substrate having a first conductivity type; forming a first collector region in the substrate, the first collector region having a second conductivity type that is opposite the first conductivity type; forming a second collector region in the substrate, the second collector region having a conductivity type that is the same as the second conductivity type; forming a base region in the substrate, the base region having a conductivity type that is the same as the first conductivity type, the base region having a first dopant concentration to achieve a desired electrical resistivity; removing a portion of the base region down from a top surface of the base region at a predetermined distance to thereby form a shallow trench in the base region, the shallow trench defining two extrinsic base regions within the base region, the two extrinsic base regions being disposed on each side of the shallow trench; forming an intrinsic base region down a predetermined distance in the second collector region from a bottom surface of the shallow trench, the intrinsic base region having a conductivity type that is the same as the first conductivity type, the intrinsic base region having a second dopant concentration to achieve a desired electrical resistivity that is greater than the electrical resistivity of the two extrinsic base regions; forming at least one insulating spacer along both a sidewall of the shallow trench and a portion of the bottom surface of shallow trench; forming an emitter contact region by providing a conductive material completely within the shallow trench, the emitter contact region having a conductivity type that is the same as the second conductivity type; and

-10- forming an emitter region down from the bottom surface of the shallow trench and within the intrinsic base region, the emitter region having a conductivity type that is the same as the second conductivity type.

2. The method of Claim 1 , further comprising the step of forming a field isolating region on each side of an active device area comprising a portion of the substrate, the first and second collector regions, the intrinsic and extrinsic base regions, the emitter contact region and the emitter region.

3. The method of Claim 1, further comprising the steps of: forming a conductive contact layer on a top surface of each one of the two extrinsic base regions; and forming an insulating layer on a top surface of each one of the two conductive contact layers.

4. The method of Claim 3, wherein the step of forming the emitter contact region by providing the conductive material completely within the shallow trench further comprises the step of providing the conductive material on at least a portion of a top surface of each one of the two insulating layers.

5. The method of Claim 1 , further comprising the step of forming a conductive contact layer on a top surface of the emitter contact region.

6. The method of Claim 1, wherein the conductive material completely filling the shallow trench comprises polysilicon.

7. The method of Claim 1 , wherein the step of removing a portion of the base region down from a top surface of the base region at a predetermined distance to thereby form a shallow trench in the base region comprises an etching step.

-11-

8. The method of Claim 7, wherein the etching step comprises a reactive ion etching step.

9. The method of Claim 1 , wherein prior to the step of removing a portion of the base region down from a top surface of the base region at a predetermined distance to thereby form a shallow trench in the base region, the method further comprises the step of providing a mask layer having a predetermined opening located therein, the opening being located at the desired location of the shallow trench to be formed in the base region.

10. A vertical bipolar transistor, comprising: a substrate having a first conductivity type; a first collector region within the substrate, the first collector region having a second conductivity type that is opposite the first conductivity type; a second collector region within the substrate, the second collector region having a conductivity type that is the same as the second conductivity type; a base region within the substrate, the base region having a conductivity type that is the same as the first conductivity type, the base region having a first dopant concentration to achieve a desired electrical resistivity; a shallow trench within the base region, the shallow trench defining two extrinsic base regions within the base region, the two extrinsic base regions being disposed on each side of the shallow trench; an intrinsic base region within the second collector region, the intrinsic base region having a conductivity type that is the same as the first conductivity type, the intrinsic base region having a second dopant concentration to achieve a desired electrical resistivity that is greater than the electrical resistivity of the two extrinsic base regions;

-12- at least one insulating spacer disposed along both a sidewall of the shallow trench and a portion of the bottom surface of shallow trench; an emitter contact region comprising a conductive material disposed completely within the shallow trench, the emitter contact region having a conductivity type that is the same as the second conductivity type; and an emitter region within the intrinsic base region, the emitter region having a conductivity type that is the same as the second conductivity type.

11. The transistor of Claim 10, wherein the conductive material disposed completely within the shallow trench comprises polysilicon.

12. The transistor of Claim 10, further comprising a field isolating region disposed on each side of an active device area comprising a portion of the substrate, the first and second collector regions, the intrinsic and extrinsic base regions, the emitter contact region and the emitter region.

13. The transistor of Claim 10, further comprising a conductive contact layer disposed on a top surface of each one of the two extrinsic base regions, and an insulating layer disposed on a top surface of each one of the two conductive contact layers.

14. The transistor of Claim 13, wherein the conductive material completely disposed within the shallow trench also is disposed on at least a portion of a top surface of each one of the two insulating layers.

15. The transistor of Claim 10, further comprising a conductive contact layer disposed on a top surface of the emitter contact region.

-13-