JP2007531054A - マスクをエッチングするためのシステムおよび方法 - Google Patents

マスクをエッチングするためのシステムおよび方法 Download PDF

Info

Publication number
JP2007531054A
JP2007531054A JP2007506163A JP2007506163A JP2007531054A JP 2007531054 A JP2007531054 A JP 2007531054A JP 2007506163 A JP2007506163 A JP 2007506163A JP 2007506163 A JP2007506163 A JP 2007506163A JP 2007531054 A JP2007531054 A JP 2007531054A
Authority
JP
Japan
Prior art keywords
layer
critical dimension
trim amount
pattern
variable parameter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007506163A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007531054A5 (https=
Inventor
ホンギュ・ユエ
朝夫 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of JP2007531054A publication Critical patent/JP2007531054A/ja
Publication of JP2007531054A5 publication Critical patent/JP2007531054A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70681—Metrology strategies
    • G03F7/706831—Recipe selection or optimisation, e.g. select or optimise recipe parameters such as wavelength, polarisation or illumination modes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/706835—Metrology information management or control
    • G03F7/706839—Modelling, e.g. modelling scattering or solving inverse problems
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Drying Of Semiconductors (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
JP2007506163A 2004-03-31 2005-02-08 マスクをエッチングするためのシステムおよび方法 Pending JP2007531054A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/813,570 US6893975B1 (en) 2004-03-31 2004-03-31 System and method for etching a mask
PCT/US2005/004070 WO2005104217A2 (en) 2004-03-31 2005-02-08 System and method for etching a mask

Publications (2)

Publication Number Publication Date
JP2007531054A true JP2007531054A (ja) 2007-11-01
JP2007531054A5 JP2007531054A5 (https=) 2008-02-28

Family

ID=34574882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007506163A Pending JP2007531054A (ja) 2004-03-31 2005-02-08 マスクをエッチングするためのシステムおよび方法

Country Status (7)

Country Link
US (2) US6893975B1 (https=)
EP (1) EP1730769B1 (https=)
JP (1) JP2007531054A (https=)
KR (1) KR101142709B1 (https=)
CN (1) CN100511621C (https=)
TW (1) TWI270121B (https=)
WO (1) WO2005104217A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011040757A (ja) * 2009-08-17 2011-02-24 Tokyo Electron Ltd 六フッ化硫黄（ｓｆ６）および炭化水素ガスを用いた反射防止層のパターニング方法

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7323417B2 (en) * 2004-09-21 2008-01-29 Molecular Imprints, Inc. Method of forming a recessed structure employing a reverse tone process
US8075732B2 (en) * 2004-11-01 2011-12-13 Cymer, Inc. EUV collector debris management
US7292906B2 (en) * 2004-07-14 2007-11-06 Tokyo Electron Limited Formula-based run-to-run control
US7547504B2 (en) * 2004-09-21 2009-06-16 Molecular Imprints, Inc. Pattern reversal employing thick residual layers
US7205244B2 (en) * 2004-09-21 2007-04-17 Molecular Imprints Patterning substrates employing multi-film layers defining etch-differential interfaces
US7291285B2 (en) * 2005-05-10 2007-11-06 International Business Machines Corporation Method and system for line-dimension control of an etch process
US20070077763A1 (en) * 2005-09-30 2007-04-05 Molecular Imprints, Inc. Deposition technique to planarize a multi-layer structure
US7932181B2 (en) * 2006-06-20 2011-04-26 Lam Research Corporation Edge gas injection for critical dimension uniformity improvement
CN101296554B (zh) * 2008-06-19 2011-01-26 友达光电股份有限公司 等离子体处理装置及其上电极板
US8039399B2 (en) * 2008-10-09 2011-10-18 Micron Technology, Inc. Methods of forming patterns utilizing lithography and spacers
US8334083B2 (en) 2011-03-22 2012-12-18 Tokyo Electron Limited Etch process for controlling pattern CD and integrity in multi-layer masks
KR20160044545A (ko) * 2013-08-27 2016-04-25 도쿄엘렉트론가부시키가이샤 하드마스크를 측면으로 트리밍하기 위한 방법
US9159561B2 (en) 2013-12-26 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method for overcoming broken line and photoresist scum issues in tri-layer photoresist patterning
CN105609415B (zh) * 2015-12-25 2018-04-03 中国科学院微电子研究所 一种刻蚀方法
KR102576706B1 (ko) * 2016-04-15 2023-09-08 삼성전자주식회사 반도체 소자의 제조 방법
KR102257919B1 (ko) * 2017-02-24 2021-05-31 에이에스엠엘 네델란즈 비.브이. 에치 바이어스 특성 묘사 및 그 사용 방법
CN109950140B (zh) * 2019-04-18 2021-11-05 上海华力微电子有限公司 一种自对准双层图形的形成方法
KR102828894B1 (ko) * 2020-11-30 2025-07-04 주식회사 엘지화학 애노드 표면 특성 및 퇴화 분석 방법
KR102884223B1 (ko) * 2020-11-30 2025-11-10 주식회사 엘지화학 캐소드 코팅 성분 분석 방법
KR102765574B1 (ko) * 2020-11-30 2025-02-12 주식회사 엘지화학 애노드 표면 피막 분석 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02303022A (ja) * 1989-04-28 1990-12-17 Internatl Business Mach Corp <Ibm> パターン形成方法
JP2002217170A (ja) * 2001-01-16 2002-08-02 Semiconductor Leading Edge Technologies Inc 微細パターンの形成方法、半導体装置の製造方法および半導体装置
JP2004022747A (ja) * 2002-06-14 2004-01-22 Hitachi Ltd エッチング処理装置及び処理方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3388986B2 (ja) * 1996-03-08 2003-03-24 株式会社東芝 露光用マスク及びその製造方法
US5926690A (en) * 1997-05-28 1999-07-20 Advanced Micro Devices, Inc. Run-to-run control process for controlling critical dimensions
KR100881472B1 (ko) * 1999-02-04 2009-02-05 어플라이드 머티어리얼스, 인코포레이티드 소정 기판 상에 놓여져 있는 패턴화된 마스크 표면 위로 적층 구조물을 증착하기 위한 방법
US6235609B1 (en) * 2000-04-03 2001-05-22 Philips Electronics North America Corp. Method for forming isolation areas with improved isolation oxide
US6926843B2 (en) * 2000-11-30 2005-08-09 International Business Machines Corporation Etching of hard masks
US20030092281A1 (en) * 2001-11-13 2003-05-15 Chartered Semiconductors Manufactured Limited Method for organic barc and photoresist trimming process
US6858361B2 (en) * 2002-03-01 2005-02-22 David S. L. Mui Methodology for repeatable post etch CD in a production tool
US6716570B2 (en) * 2002-05-23 2004-04-06 Institute Of Microelectronics Low temperature resist trimming process
CN1285968C (zh) * 2002-06-14 2006-11-22 联华电子股份有限公司 图案转移的方法
US6849151B2 (en) * 2002-08-07 2005-02-01 Michael S. Barnes Monitoring substrate processing by detecting reflectively diffracted light
US20050081781A1 (en) * 2003-10-17 2005-04-21 Taiwan Semiconductor Manufacturing Co. Fully dry, Si recess free process for removing high k dielectric layer
US7094613B2 (en) * 2003-10-21 2006-08-22 Applied Materials, Inc. Method for controlling accuracy and repeatability of an etch process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02303022A (ja) * 1989-04-28 1990-12-17 Internatl Business Mach Corp <Ibm> パターン形成方法
JP2002217170A (ja) * 2001-01-16 2002-08-02 Semiconductor Leading Edge Technologies Inc 微細パターンの形成方法、半導体装置の製造方法および半導体装置
JP2004022747A (ja) * 2002-06-14 2004-01-22 Hitachi Ltd エッチング処理装置及び処理方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011040757A (ja) * 2009-08-17 2011-02-24 Tokyo Electron Ltd 六フッ化硫黄（ｓｆ６）および炭化水素ガスを用いた反射防止層のパターニング方法

Also Published As

Publication number Publication date
CN1906747A (zh) 2007-01-31
EP1730769A2 (en) 2006-12-13
EP1730769B1 (en) 2016-07-06
KR101142709B1 (ko) 2012-05-03
WO2005104217A3 (en) 2005-12-29
US20050221619A1 (en) 2005-10-06
TWI270121B (en) 2007-01-01
KR20070005921A (ko) 2007-01-10
TW200537598A (en) 2005-11-16
WO2005104217A2 (en) 2005-11-03
US6893975B1 (en) 2005-05-17
CN100511621C (zh) 2009-07-08

Similar Documents

Publication Publication Date Title
JP2007531054A (ja) マスクをエッチングするためのシステムおよび方法
KR100989107B1 (ko) 다층 포토레지스트 건식 현상을 위한 방법 및 장치
US7846645B2 (en) Method and system for reducing line edge roughness during pattern etching
CN101366100B (zh) 用于相对于硅选择性刻蚀介电材料的方法和系统
US7465673B2 (en) Method and apparatus for bilayer photoresist dry development
US7291446B2 (en) Method and system for treating a hard mask to improve etch characteristics
US7172969B2 (en) Method and system for etching a film stack
US7732340B2 (en) Method for adjusting a critical dimension in a high aspect ratio feature
JP2007521665A (ja) 基材からフォトレジストを除去する方法及び装置
US7344991B2 (en) Method and apparatus for multilayer photoresist dry development
US8048325B2 (en) Method and apparatus for multilayer photoresist dry development
KR20070051846A (ko) 게이트 스택 에칭을 위한 방법 및 시스템
CN100423192C (zh) 用于多层光致抗蚀剂干式显影的方法和装置
US20050136666A1 (en) Method and apparatus for etching an organic layer
US7767926B2 (en) Method and system for dry development of a multi-layer mask using sidewall passivation and mask passivation

Legal Events

Date Code Title Description
RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20070910

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20070921

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080109

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080109

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100316

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100514

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100831