JP2007529899A5 - - Google Patents

Download PDF

Info

Publication number
JP2007529899A5
JP2007529899A5 JP2007503903A JP2007503903A JP2007529899A5 JP 2007529899 A5 JP2007529899 A5 JP 2007529899A5 JP 2007503903 A JP2007503903 A JP 2007503903A JP 2007503903 A JP2007503903 A JP 2007503903A JP 2007529899 A5 JP2007529899 A5 JP 2007529899A5
Authority
JP
Japan
Prior art keywords
hard mask
layer
exposing
substrate holder
approximately
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2007503903A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007529899A (ja
Filing date
Publication date
Priority claimed from US10/801,571 external-priority patent/US7291446B2/en
Application filed filed Critical
Publication of JP2007529899A publication Critical patent/JP2007529899A/ja
Publication of JP2007529899A5 publication Critical patent/JP2007529899A5/ja
Withdrawn legal-status Critical Current

Links

JP2007503903A 2004-03-17 2005-02-10 エッチング特性を改良するためのハードマスクを処理する方法およびシステム。 Withdrawn JP2007529899A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/801,571 US7291446B2 (en) 2004-03-17 2004-03-17 Method and system for treating a hard mask to improve etch characteristics
PCT/US2005/004047 WO2005091796A2 (en) 2004-03-17 2005-02-10 Method and system for treating a hard mask to improve etch characteristics

Publications (2)

Publication Number Publication Date
JP2007529899A JP2007529899A (ja) 2007-10-25
JP2007529899A5 true JP2007529899A5 (enExample) 2008-03-27

Family

ID=34986730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007503903A Withdrawn JP2007529899A (ja) 2004-03-17 2005-02-10 エッチング特性を改良するためのハードマスクを処理する方法およびシステム。

Country Status (4)

Country Link
US (1) US7291446B2 (enExample)
JP (1) JP2007529899A (enExample)
TW (1) TWI295815B (enExample)
WO (1) WO2005091796A2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7153780B2 (en) * 2004-03-24 2006-12-26 Intel Corporation Method and apparatus for self-aligned MOS patterning
US7497959B2 (en) 2004-05-11 2009-03-03 International Business Machines Corporation Methods and structures for protecting one area while processing another area on a chip
KR100694412B1 (ko) * 2006-02-24 2007-03-12 주식회사 하이닉스반도체 반도체소자의 미세패턴 형성방법
TW200806567A (en) * 2006-07-26 2008-02-01 Touch Micro System Tech Method of deep etching
KR100829603B1 (ko) * 2006-11-23 2008-05-14 삼성전자주식회사 에어 갭을 갖는 반도체 소자의 제조 방법
JP2009200095A (ja) * 2008-02-19 2009-09-03 Tokyo Electron Ltd 薄膜およびその薄膜を用いた半導体装置の製造方法
US8980706B2 (en) * 2008-09-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Double treatment on hard mask for gate N/P patterning
JP5466468B2 (ja) * 2009-10-05 2014-04-09 旭化成イーマテリアルズ株式会社 ドライエッチング方法
US9058983B2 (en) 2013-06-17 2015-06-16 International Business Machines Corporation In-situ hardmask generation
US9229326B2 (en) * 2014-03-14 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US10043672B2 (en) * 2016-03-29 2018-08-07 Lam Research Corporation Selective self-aligned patterning of silicon germanium, germanium and type III/V materials using a sulfur-containing mask
US10690821B1 (en) * 2018-12-14 2020-06-23 Applied Materials, Inc. Methods of producing slanted gratings
US11424123B2 (en) * 2020-02-25 2022-08-23 Tokyo Electron Limited Forming a semiconductor feature using atomic layer etch
KR20210126214A (ko) * 2020-04-10 2021-10-20 에스케이하이닉스 주식회사 반도체 장치 제조방법
JP7773277B2 (ja) * 2021-04-14 2025-11-19 東京エレクトロン株式会社 基板処理方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4493855A (en) * 1982-12-23 1985-01-15 International Business Machines Corporation Use of plasma polymerized organosilicon films in fabrication of lift-off masks
JPH0775226B2 (ja) * 1990-04-10 1995-08-09 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン プラズマ処理方法及び装置
US6316167B1 (en) * 2000-01-10 2001-11-13 International Business Machines Corporation Tunabale vapor deposited materials as antireflective coatings, hardmasks and as combined antireflective coating/hardmasks and methods of fabrication thereof and application thereof
US7816188B2 (en) * 2001-07-30 2010-10-19 Sandisk 3D Llc Process for fabricating a dielectric film using plasma oxidation
JP2003209046A (ja) * 2002-01-16 2003-07-25 Mitsubishi Electric Corp レジストパターン形成方法および半導体装置の製造方法
US6984529B2 (en) * 2003-09-10 2006-01-10 Infineon Technologies Ag Fabrication process for a magnetic tunnel junction device

Similar Documents

Publication Publication Date Title
JP2007529899A5 (enExample)
JP2010534935A5 (enExample)
JP2008277748A5 (enExample)
JP2010219106A5 (enExample)
JP2019096877A5 (enExample)
JP2011505589A5 (enExample)
TWI364818B (en) Method for fabricating semiconductor device
TW201237934A (en) Sidewall image transfer pitch doubling and inline critical dimension slimming
JP2008547237A5 (enExample)
JP2002023340A5 (enExample)
JP2012142065A5 (enExample)
CN115893305A (zh) 一种改善Lift-Off工艺图形异常的方法
WO2007126445A3 (en) Method and system for patterning a dielectric film
JP2006516364A5 (enExample)
CN104813402B (zh) 用于hdd位元图案化介质图案转印的图案强化
JP2006503185A5 (enExample)
JP2007017987A5 (enExample)
JPS5945443A (ja) クロム・マスクの製造方法
JP2005513764A5 (enExample)
JP2021028959A5 (enExample)
TWI252536B (en) Apparatus for processing substrate and method of doing the same
JP2005256090A5 (enExample)
TWI389195B (zh) A substrate for processing a substrate, and a method of processing a substrate
JP2008042174A (ja) マスクパターン形成方法
TW201214552A (en) Method for high aspect ratio patterning in a spin-on layer