JP2006516364A5 - - Google Patents

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Publication number
JP2006516364A5
JP2006516364A5 JP2006501001A JP2006501001A JP2006516364A5 JP 2006516364 A5 JP2006516364 A5 JP 2006516364A5 JP 2006501001 A JP2006501001 A JP 2006501001A JP 2006501001 A JP2006501001 A JP 2006501001A JP 2006516364 A5 JP2006516364 A5 JP 2006516364A5
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JP
Japan
Prior art keywords
thin film
substrate
disposable
dimension
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006501001A
Other languages
English (en)
Japanese (ja)
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JP2006516364A (ja
Filing date
Publication date
Priority claimed from US10/346,263 external-priority patent/US6858542B2/en
Application filed filed Critical
Publication of JP2006516364A publication Critical patent/JP2006516364A/ja
Publication of JP2006516364A5 publication Critical patent/JP2006516364A5/ja
Pending legal-status Critical Current

Links

JP2006501001A 2003-01-17 2004-01-16 小さなフィーチャーを生成する半導体製造方法 Pending JP2006516364A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/346,263 US6858542B2 (en) 2003-01-17 2003-01-17 Semiconductor fabrication method for making small features
PCT/US2004/001219 WO2004065934A2 (en) 2003-01-17 2004-01-16 Semiconductor fabrication method for making small features

Publications (2)

Publication Number Publication Date
JP2006516364A JP2006516364A (ja) 2006-06-29
JP2006516364A5 true JP2006516364A5 (enExample) 2007-02-08

Family

ID=32712103

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006501001A Pending JP2006516364A (ja) 2003-01-17 2004-01-16 小さなフィーチャーを生成する半導体製造方法

Country Status (6)

Country Link
US (1) US6858542B2 (enExample)
EP (1) EP1588219A2 (enExample)
JP (1) JP2006516364A (enExample)
KR (1) KR20050094438A (enExample)
TW (1) TWI336106B (enExample)
WO (1) WO2004065934A2 (enExample)

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US20040144585A1 (en) * 2003-01-24 2004-07-29 Vasser Paul M. Human powered golf cart with auxiliary power source
US7473644B2 (en) * 2004-07-01 2009-01-06 Micron Technology, Inc. Method for forming controlled geometry hardmasks including subresolution elements
TWI424498B (zh) * 2006-03-31 2014-01-21 Applied Materials Inc 用以改良介電薄膜之階梯覆蓋與圖案負載的方法
US8367303B2 (en) * 2006-07-14 2013-02-05 Micron Technology, Inc. Semiconductor device fabrication and dry develop process suitable for critical dimension tunability and profile control
US8563431B2 (en) * 2006-08-25 2013-10-22 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7973413B2 (en) * 2007-08-24 2011-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate via for semiconductor device
US20090057907A1 (en) * 2007-08-30 2009-03-05 Ming-Tzong Yang Interconnection structure
US7901852B2 (en) * 2008-02-29 2011-03-08 Freescale Semiconductor, Inc. Metrology of bilayer photoresist processes
US20100051896A1 (en) * 2008-09-02 2010-03-04 Samsung Electronics Co., Ltd. Variable resistance memory device using a channel-shaped variable resistance pattern
JP2010135624A (ja) * 2008-12-05 2010-06-17 Tokyo Electron Ltd 半導体装置の製造方法
KR20100082604A (ko) * 2009-01-09 2010-07-19 삼성전자주식회사 가변저항 메모리 장치 및 그의 형성 방법
KR101617381B1 (ko) 2009-12-21 2016-05-02 삼성전자주식회사 가변 저항 메모리 장치 및 그 형성 방법
US9159581B2 (en) 2012-11-27 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a semiconductor device using a bottom antireflective coating (BARC) layer
CN105499069B (zh) * 2014-10-10 2019-03-08 住友重机械工业株式会社 膜形成装置及膜形成方法
KR102379165B1 (ko) 2015-08-17 2022-03-25 삼성전자주식회사 Tsv 구조를 구비한 집적회로 소자 및 그 제조 방법
US10867842B2 (en) * 2018-10-31 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for shrinking openings in forming integrated circuits

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US4061530A (en) * 1976-07-19 1977-12-06 Fairchild Camera And Instrument Corporation Process for producing successive stages of a charge coupled device
EP0263220B1 (en) * 1986-10-08 1992-09-09 International Business Machines Corporation Method of forming a via-having a desired slope in a photoresist masked composite insulating layer
JP3001607B2 (ja) * 1989-04-24 2000-01-24 シーメンス、アクチエンゲゼルシヤフト 二層法における寸法安定な構造転写方法
US5196376A (en) * 1991-03-01 1993-03-23 Polycon Corporation Laser lithography for integrated circuit and integrated circuit interconnect manufacture
KR940010315B1 (ko) * 1991-10-10 1994-10-22 금성 일렉트론 주식회사 반도체 소자의 미세 패턴 형성 방법
US5320981A (en) * 1993-08-10 1994-06-14 Micron Semiconductor, Inc. High accuracy via formation for semiconductor devices
US5750441A (en) * 1996-05-20 1998-05-12 Micron Technology, Inc. Mask having a tapered profile used during the formation of a semiconductor device
US6251734B1 (en) * 1998-07-01 2001-06-26 Motorola, Inc. Method for fabricating trench isolation and trench substrate contact
US6432832B1 (en) * 1999-06-30 2002-08-13 Lam Research Corporation Method of improving the profile angle between narrow and wide features
US6313019B1 (en) * 2000-08-22 2001-11-06 Advanced Micro Devices Y-gate formation using damascene processing
US6645677B1 (en) * 2000-09-18 2003-11-11 Micronic Laser Systems Ab Dual layer reticle blank and manufacturing process
US6548347B2 (en) * 2001-04-12 2003-04-15 Micron Technology, Inc. Method of forming minimally spaced word lines
US6541360B1 (en) * 2001-04-30 2003-04-01 Advanced Micro Devices, Inc. Bi-layer trim etch process to form integrated circuit gate structures
US6649517B2 (en) * 2001-05-18 2003-11-18 Chartered Semiconductor Manufacturing Ltd. Copper metal structure for the reduction of intra-metal capacitance
JP2002353195A (ja) * 2001-05-23 2002-12-06 Sony Corp 半導体装置の製造方法
US6559048B1 (en) * 2001-05-30 2003-05-06 Lsi Logic Corporation Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning
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