JP2006516364A - 小さなフィーチャーを生成する半導体製造方法 - Google Patents
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/976—Temporary protective layer
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Abstract
Description
本発明の好ましい実施態様はここに詳細に言及され、その実施例は添付の図面に例示されている。図面は簡略化されており、尺度は正しくはないことは留意されるべきである。以下の説明は前記例示した実施態様に言及しているが、これらの実施態様は、例として提
示されるのであって、限定を目的としたものではないことは理解されるべきである。以下の詳細な説明は、添付の特許請求の範囲にて定義されている本発明の精神及び範囲に属する全ての改変、代替、及び等価なるものを包含することを意図している。
SiO2)又は炭酸化酸化珪素(SiCOH)のような電気絶縁材料を有してよい。誘電体層106は同様に、誘電体層106の上方及び下方に配置されている、一組の相互接続(図示せず)の間のILDとして作用する。層106を酸化珪素とする実施態様において、前記酸化珪素は、オルソ珪酸テトラエチル(TEOS)の分解、シランと酸素との反応、ジクロロシランと亜酸化窒素との反応、又は、他の適切なCVD酸化技術によるCVDによって形成され得る。層106がSiCOHである実施形態は、約3.0未満の低い誘電率を有する材料である低Kの誘電体として採用されてよく、これは層内及び層間の容量性カップリング効果を減じるのに望ましい。
することによって、おおよそ40から70nmのフィーチャーサイズの縮小が得られる。この様に、ここに開示されたBLRドライ現像処理工程技術を用いて、約170nmの印刷寸法(参照番号124)と、約105nmの最終の、即ち、より小さい寸法126とを有するテーパー状の側壁ビア120を生成することができる。
本発明の中に含まれると解される。
Claims (10)
- 半導体基板上に使い捨て薄膜を形成する工程と、
前記使い捨て薄膜上のフォトレジスト薄膜に、印刷寸法を有するフィーチャーを画定する工程と、
傾斜した側壁を有することを特徴とする空孔を形成するように、前記印刷フィーチャーの下方に位置する前記使い捨て薄膜を処理する工程とを備え、基板に最も近接した位置における前記空孔の寸法は、前記印刷寸法よりも小さいことを特徴とする半導体製造方法。 - 前記フォトレジスト薄膜は、約500から3000オングストロームの厚さを有する珪素含有フォトレジストを含み、前記フォトレジスト層の珪素含量は約6から15重量パーセントの範囲にあり、前記使い捨て薄膜は約3500から15000オングストロームの厚さを有するポリマー層を含む、請求項1に記載の方法。
- 前記使い捨て薄膜を処理する工程は、前記薄膜を高密度低圧プラズマに暴露する工程を備え、前記プラズマは窒素(N2)プラズマであり、前記半導体基板は、前記使い捨て薄膜の処理工程中に10℃未満の温度に維持されている、請求項1に記載の方法。
- 半導体基板上に像形成層及び下層を含む二重層レジストを形成する工程と、
印刷寸法を有する印刷フィーチャーを形成するように、前記像形成層をパターニングする工程と、
下方に位置する基板に最も近接した位置において、前記印刷寸法よりも小さい完成寸法を有する空孔を、前記下層に形成するように前記下層を処理する工程と、
前記下層の空孔の完成寸法によって決定される寸法を有する集積回路フィーチャーを前記基板に形成するように、前記下層をエッチング・マスクとして用いて前記基板をエッチングする工程とを備えることを特徴とする半導体製造方法。 - 前記像形成層は、約500から3000オングストロームの厚さを有する珪素含有フォトレジストを含み、前記像形成層の珪素含量は約6から15重量パーセントの範囲にあり、前記下層は約3500から15000オングストロームの厚さを有するポリマーを含む、請求項4に記載の方法。
- 前記下層を処理する工程は、プラズマリアクタ槽にて前記ウェハをN2系プラズマに暴露する工程を備え、N2は前記下層の処理工程中に前記槽に導入される唯一のガスであり、前記半導体基板は10℃未満の温度に維持され、前記リアクタは15mTより小さい圧力に維持されている、請求項4に記載の方法。
- 前記下層の空孔は傾斜したほぼ直線的な側壁を備え、該側壁は前記基板の上面に対して約70°から89°の傾斜を有する、請求項4に記載の方法。
- 半導体基板上に使い捨て薄膜を形成する工程と、
前記使い捨て薄膜上のフォトレジスト薄膜に印刷寸法を有する開口を画定する工程と、
傾斜した側壁を特徴とする空孔を形成するように、前記開口の下方に位置する前記使い捨て薄膜を高密度窒素プラズマにて処理する工程であって、前記基板に最も近接した位置における前記空孔の寸法は、前記印刷寸法よりも小さい工程と、
前記基板に最も近接した位置における前記空孔の寸法によって決定される寸法を有する集積回路フィーチャーを前記基板に形成するように、前記処理された使い捨て層をエッチング・マスクとして用いることにより、前記基板をエッチングする工程とを備えることを特徴とする、半導体製造方法。 - 前記使い捨て薄膜はポリマー薄膜を含み、前記フォトレジスト薄膜は珪素含有フォトレジストを含み、前記珪素含有フォトレジストの厚さは約500から3000オングストロームの範囲にあり、前記ポリマー薄膜の厚さは3500から15000オングストロームの範囲にある、請求項8に記載の方法。
- 前記使い捨て層を処理する工程は、1011イオン/cm3より大きいプラズマ密度で、15mTより小さい圧力で、10℃より低い温度のプラズマにて、前記使い捨て層を処理する工程であることを更に特徴とする請求項8に記載の方法。
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US10/346,263 US6858542B2 (en) | 2003-01-17 | 2003-01-17 | Semiconductor fabrication method for making small features |
PCT/US2004/001219 WO2004065934A2 (en) | 2003-01-17 | 2004-01-16 | Semiconductor fabrication method for making small features |
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JP2010135624A (ja) * | 2008-12-05 | 2010-06-17 | Tokyo Electron Ltd | 半導体装置の製造方法 |
JP2016078019A (ja) * | 2014-10-10 | 2016-05-16 | 住友重機械工業株式会社 | 膜形成装置及び膜形成方法 |
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2003
- 2003-01-17 US US10/346,263 patent/US6858542B2/en not_active Expired - Lifetime
- 2003-12-12 TW TW092135222A patent/TWI336106B/zh not_active IP Right Cessation
-
2004
- 2004-01-16 KR KR1020057013155A patent/KR20050094438A/ko not_active Application Discontinuation
- 2004-01-16 EP EP04703010A patent/EP1588219A2/en not_active Withdrawn
- 2004-01-16 WO PCT/US2004/001219 patent/WO2004065934A2/en active Application Filing
- 2004-01-16 JP JP2006501001A patent/JP2006516364A/ja active Pending
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WO2002023272A1 (en) * | 2000-09-18 | 2002-03-21 | Micronic Laser Systems Ab | Dual layer reticle blank and manufacturing process |
JP2002353195A (ja) * | 2001-05-23 | 2002-12-06 | Sony Corp | 半導体装置の製造方法 |
Cited By (2)
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JP2010135624A (ja) * | 2008-12-05 | 2010-06-17 | Tokyo Electron Ltd | 半導体装置の製造方法 |
JP2016078019A (ja) * | 2014-10-10 | 2016-05-16 | 住友重機械工業株式会社 | 膜形成装置及び膜形成方法 |
Also Published As
Publication number | Publication date |
---|---|
TWI336106B (en) | 2011-01-11 |
US20040142576A1 (en) | 2004-07-22 |
WO2004065934A8 (en) | 2005-08-04 |
TW200507103A (en) | 2005-02-16 |
EP1588219A2 (en) | 2005-10-26 |
KR20050094438A (ko) | 2005-09-27 |
WO2004065934A2 (en) | 2004-08-05 |
WO2004065934A3 (en) | 2005-03-10 |
US6858542B2 (en) | 2005-02-22 |
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