JP2007527113A - 二軸圧縮歪みの状態の<110>Si中の電子および正孔移動度の増加(シリコン含有半導体材料および形成方法) - Google Patents
二軸圧縮歪みの状態の<110>Si中の電子および正孔移動度の増加(シリコン含有半導体材料および形成方法) Download PDFInfo
- Publication number
- JP2007527113A JP2007527113A JP2006549292A JP2006549292A JP2007527113A JP 2007527113 A JP2007527113 A JP 2007527113A JP 2006549292 A JP2006549292 A JP 2006549292A JP 2006549292 A JP2006549292 A JP 2006549292A JP 2007527113 A JP2007527113 A JP 2007527113A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- forming
- semiconductor material
- containing layer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 99
- 239000000463 material Substances 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 18
- 239000010703 silicon Substances 0.000 title claims abstract description 18
- 230000006835 compression Effects 0.000 title claims description 39
- 238000007906 compression Methods 0.000 title claims description 39
- 230000015572 biosynthetic process Effects 0.000 title claims description 9
- 239000013078 crystal Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 167
- 239000000758 substrate Substances 0.000 claims description 63
- 230000008569 process Effects 0.000 claims description 49
- 229910021426 porous silicon Inorganic materials 0.000 claims description 44
- 238000002955 isolation Methods 0.000 claims description 29
- 238000000137 annealing Methods 0.000 claims description 23
- 238000002048 anodisation reaction Methods 0.000 claims description 14
- 238000012546 transfer Methods 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 238000001816 cooling Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 8
- 239000012298 atmosphere Substances 0.000 claims description 7
- 239000002344 surface layer Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 claims description 5
- 229910001634 calcium fluoride Inorganic materials 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 4
- 239000010980 sapphire Substances 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 2
- 238000001459 lithography Methods 0.000 claims description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 2
- 238000005868 electrolysis reaction Methods 0.000 claims 1
- 238000009499 grossing Methods 0.000 claims 1
- 230000037230 mobility Effects 0.000 abstract description 31
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 235000012431 wafers Nutrition 0.000 description 16
- 239000011148 porous material Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 230000007423 decrease Effects 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 5
- 238000013459 approach Methods 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 3
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- 238000003776 cleavage reaction Methods 0.000 description 3
- 239000011247 coating layer Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000007017 scission Effects 0.000 description 3
- 239000004094 surface-active agent Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910008065 Si-SiO Inorganic materials 0.000 description 1
- 229910006405 Si—SiO Inorganic materials 0.000 description 1
- 230000005535 acoustic phonon Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- BDERNNFJNOPAEC-UHFFFAOYSA-N propan-1-ol Chemical compound CCCO BDERNNFJNOPAEC-UHFFFAOYSA-N 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/109—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN heterojunction type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Element Separation (AREA)
- Chemical Vapour Deposition (AREA)
- Formation Of Insulating Films (AREA)
- Recrystallisation Techniques (AREA)
- Luminescent Compositions (AREA)
- Photoreceptors In Electrophotography (AREA)
- Polymers With Sulfur, Phosphorus Or Metals In The Main Chain (AREA)
Abstract
【解決手段】半導体材料は<110>結晶配向および二軸圧縮歪みを有するSi含有層を備える。本明細書では、用語「二軸圧縮応力」は、半導体材料の製造時にSi含有層に誘起される縦圧縮応力および横応力によって生じる総応力を記載するために用いられる。本発明の他の側面は、本発明の半導体材料を形成する方法に関する。本発明の方法は、シリコン含有<110>層を準備する工程、およびシリコン含有<110>層中に二軸圧縮歪みを発生させる工程を含む。
【選択図】図2
Description
International Technology Roadmap for Semiconductors(ITRS),2002 Update,"Grand Challenges." Proc.IEEE,Vol.89,No.3,March 2001 Special Issue. M.Yang et al.,IDEM Technical Digest,p.453(2003) M.V.Fischetti and S.E.Laux,J.Appl.Phys.Vol.80,2234(1996) T.Yonehara and K.Sakaguchi,"ELTRAN(SOI Epi Wafer) Technology",Science of SOI,Chapter 2,Section 2,(4/19/2000)
<110>Si含有基板中に、上部表面を有する少なくとも一つの多孔質(porous)Si層を形成する工程、
上部表面をアニールし、これによって、非多孔質表面層を形成する工程、
非多孔質表面層上に、<110>配向を有する結晶性エピタキシャルSi含有層を形成し、それによって、転写構造体(transfer structure)を形成する工程、
最高デバイス動作温度より高い温度で、Siより高い熱膨張係数を有する材料に転写構造体をボンディングしてボンディング構造体を準備する工程、
機械的に弱い界面が前記少なくとも一つの多孔質Si層に形成されるように、ボンディング構造体を冷却し、それによって、前記ボンディング構造体を前記界面で劈開させる工程、および
劈開された構造体から、少なくとも一つの多孔質Si層の残存部分を除去し、前記材料の上に<110>配向を有する結晶性エピタキシャルSi含有層を少なくとも備える半導体材料を提供し、前記結晶性エピタキシャルSi含有層に二軸圧縮歪みを生じさせる工程。
<110>結晶配向を有するSi含有層の表面中に、少なくとも一つの多重接続トレンチ分離領域を形成する工程、および
前記少なくとも一つの多重接続トレンチ分離領域で囲まれるSi含有層の露出部分上に、少なくとも一つのCMOSデバイスを形成し、前記少なくとも一つの多重接続トレンチ分離領域によって、前記Si含有層中に二軸圧縮歪みを発生させる工程。
<110>結晶配向を有するSi含有層を備え、その上に少なくとも一つのCMOSデバイスを有する構造体を準備する工程、および
前記構造体上に圧縮ライナー(liner)を形成し、前記圧縮ライナーによって、CMOSデバイスのゲートの下で前記Si含有層が二軸圧縮歪み状態にされる工程。
<110>結晶配向を有するSi含有層の表面中に、少なくとも一つの多重接続トレンチ分離領域を形成する工程、
前記少なくとも一つの多重接続トレンチ分離領域で囲まれるSi含有層の露出部分上に、少なくとも一つのCMOSデバイスを形成する工程、および
前記Si含有層上に圧縮ライナーを形成し、前記圧縮ライナーおよび前記少なくとも一つの多重接続トレンチ分離領域によって、前記Si含有層が二軸圧縮歪み状態にされる工程。
Claims (40)
- <110>結晶配向を有するシリコン含有層を備え、前記シリコン含有層は二軸圧縮歪み状態にある半導体材料。
- 前記二軸圧縮歪みは約0.2%より大きい、請求項1に記載の半導体材料。
- 前記二軸圧縮歪みは約0.5%より大きい、請求項2に記載の半導体材料。
- 前記シリコン含有層は、酸化物層の表面または基板の表面の上に配置される、請求項1に記載の半導体材料。
- 前記酸化物層は基板上に配置される、請求項4に記載の半導体材料。
- 前記基板は、Siの熱膨張係数より大きな熱膨張係数を有する、請求項5に記載の半導体材料。
- 前記基板は、サファイヤ、ゲルマニウムまたはフッ化カルシウムである、請求項6に記載の半導体材料。
- 前記基板は、Siの熱膨張係数より大きな熱膨張係数を有する、請求項4に記載の半導体材料。
- 前記基板は、サファイヤ、ゲルマニウムまたはフッ化カルシウムである、請求項8に記載の半導体材料。
- 前記シリコン含有層は、SiまたはSiGeを含む結晶性Si含有層である、請求項1に記載の半導体材料。
- 前記シリコン含有層は、少なくとも一つの多重接続トレンチ分離領域を備える基板である、請求項1に記載の半導体材料。
- 前記Si含有層は、表面上に圧縮ライナーを備える基板である、請求項1に記載の半導体材料。
- 前記圧縮ライナーは窒化物含有材料を含む、請求項12に記載の半導体材料。
- 前記圧縮ライナーは、前記基板上に配置される金属酸化物半導体の露出表面上に配置される、請求項12に記載の半導体材料。
- 前記基板の表面に圧縮ライナーをさらに備える、請求項11の半導体材料。
- 前記圧縮ライナーは窒化物含有材料を含む、請求項15に記載の半導体材料。
- 前記圧縮ライナーは、前記基板上に配置される金属酸化物半導体の露出表面上に配置される、請求項15に記載の半導体材料。
- シリコン含有<110>層を準備する工程、および
前記シリコン含有<110>層中に二軸圧縮歪みを発生させる工程
を含む、シリコン含有半導体材料を形成するための方法。 - 前記二軸圧縮歪みを発生させる工程は、最上部表面を有する少なくとも一つの多孔質Si層を前記<110>Si含有層中に形成すること、前記最上部表面をアニールして非多孔質表面層を生成すること、前記非多孔質表面層上に<110>配向を有する結晶性エピタキシャルSi含有層を形成し、それによって、転写構造体を形成すること、Siより高い熱膨張係数を有する材料に最高デバイス動作温度より高い温度で前記転写構造体をボンディングしてボンディング構造体を提供すること、前記少なくとも一つの多孔質Si層に機械的に弱い界面が形成されるように前記ボンディング構造体を冷却し、それによって、前記ボンディング構造体を前記界面で劈開させること、および前記劈開された構造体から前記少なくとも一つの多孔質Si層の残存部分を除去すること、を含む請求項18に記載の方法。
- 前記少なくとも一つの多孔質Si層の形成は、電気分解による陽極酸化プロセスを含む、請求項19に記載の方法。
- 前記陽極酸化プロセスは、HF含有溶液を用いることを含む、請求項20に記載の方法。
- 前記アニールは、約900°から約1150℃の温度で実行される、請求項19に記載の方法。
- 前記結晶性エピタキシャルSi含有層の形成は、エピタキシャル成長プロセスを含む、請求項19に記載の方法。
- 前記エピタキシャル成長プロセスは、UHVCVDプロセスを含む、請求項23に記載の方法。
- ボンディングする前に前記結晶Si含有層上に酸化物層を形成することをさらに含む、請求項19に記載の方法。
- 前記ボンディングは、前記転写構造体と前記材料とを合わせること、任意選択で外力を加えること、および加熱することを含む、請求項19に記載の方法。
- 前記加熱は、約400°から約1000℃の温度で実行される、請求項26に記載の方法。
- 前記冷却は、約50℃/分以下の速度で実行される、請求項19に記載の方法。
- 前記除去は、ウェット・エッチング・プロセスを含む、請求項19に記載の方法。
- H2含有雰囲気中で約850°から約1100℃の温度でアニールすることによって、二軸圧縮歪み状態の前記結晶性エピタキシャルSi含有層を滑らかにすることをさらに含む、請求項19に記載の方法。
- 前記二軸圧縮歪みを発生させる工程は、前記Si含有層の表面中に少なくとも一つの多重接続トレンチ分離領域を形成すること、および前記少なくとも一つの多重接続トレンチ分離領域で囲まれる前記Si含有層の露出部分上に少なくとも一つのCMOSデバイスを形成することを含む、請求項18に記載の方法。
- 前記少なくとも一つの多重接続トレンチ分離領域の形成は、リソグラフィー、トレンチのエッチング、およびトレンチ誘電体材料による前記トレンチの充填を含む、請求項31に記載の方法。
- 各CMOSデバイスおよび前記Si含有層の少なくとも露出表面上に圧縮ライナーを形成することをさらに含む、請求項31に記載の方法。
- 前記圧縮ライナーは窒化物含有材料を含む、請求項33に記載の方法。
- 前記二軸圧縮歪みを発生させる工程は、前記Si含有層上に少なくとも一つのCMOSデバイスを形成することと、前記CMOSデバイスおよび前記Si含有層の露出表面上に圧縮ライナーを形成することとを含む、請求項18に記載の方法。
- 前記圧縮ライナーは窒化物含有材料を含む、請求項35に記載の方法。
- シリコン含有半導体材料を形成する方法であって、
最上部表面を有する少なくとも一つの多孔質Si層を<110>Si含有基板中に形成する工程と、
前記最上部表面をアニールして非多孔質表面層を形成する工程と、
<110>配向を有する結晶性エピタキシャルSi含有層を前記非多孔質表面層上に形成し、それによって、転写構造体を形成する工程と、
Siより高い熱膨張係数を有する材料に最終デバイス動作温度より高い温度で前記転写構造体をボンディングしてボンディング構造体を提供する工程と、
前記少なくとも一つの多孔質Si層に機械的に弱い界面が形成されるように前記ボンディング構造体を冷却し、それによって、前記ボンディング構造体を前記界面で劈開させる工程と、
前記劈開された構造体から前記少なくとも一つの多孔質Si層の残存部分を除去し、これによって、前記材料の上に<110>配向を有する前記結晶性エピタキシャルSi含有層を少なくとも備え、前記結晶性エピタキシャルSi含有層は二軸圧縮歪み状態の半導体材料を提供する工程と、
を含む方法。 - シリコン含有半導体材料を形成するための方法であって、
<110>結晶配向を有するSi含有層の表面中に少なくとも一つの多重接続トレンチ分離領域を形成する工程と、
前記少なくとも一つの多重接続トレンチ分離領域で囲まれる前記Si含有層の露出部分上に少なくとも一つのCMOSデバイスを形成する工程と、
を含み、前記少なくとも一つの多重接続トレンチ分離領域は、前記Si含有層中に二軸圧縮歪みを発生させる方法。 - シリコン含有半導体材料を形成するための方法であって、
<110>結晶配向を有するSi含有層を備える構造体を準備する工程であって、前記Si含有層はその上に少なくとも一つのCMOSデバイスを有する工程と、
前記構造体上に圧縮ライナーを形成する工程と、
を含み、前記圧縮ライナーによって、前記Si含有層が二軸圧縮歪み状態にされる方法。 - シリコン含有半導体材料を形成するための方法であって、
<110>結晶配向を有するSi含有層の表面中に少なくとも一つの多重接続トレンチ分離領域を形成する工程と、
前記少なくとも一つの多重接続トレンチ分離領域で囲まれる前記Si含有層の露出部分上に少なくとも一つのCMOSデバイスを形成する工程と、
前記Si含有層上に圧縮ライナーを形成する工程と、
を含み、前記圧縮ライナーおよび前記少なくとも一つの多重接続トレンチ分離領域によって、前記Si含有層が二軸圧縮歪み状態にされる方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US53491604P | 2004-01-07 | 2004-01-07 | |
US60/534,916 | 2004-01-07 | ||
US10/980,220 | 2004-11-03 | ||
US10/980,220 US7161169B2 (en) | 2004-01-07 | 2004-11-03 | Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain |
PCT/US2004/042179 WO2006057645A2 (en) | 2004-01-07 | 2004-12-15 | Enhancement of electron and hole mobilities in 110 under biaxial compressive strain |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2007527113A true JP2007527113A (ja) | 2007-09-20 |
JP2007527113A5 JP2007527113A5 (ja) | 2007-12-13 |
JP5190201B2 JP5190201B2 (ja) | 2013-04-24 |
Family
ID=34713837
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006549292A Expired - Fee Related JP5190201B2 (ja) | 2004-01-07 | 2004-12-15 | 二軸圧縮歪みの状態の<110>Si中の電子および正孔移動度の増加(シリコン含有半導体材料および形成方法) |
Country Status (8)
Country | Link |
---|---|
US (5) | US7161169B2 (ja) |
EP (1) | EP1702365B1 (ja) |
JP (1) | JP5190201B2 (ja) |
KR (1) | KR100961751B1 (ja) |
AT (1) | ATE450892T1 (ja) |
DE (1) | DE602004024448D1 (ja) |
TW (1) | TWI430329B (ja) |
WO (1) | WO2006057645A2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010206097A (ja) * | 2009-03-05 | 2010-09-16 | Toshiba Corp | 半導体素子及び半導体装置 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7217949B2 (en) * | 2004-07-01 | 2007-05-15 | International Business Machines Corporation | Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) |
US7271043B2 (en) * | 2005-01-18 | 2007-09-18 | International Business Machines Corporation | Method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels |
US8729635B2 (en) * | 2006-01-18 | 2014-05-20 | Macronix International Co., Ltd. | Semiconductor device having a high stress material layer |
US7572712B2 (en) | 2006-11-21 | 2009-08-11 | Chartered Semiconductor Manufacturing, Ltd. | Method to form selective strained Si using lateral epitaxy |
US7524740B1 (en) | 2008-04-24 | 2009-04-28 | International Business Machines Corporation | Localized strain relaxation for strained Si directly on insulator |
FR2966285B1 (fr) * | 2010-10-14 | 2013-09-06 | St Microelectronics Crolles 2 | Procédé de formation de circuits intégrés sur substrat semi conducteur contraint |
DE112011103811B4 (de) * | 2010-12-22 | 2015-08-20 | International Business Machines Corporation | Festkörpersorptionskühlung |
US20130050180A1 (en) | 2011-08-30 | 2013-02-28 | 5D Robotics, Inc. | Graphical Rendition of Multi-Modal Data |
US8895381B1 (en) * | 2013-08-15 | 2014-11-25 | International Business Machines Corporation | Method of co-integration of strained-Si and relaxed Si or strained SiGe FETs on insulator with planar and non-planar architectures |
CN110838435B (zh) * | 2019-10-14 | 2023-01-31 | 宁波大学 | 一种外延层转移方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1154756A (ja) * | 1997-07-30 | 1999-02-26 | Internatl Business Mach Corp <Ibm> | 絶縁体上の半導体のキャリア移動度を強化する構造 |
JP2000286418A (ja) * | 1999-03-30 | 2000-10-13 | Hitachi Ltd | 半導体装置および半導体基板 |
WO2002043151A1 (en) * | 2000-11-22 | 2002-05-30 | Hitachi, Ltd | Semiconductor device and method for fabricating the same |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5317069A (en) * | 1976-07-30 | 1978-02-16 | Fujitsu Ltd | Semiconductor device and its production |
JPH10107380A (ja) * | 1996-09-30 | 1998-04-24 | Toshiba Corp | 積層体のへき開方法 |
US20010020723A1 (en) * | 1998-07-07 | 2001-09-13 | Mark I. Gardner | Transistor having a transition metal oxide gate dielectric and method of making same |
JP4476390B2 (ja) * | 1998-09-04 | 2010-06-09 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6686300B2 (en) * | 2000-12-27 | 2004-02-03 | Texas Instruments Incorporated | Sub-critical-dimension integrated circuit features |
US6531739B2 (en) * | 2001-04-05 | 2003-03-11 | Peregrine Semiconductor Corporation | Radiation-hardened silicon-on-insulator CMOS device, and method of making the same |
JP2003017668A (ja) * | 2001-06-29 | 2003-01-17 | Canon Inc | 部材の分離方法及び分離装置 |
JP3782021B2 (ja) * | 2002-02-22 | 2006-06-07 | 株式会社東芝 | 半導体装置、半導体装置の製造方法、半導体基板の製造方法 |
AU2003237473A1 (en) * | 2002-06-07 | 2003-12-22 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US20030227057A1 (en) * | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
EP1396883A3 (en) * | 2002-09-04 | 2005-11-30 | Canon Kabushiki Kaisha | Substrate and manufacturing method therefor |
TWI333236B (en) * | 2002-12-02 | 2010-11-11 | Tadahiro Ohmi | Semiconductor device and method of manufacturing the same |
US7115480B2 (en) * | 2003-05-07 | 2006-10-03 | Micron Technology, Inc. | Micromechanical strained semiconductor by wafer bonding |
US20040222090A1 (en) * | 2003-05-07 | 2004-11-11 | Tim Scott | Carbon fiber and copper support for physical vapor deposition target assemblies |
FR2859312B1 (fr) * | 2003-09-02 | 2006-02-17 | Soitec Silicon On Insulator | Scellement metallique multifonction |
US7354815B2 (en) * | 2003-11-18 | 2008-04-08 | Silicon Genesis Corporation | Method for fabricating semiconductor devices using strained silicon bearing material |
JP4349151B2 (ja) * | 2004-02-26 | 2009-10-21 | トヨタ自動車株式会社 | 接触状態取得装置 |
-
2004
- 2004-11-03 US US10/980,220 patent/US7161169B2/en not_active Expired - Fee Related
- 2004-12-15 EP EP04822326A patent/EP1702365B1/en not_active Not-in-force
- 2004-12-15 WO PCT/US2004/042179 patent/WO2006057645A2/en active Application Filing
- 2004-12-15 KR KR1020067013491A patent/KR100961751B1/ko not_active IP Right Cessation
- 2004-12-15 JP JP2006549292A patent/JP5190201B2/ja not_active Expired - Fee Related
- 2004-12-15 AT AT04822326T patent/ATE450892T1/de not_active IP Right Cessation
- 2004-12-15 DE DE602004024448T patent/DE602004024448D1/de active Active
-
2005
- 2005-01-03 TW TW094100053A patent/TWI430329B/zh not_active IP Right Cessation
-
2006
- 2006-12-18 US US11/612,309 patent/US7314790B2/en not_active Expired - Fee Related
-
2007
- 2007-10-25 US US11/924,024 patent/US7462525B2/en active Active
- 2007-10-25 US US11/924,015 patent/US20080044987A1/en not_active Abandoned
-
2008
- 2008-05-06 US US12/115,731 patent/US7943486B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1154756A (ja) * | 1997-07-30 | 1999-02-26 | Internatl Business Mach Corp <Ibm> | 絶縁体上の半導体のキャリア移動度を強化する構造 |
JP2000286418A (ja) * | 1999-03-30 | 2000-10-13 | Hitachi Ltd | 半導体装置および半導体基板 |
WO2002043151A1 (en) * | 2000-11-22 | 2002-05-30 | Hitachi, Ltd | Semiconductor device and method for fabricating the same |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010206097A (ja) * | 2009-03-05 | 2010-09-16 | Toshiba Corp | 半導体素子及び半導体装置 |
US8013396B2 (en) | 2009-03-05 | 2011-09-06 | Kabushiki Kaisha Toshiba | Semiconductor component and semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
WO2006057645A3 (en) | 2006-11-30 |
KR20060127021A (ko) | 2006-12-11 |
WO2006057645A8 (en) | 2006-08-03 |
EP1702365A2 (en) | 2006-09-20 |
US20080044987A1 (en) | 2008-02-21 |
WO2006057645A2 (en) | 2006-06-01 |
EP1702365B1 (en) | 2009-12-02 |
US7161169B2 (en) | 2007-01-09 |
WO2006057645A9 (en) | 2006-09-14 |
US20050145837A1 (en) | 2005-07-07 |
US7314790B2 (en) | 2008-01-01 |
US20080044966A1 (en) | 2008-02-21 |
US20080206958A1 (en) | 2008-08-28 |
TW200616021A (en) | 2006-05-16 |
ATE450892T1 (de) | 2009-12-15 |
TWI430329B (zh) | 2014-03-11 |
JP5190201B2 (ja) | 2013-04-24 |
KR100961751B1 (ko) | 2010-06-07 |
US20070099367A1 (en) | 2007-05-03 |
US7943486B2 (en) | 2011-05-17 |
DE602004024448D1 (de) | 2010-01-14 |
US7462525B2 (en) | 2008-12-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7462525B2 (en) | Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain | |
Taraschi et al. | Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques | |
US7390725B2 (en) | Strained silicon on insulator from film transfer and relaxation by hydrogen implantation | |
US7915148B2 (en) | Method of producing a tensioned layer on a substrate | |
US6943087B1 (en) | Semiconductor on insulator MOSFET having strained silicon channel | |
US7592671B2 (en) | Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer | |
JP2010016390A (ja) | グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス | |
JP2009105427A (ja) | 半導体基板の製造方法 | |
KR20130034059A (ko) | 매립 절연 층과 결합된 응력기의 탄성 에지 이완을 사용하는 변형 반도체 | |
JP2006524426A5 (ja) | ||
JP2010040931A (ja) | 半導体基板の製造方法及び半導体基板 | |
CN100544022C (zh) | 具有<110>晶体取向含硅层的半导体材料及其形成方法 | |
US20050070070A1 (en) | Method of forming strained silicon on insulator | |
JP2005079215A (ja) | 半導体装置の製造方法 | |
JP2006253182A (ja) | 半導体装置および半導体装置の製造方法 | |
JP5278132B2 (ja) | 半導体装置の製造方法 | |
US20070010070A1 (en) | Fabrication of strained semiconductor-on-insulator (ssoi) structures by using strained insulating layers | |
JP2011009580A (ja) | 半導体装置の製造方法 | |
JP2006210810A (ja) | 半導体装置、半導体基板の製造方法および半導体装置の製造方法 | |
JP2006287006A (ja) | 半導体基板、半導体装置及びその製造法 | |
JP2007081031A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20071025 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20071025 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110909 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110927 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111129 |
|
RD12 | Notification of acceptance of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7432 Effective date: 20111129 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20111201 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120228 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120420 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120911 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121009 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130115 |
|
RD14 | Notification of resignation of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7434 Effective date: 20130115 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130128 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160201 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |