JP2007522699A5 - - Google Patents

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Publication number
JP2007522699A5
JP2007522699A5 JP2006547306A JP2006547306A JP2007522699A5 JP 2007522699 A5 JP2007522699 A5 JP 2007522699A5 JP 2006547306 A JP2006547306 A JP 2006547306A JP 2006547306 A JP2006547306 A JP 2006547306A JP 2007522699 A5 JP2007522699 A5 JP 2007522699A5
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JP
Japan
Prior art keywords
dsp
integrated circuit
dsp element
input
hardwired
Prior art date
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Application number
JP2006547306A
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English (en)
Japanese (ja)
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JP2007522699A (ja
JP4664311B2 (ja
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Priority claimed from PCT/US2004/043113 external-priority patent/WO2005066832A2/en
Publication of JP2007522699A publication Critical patent/JP2007522699A/ja
Publication of JP2007522699A5 publication Critical patent/JP2007522699A5/ja
Application granted granted Critical
Publication of JP4664311B2 publication Critical patent/JP4664311B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2006547306A 2003-12-29 2004-12-21 カスケード接続するｄｓｐスライスを備えた集積回路 Expired - Lifetime JP4664311B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US53328003P 2003-12-29 2003-12-29
US53318103P 2003-12-29 2003-12-29
US53315303P 2003-12-29 2003-12-29
PCT/US2004/043113 WO2005066832A2 (en) 2003-12-29 2004-12-21 Integrated circuit with cascading dsp slices

Publications (3)

Publication Number Publication Date
JP2007522699A JP2007522699A (ja) 2007-08-09
JP2007522699A5 true JP2007522699A5 (https=) 2008-02-14
JP4664311B2 JP4664311B2 (ja) 2011-04-06

Family

ID=34753688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006547306A Expired - Lifetime JP4664311B2 (ja) 2003-12-29 2004-12-21 カスケード接続するｄｓｐスライスを備えた集積回路

Country Status (4)

Country Link
EP (2) EP2306331B1 (https=)
JP (1) JP4664311B2 (https=)
CA (1) CA2548327C (https=)
WO (1) WO2005066832A2 (https=)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7853636B2 (en) 2003-12-29 2010-12-14 Xilinx, Inc. Digital signal processing circuit having a pattern detector circuit for convergent rounding
US7882165B2 (en) 2003-12-29 2011-02-01 Xilinx, Inc. Digital signal processing element having an arithmetic logic unit
US7840627B2 (en) 2003-12-29 2010-11-23 Xilinx, Inc. Digital signal processing circuit having input register blocks
US7480690B2 (en) 2003-12-29 2009-01-20 Xilinx, Inc. Arithmetic circuit with multiplexed addend inputs
US7849119B2 (en) 2003-12-29 2010-12-07 Xilinx, Inc. Digital signal processing circuit having a pattern detector circuit
US7860915B2 (en) 2003-12-29 2010-12-28 Xilinx, Inc. Digital signal processing circuit having a pattern circuit for determining termination conditions
US7865542B2 (en) 2003-12-29 2011-01-04 Xilinx, Inc. Digital signal processing block having a wide multiplexer
US7467177B2 (en) 2003-12-29 2008-12-16 Xilinx, Inc. Mathematical circuit with dynamic rounding
US7840630B2 (en) 2003-12-29 2010-11-23 Xilinx, Inc. Arithmetic logic unit circuit
US7467175B2 (en) 2003-12-29 2008-12-16 Xilinx, Inc. Programmable logic device with pipelined DSP slices
US7844653B2 (en) 2003-12-29 2010-11-30 Xilinx, Inc. Digital signal processing circuit having a pre-adder circuit
US7853634B2 (en) 2003-12-29 2010-12-14 Xilinx, Inc. Digital signal processing circuit having a SIMD circuit
US7567997B2 (en) 2003-12-29 2009-07-28 Xilinx, Inc. Applications of cascading DSP slices
US7870182B2 (en) 2003-12-29 2011-01-11 Xilinx Inc. Digital signal processing circuit having an adder circuit with carry-outs
US8495122B2 (en) 2003-12-29 2013-07-23 Xilinx, Inc. Programmable device with dynamic DSP architecture
US7472155B2 (en) 2003-12-29 2008-12-30 Xilinx, Inc. Programmable logic device with cascading DSP slices
US7853632B2 (en) 2003-12-29 2010-12-14 Xilinx, Inc. Architectural floorplan for a digital signal processing circuit
US8266199B2 (en) * 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8266198B2 (en) * 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US7930336B2 (en) 2006-12-05 2011-04-19 Altera Corporation Large multiplier for programmable logic device
US8386553B1 (en) 2006-12-05 2013-02-26 Altera Corporation Large multiplier for programmable logic device
US7394287B1 (en) * 2007-05-21 2008-07-01 Altera Corporation Programmable logic device having complex logic blocks with improved logic cell functionality
US8539011B1 (en) 2007-07-19 2013-09-17 Xilinx, Inc. Device having programmable logic for implementing arithmetic functions
US8117247B1 (en) 2007-07-19 2012-02-14 Xilinx, Inc. Configurable arithmetic block and method of implementing arithmetic functions in a device having programmable logic
US8010590B1 (en) * 2007-07-19 2011-08-30 Xilinx, Inc. Configurable arithmetic block and a method of implementing a configurable arithmetic block in a device having programmable logic
KR101265120B1 (ko) * 2008-01-31 2013-05-16 후지제롯쿠스 가부시끼가이샤 재구성 가능한 디바이스
US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8543635B2 (en) 2009-01-27 2013-09-24 Xilinx, Inc. Digital signal processing block with preadder stage
US8479133B2 (en) 2009-01-27 2013-07-02 Xilinx, Inc. Method of and circuit for implementing a filter in an integrated circuit
US8805916B2 (en) * 2009-03-03 2014-08-12 Altera Corporation Digital signal processing circuitry with redundancy and bidirectional data paths
KR101462157B1 (ko) 2009-12-18 2014-11-20 한국전자통신연구원 Ｍａｃ 연산을 포함하는 연산 장치, 이를 이용한 ｄｓｐ 구조 및 필터링 방법
US8120382B2 (en) * 2010-03-05 2012-02-21 Xilinx, Inc. Programmable integrated circuit with mirrored interconnect structure
US8862650B2 (en) 2010-06-25 2014-10-14 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US9600278B1 (en) 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees
US20120290819A1 (en) * 2011-05-09 2012-11-15 Altera Corporation Dsp block with embedded floating point structures
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US9053045B1 (en) 2011-09-16 2015-06-09 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US9098332B1 (en) 2012-06-01 2015-08-04 Altera Corporation Specialized processing block with fixed- and floating-point structures
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding
US9684488B2 (en) 2015-03-26 2017-06-20 Altera Corporation Combined adder and pre-adder for high-radix multiplier circuit
US10942706B2 (en) 2017-05-05 2021-03-09 Intel Corporation Implementation of floating-point trigonometric functions in an integrated circuit device
JP6553694B2 (ja) * 2017-09-25 2019-07-31 Ｎｅｃスペーステクノロジー株式会社 プロセッサエレメント、プログラマブルデバイス及びプロセッサエレメントの制御方法
JP6820875B2 (ja) 2018-03-09 2021-01-27 株式会社東芝 計算装置
US11288220B2 (en) 2019-10-18 2022-03-29 Achronix Semiconductor Corporation Cascade communications between FPGA tiles
JP7072041B2 (ja) * 2020-12-11 2022-05-19 株式会社東芝 計算装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6556044B2 (en) * 2001-09-18 2003-04-29 Altera Corporation Programmable logic device including multipliers and configurations thereof to reduce resource utilization
JPH04266151A (ja) * 1991-02-21 1992-09-22 Nec Corp 信号処理用集積回路
JPH05324694A (ja) * 1992-05-19 1993-12-07 Tomochika Fujioka 再構成可能並列プロセッサ
US5339264A (en) 1992-07-27 1994-08-16 Tektronix, Inc. Symmetric transposed FIR digital filter
US5682107A (en) 1994-04-01 1997-10-28 Xilinx, Inc. FPGA architecture with repeatable tiles including routing matrices and logic matrices
JPH08287037A (ja) * 1995-04-12 1996-11-01 Matsushita Electric Ind Co Ltd デジタル信号処理プロセッサ
US5754459A (en) 1996-02-08 1998-05-19 Xilinx, Inc. Multiplier circuit design for a programmable logic device
GB9611994D0 (en) * 1996-06-07 1996-08-07 Systolix Ltd A field programmable processor
US5963050A (en) 1997-02-26 1999-10-05 Xilinx, Inc. Configurable logic element with fast feedback paths
US5914616A (en) 1997-02-26 1999-06-22 Xilinx, Inc. FPGA repeatable interconnect structure with hierarchical interconnect lines
US6362650B1 (en) 2000-05-18 2002-03-26 Xilinx, Inc. Method and apparatus for incorporating a multiplier into an FPGA
GB2365636B (en) 2000-08-04 2005-01-05 Automatic Parallel Designs Ltd A parallel counter and a multiplication logic circuit
GB2373602B (en) 2001-03-22 2004-11-17 Automatic Parallel Designs Ltd A multiplication logic circuit
GB2373883A (en) 2001-03-27 2002-10-02 Automatic Parallel Designs Ltd Logic circuit for performing binary addition or subtraction
US20030055861A1 (en) * 2001-09-18 2003-03-20 Lai Gary N. Multipler unit in reconfigurable chip
GB2383435A (en) 2001-12-18 2003-06-25 Automatic Parallel Designs Ltd Logic circuit for performing modular multiplication and exponentiation
US6920627B2 (en) 2002-12-13 2005-07-19 Xilinx, Inc. Reconfiguration of a programmable logic device using internal control

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