DE602005014446D1 - Tung mit io-verbindungen - Google Patents

Tung mit io-verbindungen

Info

Publication number
DE602005014446D1
DE602005014446D1 DE602005014446T DE602005014446T DE602005014446D1 DE 602005014446 D1 DE602005014446 D1 DE 602005014446D1 DE 602005014446 T DE602005014446 T DE 602005014446T DE 602005014446 T DE602005014446 T DE 602005014446T DE 602005014446 D1 DE602005014446 D1 DE 602005014446D1
Authority
DE
Germany
Prior art keywords
digital signal
multiplexing
signal processors
circuits
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005014446T
Other languages
English (en)
Inventor
Den Berg Henricus H Van
Harpreet S Bhullar
Pieter Voorthuijsen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602005014446D1 publication Critical patent/DE602005014446D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Microcomputers (AREA)
  • Saccharide Compounds (AREA)
  • Polysaccharides And Polysaccharide Derivatives (AREA)
DE602005014446T 2004-02-12 2005-01-31 Tung mit io-verbindungen Active DE602005014446D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04100540 2004-02-12
PCT/IB2005/050398 WO2005078598A1 (en) 2004-02-12 2005-01-31 Digital signal processing integrated circuit with io connections

Publications (1)

Publication Number Publication Date
DE602005014446D1 true DE602005014446D1 (de) 2009-06-25

Family

ID=34854691

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005014446T Active DE602005014446D1 (de) 2004-02-12 2005-01-31 Tung mit io-verbindungen

Country Status (7)

Country Link
US (1) US7590821B2 (de)
EP (1) EP1716502B1 (de)
JP (1) JP2007522576A (de)
CN (1) CN100485656C (de)
AT (1) ATE431592T1 (de)
DE (1) DE602005014446D1 (de)
WO (1) WO2005078598A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6747765B2 (ja) * 2014-06-23 2020-08-26 東芝情報システム株式会社 半導体装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3815095A (en) * 1972-08-29 1974-06-04 Texas Instruments Inc General-purpose array processor
US4051551A (en) * 1976-05-03 1977-09-27 Burroughs Corporation Multidimensional parallel access computer memory system
JPH01114965A (ja) * 1987-10-28 1989-05-08 Nec Corp プロセッサアレイヘのコマンド転送方式及び回路
US5121342A (en) * 1989-08-28 1992-06-09 Network Communications Corporation Apparatus for analyzing communication networks
US5450557A (en) * 1989-11-07 1995-09-12 Loral Aerospace Corp. Single-chip self-configurable parallel processor
CA2138170C (en) * 1992-06-15 1998-11-10 Martin Owen Watts Service platform
US5457644A (en) * 1993-08-20 1995-10-10 Actel Corporation Field programmable digital signal processing array integrated circuit
US5541862A (en) * 1994-04-28 1996-07-30 Wandel & Goltermann Ate Systems Ltd. Emulator and digital signal analyzer
US5892934A (en) * 1996-04-02 1999-04-06 Advanced Micro Devices, Inc. Microprocessor configured to detect a branch to a DSP routine and to direct a DSP to execute said routine
US5778244A (en) * 1996-10-07 1998-07-07 Timeplex, Inc. Digital signal processing unit using digital signal processor array with recirculation
US6150837A (en) * 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
JPH1145079A (ja) * 1997-05-28 1999-02-16 Sony Corp 画像信号処理装置
US6456628B1 (en) 1998-04-17 2002-09-24 Intelect Communications, Inc. DSP intercommunication network
JP3504210B2 (ja) * 2000-03-31 2004-03-08 理想科学工業株式会社 画像処理装置
JP2002203908A (ja) 2001-01-05 2002-07-19 Seiko Epson Corp 電子装置及び電子装置の製造方法
US6781407B2 (en) * 2002-01-09 2004-08-24 Xilinx, Inc. FPGA and embedded circuitry initialization and processing
US6798239B2 (en) 2001-09-28 2004-09-28 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US7299307B1 (en) * 2002-12-24 2007-11-20 Cypress Semiconductor Corporation Analog I/O with digital signal processor array

Also Published As

Publication number Publication date
ATE431592T1 (de) 2009-05-15
US7590821B2 (en) 2009-09-15
CN1918559A (zh) 2007-02-21
WO2005078598A1 (en) 2005-08-25
JP2007522576A (ja) 2007-08-09
CN100485656C (zh) 2009-05-06
EP1716502A1 (de) 2006-11-02
EP1716502B1 (de) 2009-05-13
US20070132613A1 (en) 2007-06-14

Similar Documents

Publication Publication Date Title
US9553588B2 (en) System level interconnect with programmable switching
US9564902B2 (en) Dynamically configurable and re-configurable data path
CA2458060C (en) Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US6903573B1 (en) Programmable logic device with enhanced wide input product term cascading
US8482313B2 (en) Universal digital block interconnection and channel routing
US20080288755A1 (en) Clock driven dynamic datapath chaining
JP2006020329A5 (de)
CA2472231A1 (en) Integrated circuit and embedded circuitry initialization and processing
WO2003105345A3 (en) PROGRAMMABLE LOGIC CIRCUIT HAVING HETEROGENEOUS PROGRAMMABLE LOGIC BLOCKS
WO2002050700A3 (en) Processor architecture
KR890015118A (ko) 디지탈 신호 처리 프로세서
EP1577789A3 (de) Rekonfigurierbare Schaltung mit Verbindungseinrichtung
JP2003023083A5 (de)
WO2008105898A3 (en) Reconfigurable data processing system
TW200707459A (en) Identical chips with different operations in a system
AU2003245906A8 (en) Loosely-biased heterogeneous reconfigurable arrays
US7130238B1 (en) Divisible true dual port memory system supporting simple dual port memory subsystems
TW200737712A (en) Common input/output terminal control circuit
DE602005014446D1 (de) Tung mit io-verbindungen
DE602006011961D1 (de) Schnelles redundantes datenverarbeitungssystem
WO2004021356A3 (en) Reconfigurable electronic device having interconnected data storage devices
DE60044145D1 (de) Brückeschnittstellenschaltung
JPH0792229A (ja) 電気アセンブリ
WO2004095191A3 (en) A reconfigurable processing array with variable timing control
RU2014124346A (ru) Устройство для соединения первой единицы оборудования с несколькими вторыми единицами оборудования и система обработки данных, содержащая такое устройство

Legal Events

Date Code Title Description
8364 No opposition during term of opposition