JP2007522699A5 - - Google Patents

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Publication number
JP2007522699A5
JP2007522699A5 JP2006547306A JP2006547306A JP2007522699A5 JP 2007522699 A5 JP2007522699 A5 JP 2007522699A5 JP 2006547306 A JP2006547306 A JP 2006547306A JP 2006547306 A JP2006547306 A JP 2006547306A JP 2007522699 A5 JP2007522699 A5 JP 2007522699A5
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JP
Japan
Prior art keywords
dsp
integrated circuit
dsp element
input
hardwired
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2006547306A
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English (en)
Japanese (ja)
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JP2007522699A (ja
JP4664311B2 (ja
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Priority claimed from PCT/US2004/043113 external-priority patent/WO2005066832A2/en
Publication of JP2007522699A publication Critical patent/JP2007522699A/ja
Publication of JP2007522699A5 publication Critical patent/JP2007522699A5/ja
Application granted granted Critical
Publication of JP4664311B2 publication Critical patent/JP4664311B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2006547306A 2003-12-29 2004-12-21 カスケード接続するｄｓｐスライスを備えた集積回路 Expired - Lifetime JP4664311B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US53318103P 2003-12-29 2003-12-29
US53315303P 2003-12-29 2003-12-29
US53328003P 2003-12-29 2003-12-29
PCT/US2004/043113 WO2005066832A2 (en) 2003-12-29 2004-12-21 Integrated circuit with cascading dsp slices

Publications (3)

Publication Number Publication Date
JP2007522699A JP2007522699A (ja) 2007-08-09
JP2007522699A5 true JP2007522699A5 (enExample) 2008-02-14
JP4664311B2 JP4664311B2 (ja) 2011-04-06

Family

ID=34753688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006547306A Expired - Lifetime JP4664311B2 (ja) 2003-12-29 2004-12-21 カスケード接続するｄｓｐスライスを備えた集積回路

Country Status (4)

Country Link
EP (2) EP2306331B1 (enExample)
JP (1) JP4664311B2 (enExample)
CA (1) CA2548327C (enExample)
WO (1) WO2005066832A2 (enExample)

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US7853634B2 (en) 2003-12-29 2010-12-14 Xilinx, Inc. Digital signal processing circuit having a SIMD circuit
US7853636B2 (en) 2003-12-29 2010-12-14 Xilinx, Inc. Digital signal processing circuit having a pattern detector circuit for convergent rounding
US7480690B2 (en) 2003-12-29 2009-01-20 Xilinx, Inc. Arithmetic circuit with multiplexed addend inputs
US7853632B2 (en) 2003-12-29 2010-12-14 Xilinx, Inc. Architectural floorplan for a digital signal processing circuit
US7840630B2 (en) 2003-12-29 2010-11-23 Xilinx, Inc. Arithmetic logic unit circuit
US7882165B2 (en) 2003-12-29 2011-02-01 Xilinx, Inc. Digital signal processing element having an arithmetic logic unit
US7840627B2 (en) 2003-12-29 2010-11-23 Xilinx, Inc. Digital signal processing circuit having input register blocks
US7860915B2 (en) 2003-12-29 2010-12-28 Xilinx, Inc. Digital signal processing circuit having a pattern circuit for determining termination conditions
US7870182B2 (en) 2003-12-29 2011-01-11 Xilinx Inc. Digital signal processing circuit having an adder circuit with carry-outs
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US7849119B2 (en) 2003-12-29 2010-12-07 Xilinx, Inc. Digital signal processing circuit having a pattern detector circuit
US7467177B2 (en) 2003-12-29 2008-12-16 Xilinx, Inc. Mathematical circuit with dynamic rounding
US7865542B2 (en) 2003-12-29 2011-01-04 Xilinx, Inc. Digital signal processing block having a wide multiplexer
US7472155B2 (en) 2003-12-29 2008-12-30 Xilinx, Inc. Programmable logic device with cascading DSP slices
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US8805916B2 (en) * 2009-03-03 2014-08-12 Altera Corporation Digital signal processing circuitry with redundancy and bidirectional data paths
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US8120382B2 (en) * 2010-03-05 2012-02-21 Xilinx, Inc. Programmable integrated circuit with mirrored interconnect structure
US8862650B2 (en) 2010-06-25 2014-10-14 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US20120290819A1 (en) * 2011-05-09 2012-11-15 Altera Corporation Dsp block with embedded floating point structures
US9600278B1 (en) 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees
US9053045B1 (en) 2011-09-16 2015-06-09 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US9098332B1 (en) 2012-06-01 2015-08-04 Altera Corporation Specialized processing block with fixed- and floating-point structures
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding
US9684488B2 (en) 2015-03-26 2017-06-20 Altera Corporation Combined adder and pre-adder for high-radix multiplier circuit
US10942706B2 (en) 2017-05-05 2021-03-09 Intel Corporation Implementation of floating-point trigonometric functions in an integrated circuit device
JP6553694B2 (ja) 2017-09-25 2019-07-31 Ｎｅｃスペーステクノロジー株式会社 プロセッサエレメント、プログラマブルデバイス及びプロセッサエレメントの制御方法
JP6820875B2 (ja) 2018-03-09 2021-01-27 株式会社東芝 計算装置
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JP7072041B2 (ja) * 2020-12-11 2022-05-19 株式会社東芝 計算装置

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