JP4664311B2 - カスケード接続するｄｓｐスライスを備えた集積回路 - Google Patents

カスケード接続するｄｓｐスライスを備えた集積回路 Download PDF

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Publication number
JP4664311B2
JP4664311B2 JP2006547306A JP2006547306A JP4664311B2 JP 4664311 B2 JP4664311 B2 JP 4664311B2 JP 2006547306 A JP2006547306 A JP 2006547306A JP 2006547306 A JP2006547306 A JP 2006547306A JP 4664311 B2 JP4664311 B2 JP 4664311B2
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dsp
register
input
slice
output
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JP2007522699A (ja
JP2007522699A5 (enExample
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シムキンス，ジェームス・エム
ヤング，スティーブン・ピィ
ウォン，ジェニファー
ニュー，バーナード・ジェイ
チン，アルビン・ワイ
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Xilinx Inc
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Xilinx Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17732—Macroblocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2006547306A 2003-12-29 2004-12-21 カスケード接続するｄｓｐスライスを備えた集積回路 Expired - Lifetime JP4664311B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US53328003P 2003-12-29 2003-12-29
US53315303P 2003-12-29 2003-12-29
US53318103P 2003-12-29 2003-12-29
PCT/US2004/043113 WO2005066832A2 (en) 2003-12-29 2004-12-21 Integrated circuit with cascading dsp slices

Publications (3)

Publication Number Publication Date
JP2007522699A JP2007522699A (ja) 2007-08-09
JP2007522699A5 JP2007522699A5 (enExample) 2008-02-14
JP4664311B2 true JP4664311B2 (ja) 2011-04-06

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JP2006547306A Expired - Lifetime JP4664311B2 (ja) 2003-12-29 2004-12-21 カスケード接続するｄｓｐスライスを備えた集積回路

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EP (2) EP1700231B1 (enExample)
JP (1) JP4664311B2 (enExample)
CA (1) CA2548327C (enExample)
WO (1) WO2005066832A2 (enExample)

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US7480690B2 (en) 2003-12-29 2009-01-20 Xilinx, Inc. Arithmetic circuit with multiplexed addend inputs
US7853632B2 (en) 2003-12-29 2010-12-14 Xilinx, Inc. Architectural floorplan for a digital signal processing circuit
US7853634B2 (en) 2003-12-29 2010-12-14 Xilinx, Inc. Digital signal processing circuit having a SIMD circuit
US7849119B2 (en) 2003-12-29 2010-12-07 Xilinx, Inc. Digital signal processing circuit having a pattern detector circuit
US7882165B2 (en) 2003-12-29 2011-02-01 Xilinx, Inc. Digital signal processing element having an arithmetic logic unit
US7853636B2 (en) 2003-12-29 2010-12-14 Xilinx, Inc. Digital signal processing circuit having a pattern detector circuit for convergent rounding
US7467175B2 (en) 2003-12-29 2008-12-16 Xilinx, Inc. Programmable logic device with pipelined DSP slices
US7472155B2 (en) 2003-12-29 2008-12-30 Xilinx, Inc. Programmable logic device with cascading DSP slices
US7840627B2 (en) 2003-12-29 2010-11-23 Xilinx, Inc. Digital signal processing circuit having input register blocks
US7567997B2 (en) 2003-12-29 2009-07-28 Xilinx, Inc. Applications of cascading DSP slices
US7467177B2 (en) 2003-12-29 2008-12-16 Xilinx, Inc. Mathematical circuit with dynamic rounding
US7860915B2 (en) 2003-12-29 2010-12-28 Xilinx, Inc. Digital signal processing circuit having a pattern circuit for determining termination conditions
US7870182B2 (en) 2003-12-29 2011-01-11 Xilinx Inc. Digital signal processing circuit having an adder circuit with carry-outs
US7865542B2 (en) 2003-12-29 2011-01-04 Xilinx, Inc. Digital signal processing block having a wide multiplexer
US7840630B2 (en) 2003-12-29 2010-11-23 Xilinx, Inc. Arithmetic logic unit circuit
US8266199B2 (en) * 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8266198B2 (en) * 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8386553B1 (en) 2006-12-05 2013-02-26 Altera Corporation Large multiplier for programmable logic device
US7930336B2 (en) 2006-12-05 2011-04-19 Altera Corporation Large multiplier for programmable logic device
US7394287B1 (en) * 2007-05-21 2008-07-01 Altera Corporation Programmable logic device having complex logic blocks with improved logic cell functionality
US8117247B1 (en) 2007-07-19 2012-02-14 Xilinx, Inc. Configurable arithmetic block and method of implementing arithmetic functions in a device having programmable logic
US8539011B1 (en) 2007-07-19 2013-09-17 Xilinx, Inc. Device having programmable logic for implementing arithmetic functions
US8010590B1 (en) * 2007-07-19 2011-08-30 Xilinx, Inc. Configurable arithmetic block and a method of implementing a configurable arithmetic block in a device having programmable logic
EP2246781B1 (en) * 2008-01-31 2020-12-09 Fuji Xerox Co., Ltd. Reconfigurable device
US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8479133B2 (en) * 2009-01-27 2013-07-02 Xilinx, Inc. Method of and circuit for implementing a filter in an integrated circuit
US8543635B2 (en) 2009-01-27 2013-09-24 Xilinx, Inc. Digital signal processing block with preadder stage
US8805916B2 (en) * 2009-03-03 2014-08-12 Altera Corporation Digital signal processing circuitry with redundancy and bidirectional data paths
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US8120382B2 (en) * 2010-03-05 2012-02-21 Xilinx, Inc. Programmable integrated circuit with mirrored interconnect structure
US8862650B2 (en) 2010-06-25 2014-10-14 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US9600278B1 (en) 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees
US20120290819A1 (en) * 2011-05-09 2012-11-15 Altera Corporation Dsp block with embedded floating point structures
US9053045B1 (en) 2011-09-16 2015-06-09 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US9098332B1 (en) 2012-06-01 2015-08-04 Altera Corporation Specialized processing block with fixed- and floating-point structures
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding
US9684488B2 (en) 2015-03-26 2017-06-20 Altera Corporation Combined adder and pre-adder for high-radix multiplier circuit
US10942706B2 (en) 2017-05-05 2021-03-09 Intel Corporation Implementation of floating-point trigonometric functions in an integrated circuit device
JP6553694B2 (ja) * 2017-09-25 2019-07-31 Ｎｅｃスペーステクノロジー株式会社 プロセッサエレメント、プログラマブルデバイス及びプロセッサエレメントの制御方法
JP6820875B2 (ja) * 2018-03-09 2021-01-27 株式会社東芝 計算装置
US11288220B2 (en) 2019-10-18 2022-03-29 Achronix Semiconductor Corporation Cascade communications between FPGA tiles
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Also Published As

Publication number Publication date
CA2548327C (en) 2015-10-20
EP2306331B1 (en) 2018-05-02
JP2007522699A (ja) 2007-08-09
EP2306331A1 (en) 2011-04-06
EP1700231A2 (en) 2006-09-13
EP1700231B1 (en) 2012-10-17
WO2005066832A2 (en) 2005-07-21
CA2548327A1 (en) 2005-07-21
WO2005066832A3 (en) 2006-01-19

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