JP2007522673A - 処理済みフォトレジストを使用して半導体素子を形成する方法 - Google Patents

処理済みフォトレジストを使用して半導体素子を形成する方法 Download PDF

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Publication number
JP2007522673A
JP2007522673A JP2006553127A JP2006553127A JP2007522673A JP 2007522673 A JP2007522673 A JP 2007522673A JP 2006553127 A JP2006553127 A JP 2006553127A JP 2006553127 A JP2006553127 A JP 2006553127A JP 2007522673 A JP2007522673 A JP 2007522673A
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JP
Japan
Prior art keywords
layer
photoresist layer
photoresist
patterned
patterned photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006553127A
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English (en)
Japanese (ja)
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JP2007522673A5 (https=
Inventor
エム． ガーザ、シーザー
ディ． ダーリントン、ウィリアム
エム． フィリピアク、スタンリー
イー． ベイセク、ジェームズ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2007522673A publication Critical patent/JP2007522673A/ja
Publication of JP2007522673A5 publication Critical patent/JP2007522673A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2006553127A 2004-02-13 2005-01-12 処理済みフォトレジストを使用して半導体素子を形成する方法 Pending JP2007522673A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/779,007 US7157377B2 (en) 2004-02-13 2004-02-13 Method of making a semiconductor device using treated photoresist
PCT/US2005/000961 WO2005082122A2 (en) 2004-02-13 2005-01-12 Method of making a semiconductor device using treated photoresist

Publications (2)

Publication Number Publication Date
JP2007522673A true JP2007522673A (ja) 2007-08-09
JP2007522673A5 JP2007522673A5 (https=) 2008-03-06

Family

ID=34838285

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006553127A Pending JP2007522673A (ja) 2004-02-13 2005-01-12 処理済みフォトレジストを使用して半導体素子を形成する方法

Country Status (6)

Country Link
US (2) US7157377B2 (https=)
EP (1) EP1719162B8 (https=)
JP (1) JP2007522673A (https=)
KR (1) KR101128260B1 (https=)
CN (1) CN100487873C (https=)
WO (1) WO2005082122A2 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007311508A (ja) * 2006-05-17 2007-11-29 Nikon Corp 微細パターン形成方法及びデバイス製造方法
JP2010103497A (ja) * 2008-09-29 2010-05-06 Tokyo Electron Ltd マスクパターンの形成方法、微細パターンの形成方法及び成膜装置
JP2015508574A (ja) * 2012-01-03 2015-03-19 東京エレクトロン株式会社 パターン平滑化及びインライン限界寸法のスリム化のための蒸気処理プロセス

Families Citing this family (10)

* Cited by examiner, † Cited by third party
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US20050026084A1 (en) * 2003-07-31 2005-02-03 Garza Cesar M. Semiconductor device and method for elimination of resist linewidth slimming by fluorination
US8057143B2 (en) * 2004-10-05 2011-11-15 Fontaine Trailer Company, Inc. Trailer load securement system
US7435354B2 (en) * 2005-01-06 2008-10-14 United Microelectronic Corp. Treatment method for surface of photoresist layer and method for forming patterned photoresist layer
US8915684B2 (en) 2005-09-27 2014-12-23 Fontaine Trailer Company, Inc. Cargo deck
US7703826B1 (en) * 2006-09-08 2010-04-27 German Mark K Bed liner rail system for cargo holddown
CN102573329B (zh) * 2010-12-08 2014-04-02 北大方正集团有限公司 制作电路板导电柱的方法、系统以及电路板
US20120318773A1 (en) * 2011-06-15 2012-12-20 Applied Materials, Inc. Methods and apparatus for controlling photoresist line width roughness with enhanced electron spin control
JP2015115599A (ja) * 2013-12-13 2015-06-22 株式会社東芝 パターン形成方法
EP3719576A1 (en) * 2019-04-04 2020-10-07 IMEC vzw Resistless pattering mask
DE102020206696A1 (de) 2020-05-28 2021-12-02 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren und Steuergerät zum Herstellen eines Trägerelements zum Aufnehmen einer Probenflüssigkeit, Trägerelement, Trägermodul und Verfahren zum Verwenden eines Trägerelements

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JPH0831720A (ja) * 1994-07-13 1996-02-02 Nkk Corp レジストマスクの形成方法
JPH11251295A (ja) * 1998-02-27 1999-09-17 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2002305181A (ja) * 2001-04-06 2002-10-18 Seiko Epson Corp 半導体装置の製造方法
JP2002343769A (ja) * 2001-05-16 2002-11-29 Shin Etsu Chem Co Ltd クロム系フォトマスクの形成方法
JP2004530922A (ja) * 2001-03-28 2004-10-07 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド サブリソグラフィフォトレジストフィーチャーを形成するプロセス

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US5332653A (en) * 1992-07-01 1994-07-26 Motorola, Inc. Process for forming a conductive region without photoresist-related reflective notching damage
JPH0669190A (ja) * 1992-08-21 1994-03-11 Fujitsu Ltd フッ素系樹脂膜の形成方法
US5912187A (en) * 1993-12-30 1999-06-15 Lucent Technologies Inc. Method of fabricating circuits
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JP2000214575A (ja) * 1999-01-26 2000-08-04 Sharp Corp クロムマスクの形成方法
US6174818B1 (en) * 1999-11-19 2001-01-16 Taiwan Semiconductor Manufacturing Company Method of patterning narrow gate electrode
US6506653B1 (en) * 2000-03-13 2003-01-14 International Business Machines Corporation Method using disposable and permanent films for diffusion and implant doping
JP2002222941A (ja) * 2001-01-24 2002-08-09 Sony Corp Ｍｉｓ型半導体装置及びその製造方法
US6589709B1 (en) * 2001-03-28 2003-07-08 Advanced Micro Devices, Inc. Process for preventing deformation of patterned photoresist features
US6815359B2 (en) * 2001-03-28 2004-11-09 Advanced Micro Devices, Inc. Process for improving the etch stability of ultra-thin photoresist
US6716571B2 (en) * 2001-03-28 2004-04-06 Advanced Micro Devices, Inc. Selective photoresist hardening to facilitate lateral trimming
JP3725811B2 (ja) * 2001-10-11 2005-12-14 ローム株式会社 半導体装置の製造方法
US6790782B1 (en) * 2001-12-28 2004-09-14 Advanced Micro Devices, Inc. Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal
US6716570B2 (en) * 2002-05-23 2004-04-06 Institute Of Microelectronics Low temperature resist trimming process
US6979408B2 (en) * 2002-12-30 2005-12-27 Intel Corporation Method and apparatus for photomask fabrication
US20050026084A1 (en) * 2003-07-31 2005-02-03 Garza Cesar M. Semiconductor device and method for elimination of resist linewidth slimming by fluorination
US6849515B1 (en) * 2003-09-25 2005-02-01 Freescale Semiconductor, Inc. Semiconductor process for disposable sidewall spacers

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831720A (ja) * 1994-07-13 1996-02-02 Nkk Corp レジストマスクの形成方法
JPH11251295A (ja) * 1998-02-27 1999-09-17 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2004530922A (ja) * 2001-03-28 2004-10-07 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド サブリソグラフィフォトレジストフィーチャーを形成するプロセス
JP2002305181A (ja) * 2001-04-06 2002-10-18 Seiko Epson Corp 半導体装置の製造方法
JP2002343769A (ja) * 2001-05-16 2002-11-29 Shin Etsu Chem Co Ltd クロム系フォトマスクの形成方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007311508A (ja) * 2006-05-17 2007-11-29 Nikon Corp 微細パターン形成方法及びデバイス製造方法
JP2010103497A (ja) * 2008-09-29 2010-05-06 Tokyo Electron Ltd マスクパターンの形成方法、微細パターンの形成方法及び成膜装置
JP2015508574A (ja) * 2012-01-03 2015-03-19 東京エレクトロン株式会社 パターン平滑化及びインライン限界寸法のスリム化のための蒸気処理プロセス

Also Published As

Publication number Publication date
EP1719162A2 (en) 2006-11-08
US20050224455A1 (en) 2005-10-13
EP1719162B1 (en) 2016-03-23
US20050181630A1 (en) 2005-08-18
CN1918700A (zh) 2007-02-21
WO2005082122A3 (en) 2006-02-16
WO2005082122A2 (en) 2005-09-09
EP1719162A4 (en) 2009-05-20
KR101128260B1 (ko) 2012-03-26
US7157377B2 (en) 2007-01-02
EP1719162B8 (en) 2016-05-11
KR20060114716A (ko) 2006-11-07
CN100487873C (zh) 2009-05-13

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