JP2007520078A - 改良された表面形状を用いるメモリ構造の形成方法及びその構造。 - Google Patents

改良された表面形状を用いるメモリ構造の形成方法及びその構造。 Download PDF

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Publication number
JP2007520078A
JP2007520078A JP2006551086A JP2006551086A JP2007520078A JP 2007520078 A JP2007520078 A JP 2007520078A JP 2006551086 A JP2006551086 A JP 2006551086A JP 2006551086 A JP2006551086 A JP 2006551086A JP 2007520078 A JP2007520078 A JP 2007520078A
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Japan
Prior art keywords
floating gate
individual elements
forming
covering
dielectric
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Pending
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JP2006551086A
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English (en)
Japanese (ja)
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JP2007520078A5 (https=
Inventor
エイ． インガーソル、ポール
エル． チンダロール、ゴーリシャンカール
ムラリダール、ラマチャンドラン
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NXP USA Inc
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NXP USA Inc
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Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2007520078A publication Critical patent/JP2007520078A/ja
Publication of JP2007520078A5 publication Critical patent/JP2007520078A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H10D64/666—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum the conductor further comprising additional layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
JP2006551086A 2004-01-27 2004-12-21 改良された表面形状を用いるメモリ構造の形成方法及びその構造。 Pending JP2007520078A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/765,804 US6991984B2 (en) 2004-01-27 2004-01-27 Method for forming a memory structure using a modified surface topography and structure thereof
PCT/US2004/043197 WO2005074471A2 (en) 2004-01-27 2004-12-21 Method for forming a memory structure using a modified surface topography and structure thereof

Publications (2)

Publication Number Publication Date
JP2007520078A true JP2007520078A (ja) 2007-07-19
JP2007520078A5 JP2007520078A5 (https=) 2008-02-14

Family

ID=34795568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006551086A Pending JP2007520078A (ja) 2004-01-27 2004-12-21 改良された表面形状を用いるメモリ構造の形成方法及びその構造。

Country Status (6)

Country Link
US (1) US6991984B2 (https=)
EP (1) EP1714314A4 (https=)
JP (1) JP2007520078A (https=)
KR (1) KR20070006712A (https=)
CN (1) CN1906743A (https=)
WO (1) WO2005074471A2 (https=)

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US7102191B2 (en) * 2004-03-24 2006-09-05 Micron Technologies, Inc. Memory device with high dielectric constant gate dielectrics and metal floating gates
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US7582929B2 (en) * 2005-07-25 2009-09-01 Freescale Semiconductor, Inc Electronic device including discontinuous storage elements
US7619270B2 (en) 2005-07-25 2009-11-17 Freescale Semiconductor, Inc. Electronic device including discontinuous storage elements
US7112490B1 (en) * 2005-07-25 2006-09-26 Freescale Semiconductor, Inc. Hot carrier injection programmable structure including discontinuous storage elements and spacer control gates in a trench
US7619275B2 (en) * 2005-07-25 2009-11-17 Freescale Semiconductor, Inc. Process for forming an electronic device including discontinuous storage elements
US7642594B2 (en) * 2005-07-25 2010-01-05 Freescale Semiconductor, Inc Electronic device including gate lines, bit lines, or a combination thereof
JP2007073969A (ja) * 2005-09-07 2007-03-22 Samsung Electronics Co Ltd 電荷トラップ型メモリ素子及びその製造方法
US7592224B2 (en) * 2006-03-30 2009-09-22 Freescale Semiconductor, Inc Method of fabricating a storage device including decontinuous storage elements within and between trenches
US7667260B2 (en) * 2006-08-09 2010-02-23 Micron Technology, Inc. Nanoscale floating gate and methods of formation
US7838922B2 (en) * 2007-01-24 2010-11-23 Freescale Semiconductor, Inc. Electronic device including trenches and discontinuous storage elements
US7572699B2 (en) * 2007-01-24 2009-08-11 Freescale Semiconductor, Inc Process of forming an electronic device including fins and discontinuous storage elements
US7651916B2 (en) * 2007-01-24 2010-01-26 Freescale Semiconductor, Inc Electronic device including trenches and discontinuous storage elements and processes of forming and using the same
US7723186B2 (en) * 2007-12-18 2010-05-25 Sandisk Corporation Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer
US8193055B1 (en) 2007-12-18 2012-06-05 Sandisk Technologies Inc. Method of forming memory with floating gates including self-aligned metal nanodots using a polymer solution
US8383479B2 (en) * 2009-07-21 2013-02-26 Sandisk Technologies Inc. Integrated nanostructure-based non-volatile memory fabrication
KR101855169B1 (ko) 2011-10-13 2018-05-09 삼성전자주식회사 불휘발성 메모리 장치, 불휘발성 메모리 장치의 프로그램 방법, 불휘발성 메모리 장치를 포함하는 메모리 시스템
JP2013197411A (ja) * 2012-03-21 2013-09-30 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US8822288B2 (en) 2012-07-02 2014-09-02 Sandisk Technologies Inc. NAND memory device containing nanodots and method of making thereof
US8823075B2 (en) 2012-11-30 2014-09-02 Sandisk Technologies Inc. Select gate formation for nanodot flat cell
US8987802B2 (en) 2013-02-28 2015-03-24 Sandisk Technologies Inc. Method for using nanoparticles to make uniform discrete floating gate layer
US9331181B2 (en) 2013-03-11 2016-05-03 Sandisk Technologies Inc. Nanodot enhanced hybrid floating gate for non-volatile memory devices
US9177808B2 (en) 2013-05-21 2015-11-03 Sandisk Technologies Inc. Memory device with control gate oxygen diffusion control and method of making thereof
US8969153B2 (en) 2013-07-01 2015-03-03 Sandisk Technologies Inc. NAND string containing self-aligned control gate sidewall cladding

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10189778A (ja) * 1996-12-26 1998-07-21 Sony Corp 半導体記憶素子およびその製造方法
JP2001118810A (ja) * 1999-10-21 2001-04-27 Matsushita Electric Ind Co Ltd 微粒子の形成方法
JP2003163293A (ja) * 2001-10-04 2003-06-06 Hynix Semiconductor America Inc メモリセルアレイの形成方法及びメモリセルアレイ
JP2003531738A (ja) * 2000-05-04 2003-10-28 ビーティージー・インターナショナル・リミテッド ナノ構造

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US3878549A (en) 1970-10-27 1975-04-15 Shumpei Yamazaki Semiconductor memories
US5852306A (en) 1997-01-29 1998-12-22 Micron Technology, Inc. Flash memory with nanocrystalline silicon film floating gate
US6548825B1 (en) * 1999-06-04 2003-04-15 Matsushita Electric Industrial Co., Ltd. Semiconductor device including barrier layer having dispersed particles
US6461915B1 (en) 1999-09-01 2002-10-08 Micron Technology, Inc. Method and structure for an improved floating gate memory cell
US6413819B1 (en) 2000-06-16 2002-07-02 Motorola, Inc. Memory device and method for using prefabricated isolated storage elements
US20040152260A1 (en) * 2001-09-07 2004-08-05 Peter Rabkin Non-volatile memory cell with non-uniform surface floating gate and control gate
US6656792B2 (en) * 2001-10-19 2003-12-02 Chartered Semiconductor Manufacturing Ltd Nanocrystal flash memory device and manufacturing method therefor
KR100426483B1 (ko) * 2001-12-22 2004-04-14 주식회사 하이닉스반도체 플래쉬 메모리 셀의 제조 방법
US7005697B2 (en) * 2002-06-21 2006-02-28 Micron Technology, Inc. Method of forming a non-volatile electron storage memory and the resulting device
US7154140B2 (en) * 2002-06-21 2006-12-26 Micron Technology, Inc. Write once read only memory with large work function floating gates
US6690059B1 (en) * 2002-08-22 2004-02-10 Atmel Corporation Nanocrystal electron device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10189778A (ja) * 1996-12-26 1998-07-21 Sony Corp 半導体記憶素子およびその製造方法
JP2001118810A (ja) * 1999-10-21 2001-04-27 Matsushita Electric Ind Co Ltd 微粒子の形成方法
JP2003531738A (ja) * 2000-05-04 2003-10-28 ビーティージー・インターナショナル・リミテッド ナノ構造
JP2003163293A (ja) * 2001-10-04 2003-06-06 Hynix Semiconductor America Inc メモリセルアレイの形成方法及びメモリセルアレイ

Also Published As

Publication number Publication date
CN1906743A (zh) 2007-01-31
EP1714314A4 (en) 2008-07-09
US6991984B2 (en) 2006-01-31
US20050161731A1 (en) 2005-07-28
KR20070006712A (ko) 2007-01-11
WO2005074471A3 (en) 2005-12-15
WO2005074471A2 (en) 2005-08-18
EP1714314A2 (en) 2006-10-25

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