JP2007518149A5 - - Google Patents

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Publication number
JP2007518149A5
JP2007518149A5 JP2006533913A JP2006533913A JP2007518149A5 JP 2007518149 A5 JP2007518149 A5 JP 2007518149A5 JP 2006533913 A JP2006533913 A JP 2006533913A JP 2006533913 A JP2006533913 A JP 2006533913A JP 2007518149 A5 JP2007518149 A5 JP 2007518149A5
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JP
Japan
Prior art keywords
memory
memory array
circuit
array
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006533913A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007518149A (ja
Filing date
Publication date
Priority claimed from US10/675,005 external-priority patent/US6917555B2/en
Application filed filed Critical
Publication of JP2007518149A publication Critical patent/JP2007518149A/ja
Publication of JP2007518149A5 publication Critical patent/JP2007518149A5/ja
Pending legal-status Critical Current

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JP2006533913A 2003-09-30 2004-09-14 回路アレイの漏れ電流を低減するための集積回路電力管理及びそのための方法 Pending JP2007518149A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/675,005 US6917555B2 (en) 2003-09-30 2003-09-30 Integrated circuit power management for reducing leakage current in circuit arrays and method therefor
PCT/US2004/029935 WO2005034189A2 (en) 2003-09-30 2004-09-14 Integrated circuit power management for reducing leakage current in circuit arrays and method therefor

Publications (2)

Publication Number Publication Date
JP2007518149A JP2007518149A (ja) 2007-07-05
JP2007518149A5 true JP2007518149A5 (enExample) 2007-10-11

Family

ID=34377015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006533913A Pending JP2007518149A (ja) 2003-09-30 2004-09-14 回路アレイの漏れ電流を低減するための集積回路電力管理及びそのための方法

Country Status (6)

Country Link
US (1) US6917555B2 (enExample)
EP (1) EP1671352A4 (enExample)
JP (1) JP2007518149A (enExample)
KR (1) KR101034909B1 (enExample)
TW (1) TWI368227B (enExample)
WO (1) WO2005034189A2 (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101035077B1 (ko) * 2004-02-20 2011-05-19 삼성전자주식회사 다이나믹 전압 스케일링에 따라 전력 소비 감소가 가능한반도체 시스템
US20060005053A1 (en) * 2004-06-30 2006-01-05 Jones Oscar F Jr Cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devices
US7209404B2 (en) * 2005-08-05 2007-04-24 Fortemedia Inc. Low power memory sub-system architecture
US20070043965A1 (en) * 2005-08-22 2007-02-22 Intel Corporation Dynamic memory sizing for power reduction
KR101254350B1 (ko) * 2006-01-12 2013-04-23 삼성전자주식회사 버스를 공유하는 이종 시스템 프로세서들 사이에서 누설전류를 차단하기 위한 장치 및 방법
FR2897199A1 (fr) * 2006-02-03 2007-08-10 St Microelectronics Sa Dispositif de gestion du pic de consommation d'un domaine a chaque mise sous tension
CN100574030C (zh) * 2006-09-27 2009-12-23 鸿富锦精密工业（深圳）有限公司 泄漏电流防护电路
US7900018B2 (en) * 2006-12-05 2011-03-01 Electronics And Telecommunications Research Institute Embedded system and page relocation method therefor
US8898400B2 (en) * 2007-07-23 2014-11-25 Infineon Technologies Ag Integrated circuit including multiple memory devices
US20090113085A1 (en) * 2007-10-25 2009-04-30 Banyai Chris J Flushing write buffers
US20110204148A1 (en) * 2008-07-21 2011-08-25 Stuart Colin Littlechild Device having data storage
US7848172B2 (en) * 2008-11-24 2010-12-07 Agere Systems Inc. Memory circuit having reduced power consumption
US9368162B2 (en) 2011-02-08 2016-06-14 Freescale Semiconductor, Inc. Integrated circuit device, power management module and method for providing power management
US9065433B2 (en) 2013-01-16 2015-06-23 Freescale Semiconductor, Inc. Capacitor charging circuit with low sub-threshold transistor leakage current
US11003238B2 (en) * 2017-04-03 2021-05-11 Nvidia Corporation Clock gating coupled memory retention circuit
US10572388B2 (en) 2017-08-30 2020-02-25 Micron Technology, Inc. Managed NVM adaptive cache management
US10825486B2 (en) 2018-04-09 2020-11-03 Nxp Usa, Inc. High performance method for reduction of memory power consumption employing RAM retention mode control with low latency and maximum granularity
CN118228657A (zh) * 2022-12-19 2024-06-21 兆易创新科技集团股份有限公司 兼具MCU和Flash的系统及其低功耗控制方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5635228A (en) * 1979-08-31 1981-04-07 Fujitsu Ltd Power supply system for memory device
JP3312162B2 (ja) * 1994-03-15 2002-08-05 日本電信電話株式会社 半導体メモリ装置
JPH09212416A (ja) * 1995-11-30 1997-08-15 Toshiba Corp 計算機システムおよび計算機システムの電力管理方法
US5848428A (en) * 1996-12-19 1998-12-08 Compaq Computer Corporation Sense amplifier decoding in a memory device to reduce power consumption
US5901103A (en) * 1997-04-07 1999-05-04 Motorola, Inc. Integrated circuit having standby control for memory and method thereof
KR100297139B1 (ko) * 1998-04-20 2001-10-29 가네꼬 히사시 반도체 집적회로
JP2000222285A (ja) * 1999-01-29 2000-08-11 Matsushita Electric Ind Co Ltd メモリー電力管理装置
US6597620B1 (en) * 2001-07-18 2003-07-22 Advanced Micro Devices, Inc. Storage circuit with data retention during power down
JP2003045189A (ja) * 2001-07-31 2003-02-14 Fujitsu Ltd 半導体メモリ
US6766420B2 (en) * 2001-09-27 2004-07-20 International Business Machines Corporation Selectively powering portions of system memory in a network server to conserve energy

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