JP2007513523A - クローズドセルトレンチmos電界効果トランジスタ - Google Patents
クローズドセルトレンチmos電界効果トランジスタ Download PDFInfo
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- 230000005669 field effect Effects 0.000 title claims abstract description 19
- 239000012212 insulator Substances 0.000 claims abstract description 96
- 210000000746 body region Anatomy 0.000 claims abstract description 82
- 238000000034 method Methods 0.000 claims description 76
- 239000004065 semiconductor Substances 0.000 claims description 73
- 229910052710 silicon Inorganic materials 0.000 claims description 38
- 239000010703 silicon Substances 0.000 claims description 38
- 239000012535 impurity Substances 0.000 claims description 36
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 31
- 229910052698 phosphorus Inorganic materials 0.000 claims description 31
- 239000011574 phosphorus Substances 0.000 claims description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 16
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 15
- 229910052796 boron Inorganic materials 0.000 claims description 15
- 238000005229 chemical vapour deposition Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 claims description 5
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 37
- 230000004888 barrier function Effects 0.000 description 30
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 229910052785 arsenic Inorganic materials 0.000 description 12
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 12
- 238000005468 ion implantation Methods 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- 238000005382 thermal cycling Methods 0.000 description 6
- 238000002513 implantation Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000011282 treatment Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000004380 ashing Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000000354 decomposition reaction Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (26)
- ドレイン領域と、
前記ドレイン領域の上に設けられたボディ領域と、
前記ボディ領域内に設けられたゲート領域と、
前記ゲート領域の周辺に設けられたゲート絶縁体領域と、
前記ゲート絶縁体領域の周辺に隣接して前記ボディ領域の表面に沿って設けられた複数のソース領域と、
を備えるクローズドセルトレンチMOS電界効果トランジスタ(TMOSFET)であって、
前記ゲート領域の第一の部分と前記ゲート絶縁体領域の第一の部分とが、実質的に平行に延びた構造として形成され、
前記ゲート領域の第二の部分と前記ゲート絶縁体領域の第二の部分とが、平行に対して直交する構造として形成され、
前記ドレイン領域の第一の部分が前記平行な構造とオーバーラップしており、
前記ドレイン領域の第二の部分が前記平行に対して直交する構造から分離している、
クローズドセルTMOSFET。 - 前記クローズドセルMOSFETは、低いゲート-ドレイン容量(Cgd)・オン抵抗(Rds-on)積を提供する、請求項1に記載のクローズドセルTMOSFET。
- 前記クローズドセルMOSFETは、低減されたゲート-ドレイン容量・ゲート-ソース容量比を提供する、請求項1に記載のクローズドセルTMOSFET。
- 前記ドレイン領域の前記第一の部分と前記平行に延びた構造とのオーバーラップが、前記ドレイン領域の延長部を含む、請求項1に記載のクローズドセルTMOSFET。
- 前記ドレイン領域の前記第二の部分と前記平行に対して直交して延びる構造との分離が、前記ボディ領域のウエルを含む、請求項1に記載のクローズドセルTMOSFET。
- 前記ボディ領域と前記複数のソース領域とが電気的に相互に接続している、請求項1に記載のクローズドセルTMOSFET。
- 前記ドレイン領域はnドープド半導体を含み、
前記ボディ領域はpドープド半導体を含み、
前記ゲート絶縁体領域は酸化物を含み、
前記複数のソース領域は高濃度nドープド半導体を含み、
前記ゲート領域は高濃度nドープド半導体を含む、
請求項1に記載のクローズドセルTMOSFET。 - 前記ドレイン領域は、
高いドーピング濃度を有する第一のドレイン部と、
低いドーピング濃度を有し、前記ボディ領域と前記第一のドレイン部との間に設けられた第二のドレイン部と、を備える、請求項1に記載のクローズドセルTMOSFET。 - 前記第二のドレイン部は、前記クローズドセルTMOSFETの逆破壊電圧を増加させる、請求項8に記載のクローズドセルTMOSFET。
- 前記ドレイン領域の前記第一の部分は高濃度nドープド半導体を含み、
前記ドレイン領域の前記第二の部分は低濃度nドープド半導体を含む、
請求項8に記載のクローズドセルTMOSFET。 - 基板上に第一の種類の不純物がドーピングされる第一の半導体層を堆積するステップと、
前記第一の半導体層に複数のトレンチをエッチングするステップであって、前記複数のトレンチの第一セットが互いに実質的に平行であって、前記複数のトレンチの第二セットが前記複数のトレンチの第一セットに関連して平行に対して直交しており、
前記複数のトレンチに隣接して絶縁体を形成するステップと、
前記複数のトレンチの第一セットの底部に隣接して前記第一の半導体層にドーピングするステップと、
前記複数のトレンチ内に第二の半導体層を堆積するステップと、
前記第一の半導体層の第一の部分に第二の種類の不純物をドーピングするステップと、
前記絶縁体に隣接して前記第一の半導体層の第二の部分に前記第一の種類の不純物をドーピングするステップと、
からなるクローズドセルMOS電界効果トランジスタ(TMOSFET)の製造方法。 - 前記第一の半導体層の堆積は、リンが低濃度にドープされたシリコンをエピタキシャル堆積することを含む、請求項11に記載の方法。
- 前記第一の半導体層の前記第一の部分を前記第二の種類の不純物でドーピングすることは、ボロンを注入してボディ領域を形成することを含む、請求項11に記載の方法。
- 前記複数のトレンチに隣接して絶縁体を形成することは、前記複数のトレンチに隣接した前記第一の半導体層を酸化することを含む、請求項11に記載の方法。
- 前記複数のトレンチのエッチングが、前記複数のトレンチの底部が前記第一の半導体層の第三の部分に到達するまで実行される、請求項11に記載の方法。
- 前記複数のトレンチの第一セットの底部に隣接した前記第一の半導体層のドーピングは、ボロンを注入して、前記複数のトレンチの第一セットの底部に隣接した前記絶縁体の一部を取り囲むウエルを形成することを含む、請求項15に記載の方法。
- 前記複数のトレンチの第二セットの底部に隣接した前記第一の半導体層にリンをドーピングして、前記複数のトレンチの第二セットの底部に隣接した前記絶縁体から前記第一の半導体層の前記第三の部分まで延長部を形成することをさらに含む、請求項16に記載の方法。
- 前記複数のトレンチのエッチングは、前記複数のトレンチの底部が前記第一の半導体層の第三の部分に到達する前に終了する、請求項11に記載の方法。
- 前記複数のトレンチの第一セットの底部に隣接した前記第一の半導体層のドーピングは、リンを注入して、前記複数のトレンチの第一セットの底部に隣接した前記絶縁体層から前記第一の半導体層の前記第三の部分まで延長部を形成することを含む、請求項18に記載の方法。
- 前記複数のトレンチの第二セットの底部に隣接した前記絶縁体層から、前記第一の半導体層の前記第三の部分までボロンがドープされた埋め込み層を形成することを含む、請求項19に記載の方法。
- 前記第二の半導体層の前記複数のトレンチ内への前記堆積は、リンを高濃度にドープされたポリシリコンの化学気相堆積を含む、請求項11に記載の方法。
- 前記絶縁体に隣接した前記第一の半導体層の第二の部分を前記第一の種類の不純物で前記ドーピングすることは、リンを注入してソース領域を形成することを含む、請求項11に記載の方法。
- 前記複数のトレンチの第一セットの底部に隣接した前記第一の半導体層を前記ドーピングすることは、不純物が前記複数のトレンチの第一セット内に注入されるが、前記複数のトレンチの第二セット内には注入されないように、第一の角度で前記不純物を注入することを含む、請求項11に記載の方法。
- 第一の複数の平行な領域に設けられた複数の開放したゲート-ドレイン領域と、
前記開放したゲート-ドレイン領域に対して直交する第二の複数の平行な領域内に設けられた複数の閉鎖したゲート-ドレイン領域と、
を備えるクローズドセルトレンチMOS電界効果トランジスタ(TMOSFET)。 - 前記複数の開放したゲート-ドレイン領域と、前記複数の閉鎖したゲート-ドレイン領域との組み合わせが、ゲート-ドレイン容量(Cgd)・オン抵抗(Rds-on)積を減少させる、請求項24に記載のクローズドセルTMOSFET。
- 前記複数の開放したゲート-ドレイン領域と、前記複数の閉鎖したゲート-ドレイン領域との組み合わせが、ゲート-ドレイン容量・ゲート-ソース容量比を減少させる、請求項24に記載のクローズドセルTMOSFET。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US10/726,922 US7279743B2 (en) | 2003-12-02 | 2003-12-02 | Closed cell trench metal-oxide-semiconductor field effect transistor |
PCT/US2004/040063 WO2005057615A2 (en) | 2003-12-02 | 2004-11-30 | Closed cell trench metal-oxide-semiconductor field effect transistor |
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JP2007513523A true JP2007513523A (ja) | 2007-05-24 |
JP2007513523A5 JP2007513523A5 (ja) | 2011-04-21 |
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US (3) | US7279743B2 (ja) |
JP (1) | JP2007513523A (ja) |
DE (1) | DE112004002310B4 (ja) |
TW (1) | TWI366249B (ja) |
WO (1) | WO2005057615A2 (ja) |
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Also Published As
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US20050148128A1 (en) | 2005-07-07 |
DE112004002310T5 (de) | 2006-12-14 |
DE112004002310B4 (de) | 2016-12-15 |
US7279743B2 (en) | 2007-10-09 |
TWI366249B (en) | 2012-06-11 |
TW200524085A (en) | 2005-07-16 |
US7833863B1 (en) | 2010-11-16 |
WO2005057615A3 (en) | 2005-11-03 |
WO2005057615A2 (en) | 2005-06-23 |
US20050116282A1 (en) | 2005-06-02 |
US7361558B2 (en) | 2008-04-22 |
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