JP2007324319A5 - - Google Patents

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Publication number
JP2007324319A5
JP2007324319A5 JP2006151862A JP2006151862A JP2007324319A5 JP 2007324319 A5 JP2007324319 A5 JP 2007324319A5 JP 2006151862 A JP2006151862 A JP 2006151862A JP 2006151862 A JP2006151862 A JP 2006151862A JP 2007324319 A5 JP2007324319 A5 JP 2007324319A5
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JP
Japan
Prior art keywords
test pad
circuit
wiring
semiconductor integrated
integrated circuit
Prior art date
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Application number
JP2006151862A
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English (en)
Japanese (ja)
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JP2007324319A (ja
JP5153089B2 (ja
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Priority to JP2006151862A priority Critical patent/JP5153089B2/ja
Priority claimed from JP2006151862A external-priority patent/JP5153089B2/ja
Publication of JP2007324319A publication Critical patent/JP2007324319A/ja
Publication of JP2007324319A5 publication Critical patent/JP2007324319A5/ja
Application granted granted Critical
Publication of JP5153089B2 publication Critical patent/JP5153089B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2006151862A 2006-05-31 2006-05-31 半導体集積回路の検査方法 Expired - Fee Related JP5153089B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006151862A JP5153089B2 (ja) 2006-05-31 2006-05-31 半導体集積回路の検査方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006151862A JP5153089B2 (ja) 2006-05-31 2006-05-31 半導体集積回路の検査方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012237464A Division JP5470436B2 (ja) 2012-10-29 2012-10-29 半導体集積回路

Publications (3)

Publication Number Publication Date
JP2007324319A JP2007324319A (ja) 2007-12-13
JP2007324319A5 true JP2007324319A5 (enExample) 2009-05-28
JP5153089B2 JP5153089B2 (ja) 2013-02-27

Family

ID=38856851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006151862A Expired - Fee Related JP5153089B2 (ja) 2006-05-31 2006-05-31 半導体集積回路の検査方法

Country Status (1)

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JP (1) JP5153089B2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9767248B2 (en) 2014-09-18 2017-09-19 Samsung Electronics, Co., Ltd. Semiconductor having cross coupled structure and layout verification method thereof
US9811626B2 (en) 2014-09-18 2017-11-07 Samsung Electronics Co., Ltd. Method of designing layout of semiconductor device
US9704862B2 (en) 2014-09-18 2017-07-11 Samsung Electronics Co., Ltd. Semiconductor devices and methods for manufacturing the same
US10026661B2 (en) 2014-09-18 2018-07-17 Samsung Electronics Co., Ltd. Semiconductor device for testing large number of devices and composing method and test method thereof
US10095825B2 (en) 2014-09-18 2018-10-09 Samsung Electronics Co., Ltd. Computer based system for verifying layout of semiconductor device and layout verify method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62224045A (ja) * 1986-03-26 1987-10-02 Toshiba Corp モニタパツドセル
JP2954076B2 (ja) * 1997-04-09 1999-09-27 広島日本電気株式会社 半導体集積回路ウェハ及びその試験方法

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