JP2007273942A - 複合材料を製造する方法及びウエハを選択する方法 - Google Patents
複合材料を製造する方法及びウエハを選択する方法 Download PDFInfo
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- JP2007273942A JP2007273942A JP2006285168A JP2006285168A JP2007273942A JP 2007273942 A JP2007273942 A JP 2007273942A JP 2006285168 A JP2006285168 A JP 2006285168A JP 2006285168 A JP2006285168 A JP 2006285168A JP 2007273942 A JP2007273942 A JP 2007273942A
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000002131 composite material Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 235000012431 wafers Nutrition 0.000 claims abstract description 158
- 239000012212 insulator Substances 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 21
- 239000013078 crystal Substances 0.000 abstract description 2
- 239000011148 porous material Substances 0.000 description 9
- 230000007704 transition Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000004816 latex Substances 0.000 description 1
- 229920000126 latex Polymers 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Laminated Bodies (AREA)
- Die Bonding (AREA)
Abstract
【解決手段】2つのウエハを用意するステップ31と、一方のウエハを他方のウエハに対して付着させ、特に接合させるステップ41とを備え、ウエハの境界もしくはその近傍で生じる結晶欠陥の量を減らすために、エッジロールオフ値を決定するステップ33が実行される方法に関する。エッジロールオフ値は、ウエハのエッジから約0.5〜2.5mm離れた位置で決定され及び/又は高さプロファイルの二次導関数を使用して決定する。
【選択図】 図3
Description
したがって、nmで表されるEROは、2つの場所の間、すなわち半径“a”の場所と半径“fqa”の場所との間の高さ(又は厚さ)の差である。“fqa”の値は、300mmウエハの場合、147.5mm〜149.5mmの半径の範囲となるように、特に149nmの半径となるように選択される。
これらのウエハは、二次導関数に基づくERO値を定めるレイテックス・ダイナサーチツールを使用して解析された。
Claims (7)
- 複合材料ウエハ、特にシリコンオンインシュレータ(SOI)タイプのウエハを製造するための方法において、
2つのウエハ(11,13)を用意するステップと、
一方のウエハを他方のウエハに対して付着させ、特に接合させるステップと、
を備え、
付着させる前に、各ウエハ(11,13)のプロファイルの二次導関数を使用して2つの各ウエハのエッジロールオフ(ERO)値を決定するとともに、50nmよりも大きい、特に100nmよりも大きい、更には150nmよりも大きいEROを有するウエハを使用し、
EROが、以下の式を確定することにより得られ、
ERO=Y(a)−Y(fqa)
a及びfqaがウエハの2つの半径位置に対応しており、Y(a)が二次導関数Y”がゼロとなる径方向位置でのウエハの高さに対応しており、Y(fqa)が外周(27)から約0.5mm〜2.5mm離れた、特に約1mm離れた径方向位置でのウエハの高さに対応していることを特徴とする、方法。 - 請求項1に記載の複合材料ウエハの製造プロセスに適したウエハを選択する方法において、
ウエハのプロファイルの二次導関数が、ウエハのエッジロールオフ(ERO)値を定めるために決定され、50nmよりも大きい、特に100nmよりも大きい、更には150nmよりも大きいEROを有するウエハだけが製造プロセスのために選択され、
EROが以下の式を確定することにより得られ、
ERO=Y(a)−Y(fqa)
a及びfqaがウエハの2つの半径位置に対応しており、Y(a)が二次導関数Y”がゼロとなる径方向位置でのウエハの高さに対応しており、Y(fqa)が外周(27)から約0.5mm〜2.5mm離れた、特に約1mm離れた径方向位置でのウエハの高さに対応していることを特徴とする、ウエハを選択する方法。 - 各ウエハ(11,13)が300mmタイプのウエハである、請求項1又は2に記載の方法。
- EROがウエハの幾つかの位置で決定され、個々の値から平均EROが計算される、請求項1〜3のいずれか一項に記載の方法。
- ウエハ同士を付着させる前に2つのウエハ(11,13)の少なくとも一方に絶縁層(15)を設けるステップを更に備える、請求項1〜4のいずれか一項に記載の方法。
- ウエハ(11,13)の一方に所定の分離領域(17)を形成するステップを更に備える、請求項1〜5のいずれか一項に記載の方法。
- 複合材料ウエハ(21)、特にシリコンオンインシュレータタイプのウエハの製造プロセスにおける、50nmよりも大きい、特に100nmよりも大きい、更には150nmよりも大きいエッジロールオフ値(ERO)を有するウエハの使用であって、
EROが以下の式を確定することにより得られ、
ERO=Y(a)−Y(fqa)
a及びfqaがウエハの2つの半径位置に対応しており、Y(a)が二次導関数Y”がゼロとなる径方向位置でのウエハの高さに対応しており、Y(fqa)が外周(27)から約0.5mm〜2.5mm離れた、特に約1mm離れた径方向位置でのウエハの高さに対応している、ウエハの使用。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP06290542A EP1840955B1 (en) | 2006-03-31 | 2006-03-31 | Method for fabricating a compound material and method for choosing a wafer |
EP06290542.7 | 2006-03-31 |
Publications (2)
Publication Number | Publication Date |
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JP2007273942A true JP2007273942A (ja) | 2007-10-18 |
JP4723455B2 JP4723455B2 (ja) | 2011-07-13 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP2006285168A Active JP4723455B2 (ja) | 2006-03-31 | 2006-10-19 | 複合材料を製造する方法及びウエハを選択する方法 |
Country Status (9)
Country | Link |
---|---|
US (1) | US7892861B2 (ja) |
EP (1) | EP1840955B1 (ja) |
JP (1) | JP4723455B2 (ja) |
KR (1) | KR100854800B1 (ja) |
CN (1) | CN100547761C (ja) |
AT (1) | ATE383656T1 (ja) |
DE (1) | DE602006000423T2 (ja) |
SG (1) | SG136024A1 (ja) |
TW (1) | TWI327745B (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008258304A (ja) * | 2007-04-03 | 2008-10-23 | Sumco Corp | 半導体基板の製造方法 |
KR20170051442A (ko) | 2014-09-11 | 2017-05-11 | 신에쯔 한도타이 가부시키가이샤 | 반도체 웨이퍼의 가공방법, 접합웨이퍼의 제조방법, 및 에피택셜 웨이퍼의 제조방법 |
JP2019208003A (ja) * | 2018-05-28 | 2019-12-05 | 瀋陽硅基科技有限公司 | フィルム貼付によってsoiの縁のstirを変更する方法 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
FR2891281B1 (fr) * | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
FR2947098A1 (fr) | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
JP5423384B2 (ja) | 2009-12-24 | 2014-02-19 | 株式会社Sumco | 半導体ウェーハおよびその製造方法 |
US8330245B2 (en) * | 2010-02-25 | 2012-12-11 | Memc Electronic Materials, Inc. | Semiconductor wafers with reduced roll-off and bonded and unbonded SOI structures produced from same |
US9156705B2 (en) | 2010-12-23 | 2015-10-13 | Sunedison, Inc. | Production of polycrystalline silicon by the thermal decomposition of dichlorosilane in a fluidized bed reactor |
JP5621702B2 (ja) * | 2011-04-26 | 2014-11-12 | 信越半導体株式会社 | 半導体ウェーハ及びその製造方法 |
DE102013201663B4 (de) * | 2012-12-04 | 2020-04-23 | Siltronic Ag | Verfahren zum Polieren einer Halbleiterscheibe |
FR2999801B1 (fr) | 2012-12-14 | 2014-12-26 | Soitec Silicon On Insulator | Procede de fabrication d'une structure |
CN103871870B (zh) * | 2014-02-28 | 2016-05-25 | 武汉新芯集成电路制造有限公司 | 一种去除晶圆键合边缘缺陷的方法 |
CN117497407B (zh) * | 2023-12-28 | 2024-04-09 | 物元半导体技术(青岛)有限公司 | Igbt器件的形成方法及igbt器件 |
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US20020187595A1 (en) * | 1999-08-04 | 2002-12-12 | Silicon Evolution, Inc. | Methods for silicon-on-insulator (SOI) manufacturing with improved control and site thickness variations and improved bonding interface quality |
WO2004008527A1 (en) * | 2002-07-17 | 2004-01-22 | S.O.I.Tec Silicon On Insulator Technologies | A method of increasing the area of a useful layer of material transferred onto a support |
EP1566830A1 (en) * | 2002-11-29 | 2005-08-24 | Shin-Etsu Handotai Co., Ltd | Method for manufacturing soi wafer |
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US20070040181A1 (en) * | 2002-12-27 | 2007-02-22 | General Electric Company | Crystalline composition, wafer, and semi-conductor structure |
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- 2006-03-31 EP EP06290542A patent/EP1840955B1/en active Active
- 2006-03-31 AT AT06290542T patent/ATE383656T1/de not_active IP Right Cessation
- 2006-03-31 DE DE602006000423T patent/DE602006000423T2/de active Active
- 2006-06-21 US US11/472,745 patent/US7892861B2/en active Active
- 2006-10-19 JP JP2006285168A patent/JP4723455B2/ja active Active
- 2006-11-06 TW TW095141057A patent/TWI327745B/zh active
- 2006-11-14 KR KR1020060112292A patent/KR100854800B1/ko active IP Right Grant
- 2006-11-22 CN CNB2006101467596A patent/CN100547761C/zh active Active
- 2006-11-23 SG SG200608167-3A patent/SG136024A1/en unknown
Patent Citations (3)
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US20020187595A1 (en) * | 1999-08-04 | 2002-12-12 | Silicon Evolution, Inc. | Methods for silicon-on-insulator (SOI) manufacturing with improved control and site thickness variations and improved bonding interface quality |
WO2004008527A1 (en) * | 2002-07-17 | 2004-01-22 | S.O.I.Tec Silicon On Insulator Technologies | A method of increasing the area of a useful layer of material transferred onto a support |
EP1566830A1 (en) * | 2002-11-29 | 2005-08-24 | Shin-Etsu Handotai Co., Ltd | Method for manufacturing soi wafer |
Non-Patent Citations (1)
Title |
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JPN6010072484, KIMURA M ET AL, ""A NEW METHOD FOR THE PRECISE MEASUREMENT OF WAFER ROLL OFF OF SILICON POLISHED WAFER"", JAPANESE JOURNAL OF APPLIED PHYSICS, 199901, vol. 38, no. 1A, PART 1, pages 38−39 * |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008258304A (ja) * | 2007-04-03 | 2008-10-23 | Sumco Corp | 半導体基板の製造方法 |
KR20170051442A (ko) | 2014-09-11 | 2017-05-11 | 신에쯔 한도타이 가부시키가이샤 | 반도체 웨이퍼의 가공방법, 접합웨이퍼의 제조방법, 및 에피택셜 웨이퍼의 제조방법 |
US9905411B2 (en) | 2014-09-11 | 2018-02-27 | Shin-Etsu Handotai Co., Ltd. | Method for processing semiconductor wafer, method for manufacturing bonded wafer, and method for manufacturing epitaxial wafer |
JP2019208003A (ja) * | 2018-05-28 | 2019-12-05 | 瀋陽硅基科技有限公司 | フィルム貼付によってsoiの縁のstirを変更する方法 |
Also Published As
Publication number | Publication date |
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KR100854800B1 (ko) | 2008-08-27 |
DE602006000423T2 (de) | 2008-05-21 |
SG136024A1 (en) | 2007-10-29 |
TW200737287A (en) | 2007-10-01 |
US7892861B2 (en) | 2011-02-22 |
ATE383656T1 (de) | 2008-01-15 |
DE602006000423D1 (de) | 2008-02-21 |
EP1840955B1 (en) | 2008-01-09 |
CN100547761C (zh) | 2009-10-07 |
TWI327745B (en) | 2010-07-21 |
CN101047144A (zh) | 2007-10-03 |
JP4723455B2 (ja) | 2011-07-13 |
KR20070098441A (ko) | 2007-10-05 |
EP1840955A1 (en) | 2007-10-03 |
US20070231931A1 (en) | 2007-10-04 |
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