JP2007273028A - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP2007273028A
JP2007273028A JP2006099182A JP2006099182A JP2007273028A JP 2007273028 A JP2007273028 A JP 2007273028A JP 2006099182 A JP2006099182 A JP 2006099182A JP 2006099182 A JP2006099182 A JP 2006099182A JP 2007273028 A JP2007273028 A JP 2007273028A
Authority
JP
Japan
Prior art keywords
memory cell
test mode
address signal
cell arrays
refresh operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006099182A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007273028A5 (enExample
Inventor
Hiroyuki Sadakata
博之 貞方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2006099182A priority Critical patent/JP2007273028A/ja
Priority to US11/727,915 priority patent/US7460426B2/en
Publication of JP2007273028A publication Critical patent/JP2007273028A/ja
Publication of JP2007273028A5 publication Critical patent/JP2007273028A5/ja
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C2029/2602—Concurrent test

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
JP2006099182A 2006-03-31 2006-03-31 半導体記憶装置 Pending JP2007273028A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006099182A JP2007273028A (ja) 2006-03-31 2006-03-31 半導体記憶装置
US11/727,915 US7460426B2 (en) 2006-03-31 2007-03-29 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006099182A JP2007273028A (ja) 2006-03-31 2006-03-31 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2007273028A true JP2007273028A (ja) 2007-10-18
JP2007273028A5 JP2007273028A5 (enExample) 2009-04-09

Family

ID=38604713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006099182A Pending JP2007273028A (ja) 2006-03-31 2006-03-31 半導体記憶装置

Country Status (2)

Country Link
US (1) US7460426B2 (enExample)
JP (1) JP2007273028A (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8112577B2 (en) * 2007-10-08 2012-02-07 Cisco Technology, Inc. Concurrently communicating refresh and read/write commands with a memory device
TWI360880B (en) * 2008-06-10 2012-03-21 Promos Technologies Inc Leakage test method for dynamic random access memo

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000357398A (ja) * 1999-05-04 2000-12-26 Samsung Electronics Co Ltd 外部アドレスにより自動リフレッシュ動作が行えるテストモードを有する同期式ｄｒａｍ及び自動リフレッシュ方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3199862B2 (ja) 1992-08-12 2001-08-20 日本テキサス・インスツルメンツ株式会社 半導体記憶装置
KR0141432B1 (ko) 1993-10-01 1998-07-15 기다오까 다까시 반도체 기억장치
JP3238806B2 (ja) 1993-10-01 2001-12-17 三菱電機株式会社 半導体記憶装置
US6392948B1 (en) * 1996-08-29 2002-05-21 Micron Technology, Inc. Semiconductor device with self refresh test mode
US5995429A (en) 1997-05-30 1999-11-30 Fujitsu Limited Semiconductor memory device capable of multiple word-line selection and method of testing same
JP2001243766A (ja) * 2000-02-29 2001-09-07 Fujitsu Ltd 半導体記憶装置
US6262928B1 (en) 2000-09-13 2001-07-17 Silicon Access Networks, Inc. Parallel test circuit and method for wide input/output DRAM
JP4078119B2 (ja) * 2002-04-15 2008-04-23 富士通株式会社 半導体メモリ
DE10245713B4 (de) 2002-10-01 2004-10-28 Infineon Technologies Ag Testsystem und Verfahren zum Testen von Speicherschaltungen
KR100564633B1 (ko) * 2004-09-25 2006-03-28 삼성전자주식회사 향상된 동작 성능을 가지는 반도체 메모리 장치 및 이에대한 액세스 제어 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000357398A (ja) * 1999-05-04 2000-12-26 Samsung Electronics Co Ltd 外部アドレスにより自動リフレッシュ動作が行えるテストモードを有する同期式ｄｒａｍ及び自動リフレッシュ方法

Also Published As

Publication number Publication date
US20070242545A1 (en) 2007-10-18
US7460426B2 (en) 2008-12-02

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