JP2007201424A - Manufacturing method of gan light-emitting diode - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a GaN-based LED capable of improving a problem that a reverse current is extremely increased along with conduction. <P>SOLUTION: The method comprises the steps of: (a) making an n-type GaN-based semiconductor layer 3 grow on a substrate 1; (b) making an intermediate layer 4 composed of a GaN-based semiconductor grow on the n-type GaN-based semiconductor layer 3 at a decreased substrate temperature so as to form a pit with a pit diameter of 0.05 μm or more having a hexagonal opening on its upper surface; (c) making an active layer 5 of a part up to a well layer formed at a position located farthest from the intermediate layer 4 grow on the intermediate layer 4, so as not to bury a pit on the upper surface of the intermediate layer 4; (d) burying the pit formed in a range from the intermediate layer 4 to the active layer 5 after the step of (c); and (e) making a p-type GaN-based semiconductor layer 6 grow on the active layer 5 after the step of (d), wherein in the step of (d), a substrate temperature is increased so as to bury the pit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a GaN-based light-emitting diode formed by stacking layers made of a group 3 nitride-based compound semiconductor.

A group 3 nitride compound semiconductor (hereinafter referred to as “GaN”) having a composition determined by the chemical formula Al _a In _b Ga _1-ab N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1). Also known as "system semiconductor". The GaN-based semiconductor includes, for example, those having an arbitrary composition such as GaN, InGaN, AlGaN, AlInGaN, AlN, and InN. In the above chemical formula, a part of the group 3 element is B (boron), Tl (thallium). In addition, those in which a part of N (nitrogen) is substituted with P (phosphorus), As (arsenic), Sb (antimony), Bi (bismuth), or the like are also included in the GaN-based semiconductor.

A GaN-based light emitting diode (hereinafter also referred to as “GaN-based LED”) is formed on an n-type GaN-based semiconductor layer (hereinafter also referred to as “n-type layer”), an active layer made of a GaN-based semiconductor, A p-type GaN-based semiconductor layer (hereinafter also referred to as a “p-type layer”) is sequentially grown to form a pn junction light-emitting element structure. A GaN-based LED whose active layer has a quantum well structure including a well layer and a barrier layer exhibits high luminous efficiency (Patent Document 1).
JP 2003-218396 A

  The conventional GaN-based LED has a problem that when energization is continuously performed in the forward direction, deterioration proceeds at the initial stage of energization, and the reverse current significantly increases. This problem is particularly noticeable in a GaN-based LED manufactured by forming the light-emitting element structure on a sapphire substrate by crystal growth.

  The main object of the present invention is to provide a method for manufacturing a GaN-based LED in which the problem that the reverse current significantly increases with energization is improved.

The manufacturing method of the present invention has the following characteristics.
(1) A method of manufacturing a GaN-based light emitting diode including an active layer including at least one well layer, wherein (a) a step of growing an n-type GaN-based semiconductor layer on a substrate; (b) the n An intermediate layer made of a GaN-based semiconductor is grown on the type GaN-based semiconductor layer at a low substrate temperature so that a pit with a hexagonal opening having a pit diameter of 0.05 μm or more is formed on the upper surface. And (c) not burying pits on the upper surface of the intermediate layer on the intermediate layer, at least a portion of the active layer up to the well layer formed farthest from the intermediate layer. A step of burying pits formed from the intermediate layer to the active layer after the steps of (d) and (c), and (e) after the steps of (d), on the active layer A p-type GaN-based semiconductor layer is grown on That has a step, and in the step of said (d), characterized in that raising the substrate temperature to fill the pits, a method of manufacturing a GaN-based light-emitting diode.
(2) The manufacturing method according to (1), wherein the intermediate layer is grown to a thickness of 0.1 μm or more.
(3) The manufacturing method according to (1) or (2), wherein the method used for growing the GaN-based semiconductor layer is a MOVPE method, and the substrate temperature when growing the intermediate layer is 650 ° C. to 850 ° C. .
(4) The manufacturing method according to any one of (1) to (3), wherein the intermediate layer is formed of GaN or AlGaN.
(5) The manufacturing method according to any one of (1) to (4), wherein the intermediate layer is grown undoped.
(6) The manufacturing method according to any one of (1) to (4), wherein an n-type impurity is added to at least a part of the intermediate layer.
(7) A GaN-based semiconductor layer formed between the n-type GaN-based semiconductor layer grown in the step (a) and the p-type GaN-based semiconductor layer grown in the step (d) The manufacturing method according to any one of (1) to (6), wherein no p-type impurity doping is performed.
(8) The manufacturing method according to any one of (1) to (7), wherein the substrate temperature is not changed between the step (b) and the step (c).
(9) The active layer is an active layer having the uppermost layer as a barrier layer, and in the step (c), the active layer is grown up to the uppermost layer so as not to fill the pits on the upper surface of the intermediate layer. The production method according to any one of (1) to (8).
(10) The active layer is an active layer having the uppermost layer as a barrier layer, and in the step (d), the barrier layer that is the uppermost layer of the active layer is grown while extending from the intermediate layer to the active layer. The manufacturing method according to any one of (1) to (8), wherein the formed pits are embedded.
(11) The manufacturing method according to any one of (1) to (10), wherein a cap layer is formed between the active layer and the p-type GaN-based semiconductor layer.
(12) The manufacturing method according to any one of (1) to (11), wherein in the step (e), the p-type GaN-based semiconductor layer is grown at a substrate temperature of less than 1000 ° C.
(13) In the step (e), the p-type GaN-based semiconductor layer is grown at a low substrate temperature so that pits are formed on the upper surface thereof, and thereafter, the p-type GaN-based semiconductor layer is further grown. The manufacturing method according to any one of (1) to (12), further including a step of increasing the substrate temperature in order to embed pits on the upper surface of the semiconductor layer.
(14) In the step (d), the substrate temperature is raised to a temperature higher than the substrate temperature when the p-type GaN-based semiconductor layer is grown in the step (e). The manufacturing method in any one of).

  According to the manufacturing method of the present invention, it is possible to obtain a highly reliable GaN-based LED in which the problem that the reverse current is remarkably increased with continuous energization is improved.

  FIG. 2 is a cross-sectional view showing a structural example of a GaN-based LED manufactured by the manufacturing method of the present invention. Reference numeral 1 denotes a sapphire substrate, on which an n-type contact layer 3 made of Si (silicon) -doped GaN with a film thickness of about 4 μm is formed via a buffer layer 2 made of AlGaN. On the n-type contact layer 3, an intermediate layer 4 made of undoped GaN and having a thickness of 0.2 μm is formed. The intermediate layer 4 is grown so that pits are formed on the upper surface. On the intermediate layer 4 is formed an active layer 5 having a quantum well structure in which seven barrier layers and six well layers are alternately stacked so that the lowermost layer and the uppermost layer serve as barrier layers. ing. The barrier layer is a Si-doped GaN layer having a thickness of 10 nm, and the well layer is an undoped InGaN layer (emission wavelength 400 nm) having a thickness of 5 nm. On the active layer 5, as a p-type layer 6, a p-type cladding layer 6 a made of Mg (magnesium) doped AlGaN with a thickness of 0.03 μm and a p-type contact layer made of Mg-doped GaN with a thickness of 0.15 μm. 6b are laminated in order. On the partially exposed surface of the n-type contact layer 3, there is an n-side electrode P1 formed by laminating Ti and aluminum (Al) with titanium (Ti) as a side in contact with the n-type contact layer 3 and heat-treating. Is formed. On the upper surface of the p-type contact layer 6b, a p-side electrode P2 formed by stacking Ni and gold (Au) with Ni (nickel) being in contact with the p-type contact layer 6b and performing heat treatment is formed on almost the entire surface. ing.

  As a method for growing the GaN-based semiconductor layer on the sapphire substrate 1, an organic metal compound vapor phase growth method (MOVPE method) can be suitably used. According to the MOVPE method, a high-quality GaN-based semiconductor crystal can be grown at a practically sufficient growth rate. The growth technology of GaN-based semiconductor crystals using the MOVPE method is known. For the equipment (growth furnace, control system, piping system), raw materials, carrier gas, basic growth conditions, etc., refer to the prior art as appropriate. Can do.

EXAMPLE A GaN-based LED shown in FIG. 2 was produced as follows.
First, a sapphire substrate 1 having a C-plane as a main surface was prepared, and this was mounted on a susceptor provided in a growth furnace of an MOVPE apparatus. Then, while supplying hydrogen gas into the growth furnace, the substrate was heated to 1100 ° C. or higher to remove organic contamination on the substrate surface. Then, the substrate temperature was lowered to 500 ° C., and trimethylaluminum (TMA), trimethylgallium (TMG) and ammonia were supplied as raw materials to grow the buffer layer 2. After the growth of the buffer layer 2, the substrate temperature was raised to 1000 ° C., and TMG, ammonia, and silane were supplied to grow the n-type contact layer 3. The supply amount of silane gas was adjusted so that the Si concentration in the n-type contact layer 3 was 3 × 10 ¹⁸ cm ⁻³ .

  When the growth of the n-type contact layer 3 was completed, the supply of the organometallic raw material and silane was stopped, and the substrate temperature was lowered to 750 ° C. Then, TMG and ammonia were supplied to grow the intermediate layer 4. Many pits were formed on the surface of the intermediate layer 4. When observed with an atomic force microscope (AFM), this pit had a hexagonal opening. As shown in FIG. 3, when the length of the diagonal line connecting the two opposite corners of the hexagon in the opening is defined as “pit diameter”, the pit diameter of the pit formed on the surface of the intermediate layer 4 is 0. It was 1 μm to 0.2 μm.

  After the growth of the intermediate layer 4, the active layer 5 was grown with the substrate temperature kept at 750 ° C. When growing the barrier layer, silane was supplied in addition to TMG and ammonia, and when growing the well layer, silane was stopped and trimethylindium (In) was supplied. When observed by AFM, pits were observed on the surface of the active layer 5, but the density (the average number of pits existing in the unit area) was substantially the same as the density of pits on the surface of the intermediate layer 4. It was. In addition, the pit diameter of the pits seen on the surface of the active layer 5 is smaller than the pit diameter of the pits seen on the surface of the intermediate layer 4, regardless of whether the active layer 5 is smaller in thickness than the intermediate layer 4. It was big. From this, the active layer 5 was grown in such a manner as to take over the pits on the surface of the intermediate layer 4 without embedding the pits formed on the surface of the intermediate layer 4 as schematically shown in FIG. It is considered a thing.

  When the growth of the active layer 3 was completed, the supply of the organometallic raw material and silane was stopped, and the substrate temperature was raised to 1025 ° C. while supplying ammonia and hydrogen gas. The temperature increase rate at this time was 110 ° C. per minute, and the temperature increase was completed in about 2.5 minutes. When observed by AFM, the pits were embedded during the temperature rising process, and the surface of the active layer 5 was in a state of extremely high flatness.

Thereafter, TMG, TMA, biscyclopentadienyl magnesium (Cp ₂ Mg) and ammonia were supplied as raw materials to grow the p-type cladding layer 6a. The supply amount of Cp ₂ Mg was adjusted so that the Mg concentration in the p-type cladding layer was 5 × 10 ¹⁹ cm ⁻³ .
When the p-type cladding layer 6a was grown, the supply of TMA was stopped and the p-type contact layer 6b was grown. The supply amount of Cp ₂ Mg was adjusted so that the Mg concentration in the p-type contact layer was 1 × 10 ²⁰ cm ⁻³ .
When the growth of the p-type contact layer 6b was completed, the substrate temperature was lowered to room temperature while flowing ammonia into the growth furnace. Thereafter, the obtained wafer was taken out of the MOVPE apparatus, and an annealing process was performed to activate Mg added as an impurity to the p-type layer.
Formation of the n-side electrode P1, formation of the p-side electrode P2, and cutting out of the chip from the wafer were performed using methods well known in this field.

  In the GaN-based LED manufactured in this way, the increase in reverse current when energized continuously in the forward direction is extremely small. Specifically, when an LED chip having a 0.35 mm square (when viewed from the upper surface side of the substrate) is manufactured, a current of 100 mA is continuously flowed in the forward direction for 50 hours, and then in the reverse direction. A reverse current that flows when a voltage of 5 V is applied to the capacitor is less than 1 μA. On the other hand, when the intermediate layer 4 was not provided, the current was made in the same manner except for this, but the current of 100 mA was continuously flowed in the forward direction for 5 hours. Only an LED chip was obtained in which the reverse current flowing when a voltage of 5 V was applied increased to a value greatly exceeding 1 μA.

The reason why the GaN-based LED in which the problem that the reverse current is remarkably increased with continuous energization is obtained in the above embodiment is not necessarily clear, but the present inventors consider as follows.
That is, since the GaN-based LED including the active layer includes a heterostructure in the pn junction, the GaN-based semiconductor layer constituting the pn junction is strained. Therefore, particularly in the initial stage of energization, the number of defects at the pn junction increases due to heat generation and distortion caused in the active layer due to energization, which seems to cause an increase in reverse current.
On the other hand, FIG. 1 is an explanatory view (sectional view) showing a structure of a GaN-based semiconductor layer (structure of a pn junction portion of a GaN-based LED) formed by the method of the above embodiment. FIG. 1A shows an intermediate layer 4 grown on an n-type GaN-based semiconductor layer 3 so that pits are formed on the upper surface. FIG. 1B shows a state where the active layer 5 is grown on the intermediate layer 4 so as not to fill the pits on the upper surface of the intermediate layer 4. FIG. 1 (c) shows a pit embedded by increasing the temperature. This embedding is considered to be caused by mass transport, and the hatched portion in FIG. 1C indicates a GaN-based semiconductor crystal in which pits are embedded. FIG. 1D shows a state where the p-type GaN-based semiconductor layer 6 is grown after the pits are buried. By forming the structure of FIG. 1D or in the process of forming the structure, the pn junction is stabilized by relaxing the strain and the like, thereby suppressing an increase in reverse current. It is thought that Further, by growing the p-type GaN-based semiconductor layer 6 to which the p-type impurity is added at a high concentration after the pits are buried, the p-type impurities supplied during the growth of the p-type GaN-based semiconductor layer 6 are in the pits. It is considered that the formation of a defect that becomes a reverse current path inside the active layer 5 and the intermediate layer 4 by diffusion is prevented.

As mentioned above, although this invention was demonstrated using the specific Example, this invention is not limited to the said Example.
The GaN-based semiconductor layer that can be included in the n-type layer, the intermediate layer, the active layer, the p-type layer, and other stacked bodies can be formed of any GaN-based semiconductor. Since the intermediate layer grows at a temperature at which pits are formed on the surface, deterioration in crystal quality is inevitable, but in order to alleviate this problem, it is necessary to form the intermediate layer with binary GaN. preferable. The same is true for the barrier layer included in the active layer. The n-type layer, the intermediate layer, and the p-type layer may be combined with a clad layer (carrier confinement layer), a contact layer, and other various functional layers, or such functional layers may be combined with the n-type layer, the intermediate layer, and the p-type layer. It may be provided inside the mold layer.

  When the MOVPE method is used to grow the GaN-based semiconductor layer, in order to grow the intermediate layer so that pits are formed on the surface thereof, the growth temperature of the layer is lower than 900 ° C., preferably 650 ° C. What is necessary is just to be 850 degreeC. The effect of the present invention becomes more prominent as the pit diameter of the pits on the surface of the intermediate layer is increased. A preferable pit diameter of the pit is 0.05 μm or more. Although there is no upper limit to the pit diameter of the pit, if it is 0.3 μm or more, the time required for embedding the pit by increasing the temperature after the growth of the active layer becomes longer, thereby increasing the thermal damage to the active layer. Tend. Since the pit diameter tends to increase as the growth temperature is lower and the hydrogen partial pressure in the atmosphere during crystal growth is higher, it can be controlled by adjusting the growth conditions. The addition of n-type impurities (Si, Ge, etc.) to the intermediate layer has a function of promoting the formation of pits. If the thickness of the intermediate layer is too small, the pit diameter of the pits formed on the surface does not become sufficiently large. However, if the thickness of the intermediate layer is 0.1 μm or more, the growth condition can be adjusted to the surface. Pits having the preferred pit diameter can be formed. The thickness of the intermediate layer is more preferably 0.15 μm or more, and particularly preferably 0.2 μm or more. There is no upper limit to the thickness of the intermediate layer, but if it is 1 μm or more, the time required for growth tends to be long, and the production efficiency tends to decrease. Considering the production efficiency, the preferable thickness of the intermediate layer is 0.15 μm to 0.3 μm.

  Doping to the intermediate layer can be arbitrarily performed as long as the light emitting element structure formed by the n-type layer, the active layer, and the p-type layer is not impaired. As the present inventors have confirmed, there was a tendency that the increase in the reverse current accompanying the energization was suppressed more when the n-type impurity concentration doped in the intermediate layer was lowered. Therefore, for the purpose of suppressing the increase in reverse current, it is most preferable that the intermediate layer is undoped. On the other hand, from the viewpoint of preventing a reduction in the electrostatic withstand voltage of the element, it is desirable to impart moderate conductivity to the intermediate layer by doping. When doping the intermediate layer, it is preferable to use an n-type impurity (Si, Ge, etc.) that is difficult to move in the crystal. In a preferred embodiment, the intermediate layer has a structure in which an n-type doped layer and an undoped layer are stacked. If the intermediate layer is configured in this way, it is possible to prevent a decrease in electrostatic withstand voltage without impairing the effect of preventing an increase in reverse current.

  In order to grow the active layer so as not to fill the pits on the upper surface of the intermediate layer, when only the active layer is grown without providing the intermediate layer, using the growth conditions in which pits are formed on the surface, The active layer may be grown. In the case of an MQW active layer composed of an InGaN well layer and an (In) GaN barrier layer, the growth temperature of the active layer is 900 ° C. or lower, preferably 650 ° C. to 850 ° C. It may be set to ° C. When the intermediate layer and the active layer are grown at the same temperature, the time required for temperature adjustment can be reduced.

  By making the active layer a quantum well structure, a GaN-based LED with high luminous efficiency can be obtained. The quantum well structure may be a single quantum well (SQW) structure or a multiple quantum well (MQW) structure. Even in this case, the uppermost layer is preferably a barrier layer. In order to suppress thermal damage to the well layer in the step of embedding pits, the uppermost barrier layer is preferably grown to a thickness of 10 nm or more, more preferably 15 nm or more. The uppermost barrier layer may be grown thicker than other barrier layers. The uppermost barrier layer may be formed of a GaN-based semiconductor having a crystal composition different from that of other barrier layers. On the other hand, the lowermost layer of the active layer may be either a well layer or a barrier layer. Doping to the well layer and the barrier layer can be arbitrarily performed. Doping is preferably performed using an n-type impurity (Si, Ge, etc.) that is difficult to move in the GaN-based semiconductor crystal. In a preferred embodiment, doping is performed only on the barrier layer in order to suppress a decrease in crystallinity of the well layer that becomes a light emission field.

  After the active layer is grown, in order to fill the pit formed from the intermediate layer to the active layer, it takes a sufficient time for the filling to occur, and the substrate temperature is changed from the growth temperature of the active layer to the growth temperature of the p-type layer. Just raise it. After reaching the growth temperature of the p-type layer, it can be held for a certain period of time until the growth of the p-type layer is started. Further, the substrate temperature may be once raised to a temperature higher than the growth temperature of the p-type layer. It is desirable to continue supplying the Group 5 raw material until the p-type layer starts growing after the active layer has been grown so that the active layer is not decomposed in preference to the pit filling. The embedding can also be performed while growing a barrier layer as the uppermost layer of the active layer. In the above embodiment, hydrogen gas is supplied in addition to the group 5 source gas at the time of pit embedding, but part or all of this hydrogen gas can be replaced with an inert gas such as nitrogen gas or rare gas.

  A cap layer having a function of preventing decomposition of the active layer and a function of preventing carrier overflow may be formed between the active layer and the p-type layer. This cap layer may be grown undoped, or a part or all of it may be doped with an n-type impurity. The formation of such a cap layer may be performed after the formation of the active layer and after the pits formed from the intermediate layer to the active layer are embedded by heating, so that the pits on the upper surface of the intermediate layer are not embedded. After forming the active layer, a cap layer may be formed so as not to embed the pits, and thereafter, the temperature may be increased to embed pits formed from the intermediate layer to the cap layer. It is also possible to embed this pit while growing the cap layer.

In a preferred embodiment, the substrate temperature during the growth of the p-type layer is set to less than 1000 ° C. in order to reduce thermal damage to the active layer during the growth of the p-type layer. The substrate temperature during the growth of the p-type layer in this embodiment is preferably 980 ° C. or lower, more preferably 960 ° C. or lower, and further preferably 950 ° C. or lower. In this embodiment, before the p-type layer is grown, when the pit formed from the intermediate layer to the active layer is buried, the substrate temperature may be raised to a temperature higher than the substrate temperature during the growth of the p-type layer. This is particularly effective in reducing the time required for embedding pits.
By lowering the substrate temperature during the growth of the p-type layer, pits may be formed on the surface of the p-type layer. In this case, after the growth of the p-type layer (after the supply of the Group 3 material is stopped) This can be embedded by raising the substrate temperature. In the case where the p-type layer has a multilayer structure, when pits are formed on the surface of the previously grown layer, the substrate temperature is raised before the next layer is grown and the pits are buried, and then the substrate is again formed. The temperature may be lowered and the next layer may be grown. When embedding pits on the surface of the p-type layer, it is preferable to raise the temperature while supplying the Group 5 material so that decomposition does not occur in preference to the embedding.
In the embodiment in which the GaN-based semiconductor layer to be finally grown on the substrate is grown so that pits are formed on the surface and the pits are embedded by a subsequent temperature increase, the substrate heating is stopped after the pit embedding is completed. The substrate temperature is lowered until the temperature reaches a temperature at which the substrate can be removed from the growth furnace. At this time, the supply of the hydrogen source gas (hydrogen gas, ammonia, etc.) to the substrate is stopped between the completion of the pit embedding and the substrate temperature falling below 600 ° C. Inactivation of added p-type impurities (Mg, Zn, etc.) due to hydrogen passivation can be suppressed.

When the GaN-based semiconductor layer included in the element is formed of Al _x Ga _1-x N (0 ≦ x ≦ 1) excluding the active layer, the emission wavelength of the active layer is set to an ultraviolet wavelength or a wavelength close to the ultraviolet wavelength. In this case, it is possible to suppress a loss due to the GaN-based semiconductor layer other than the active layer absorbing light emitted from the active layer.

  In addition to the above description, the present invention can be variously modified without departing from the spirit of the invention.

It is explanatory drawing (sectional drawing) which shows the structure of the GaN-type semiconductor layer formed with the manufacturing method of an Example. It is sectional drawing which shows an example of the GaN-type LED manufactured by implementing this invention. It is a figure explaining the pit diameter said to this specification.

Explanation of symbols

1 substrate 2 buffer layer 3 n-type contact layer 4 intermediate layer 5 active layer 6a p-type cladding layer 6b p-type contact layer P1 n-side electrode P2 p-side electrode

Claims (14)

A method of manufacturing a GaN-based light emitting diode having an active layer including at least one well layer,
(A) growing an n-type GaN-based semiconductor layer on the substrate;
(B) On the n-type GaN-based semiconductor layer, an intermediate layer made of a GaN-based semiconductor is lowered so that pits having a hexagonal opening on the upper surface and having a pit diameter of 0.05 μm or more are formed. Growing at substrate temperature;
(C) A step of growing on the intermediate layer at least a portion of the active layer up to the well layer formed farthest from the intermediate layer so as not to fill the pits on the upper surface of the intermediate layer When,
(D) After the step (c), a step of embedding pits formed from the intermediate layer to the active layer;
(E) After the step (d), a step of growing a p-type GaN-based semiconductor layer on the active layer;
Have
In the step (d), the substrate temperature is increased in order to embed the pits. The manufacturing method according to claim 1, wherein the intermediate layer is grown to a thickness of 0.1 μm or more. The manufacturing method according to claim 1 or 2, wherein a method of growing the GaN-based semiconductor layer is a MOVPE method, and a substrate temperature when the intermediate layer is grown is set to 650 ° C to 850 ° C. The manufacturing method according to claim 1, wherein the intermediate layer is formed of GaN or AlGaN. The manufacturing method according to claim 1, wherein the intermediate layer is grown undoped. The manufacturing method in any one of Claims 1-4 which adds an n-type impurity to at least one part of the said intermediate | middle layer. Intentional p-type is formed on the GaN-based semiconductor layer formed between the n-type GaN-based semiconductor layer grown in the step (a) and the p-type GaN-based semiconductor layer grown in the step (d). The manufacturing method according to claim 1, wherein doping of impurities is not performed. The manufacturing method according to claim 1, wherein the substrate temperature is not changed between the step (b) and the step (c). The active layer is an active layer whose uppermost layer is a barrier layer, and in the step (c), the active layer is grown up to the uppermost layer so as not to fill the pits on the upper surface of the intermediate layer. Item 9. The production method according to any one of Items 1 to 8. The active layer is an active layer whose uppermost layer is a barrier layer. In the step (d), the active layer is formed from the intermediate layer to the active layer while growing the barrier layer which is the uppermost layer of the active layer. The manufacturing method according to claim 1, wherein pits are embedded. The manufacturing method according to claim 1, wherein a cap layer is formed between the active layer and the p-type GaN-based semiconductor layer. The manufacturing method according to claim 1, wherein in the step (e), the p-type GaN-based semiconductor layer is grown at a substrate temperature of less than 1000 ° C. In the step (e), the p-type GaN-based semiconductor layer is grown at a low substrate temperature so that pits are formed on the upper surface of the p-type GaN-based semiconductor layer. The manufacturing method according to claim 1, further comprising a step of increasing the substrate temperature in order to embed pits on the upper surface. 14. In the step (d), the substrate temperature is raised to a temperature higher than the substrate temperature when the p-type GaN-based semiconductor layer is grown in the step (e). Manufacturing method.

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