JP2007194594A - Thin-film transistor - Google Patents

Thin-film transistor Download PDF

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JP2007194594A
JP2007194594A JP2006314818A JP2006314818A JP2007194594A JP 2007194594 A JP2007194594 A JP 2007194594A JP 2006314818 A JP2006314818 A JP 2006314818A JP 2006314818 A JP2006314818 A JP 2006314818A JP 2007194594 A JP2007194594 A JP 2007194594A
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thin film
oxide semiconductor
insulating film
semiconductor thin
film layer
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JP5099740B2 (en
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Mamoru Furuta
守 古田
Takashi Hirao
孝 平尾
Hiroshi Furuta
寛 古田
Tokiyoshi Matsuda
時宜 松田
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Casio Computer Co Ltd
Kochi Prefecture Sangyo Shinko Center
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Casio Computer Co Ltd
Kochi Prefecture Sangyo Shinko Center
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film transistor having an oxide semiconductor thin-film layer composed of zinc oxide as the main component, wherein the conductivity of the oxide semiconductor thin-film layer is controlled by controlling hydrogen concentration within the oxide semiconductor thin-film layer that forms a channel of the thin-film transistor to effect leakage current suppression, threshold voltage reduction, and electron mobility increase. <P>SOLUTION: The thin-film transistor comprises an oxide semiconductor thin-film layer composed of zinc oxide as the main component, deposited on a substrate, and forming a channel; a gate insulating film; and a gate electrode at least, wherein hydrogen is contained at least in the oxide semiconductor thin-film layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は薄膜トランジスタに係り、より詳しくは、酸化亜鉛を主成分とする酸化物半導体薄膜層を活性層に有する薄膜トランジスタに関する。   The present invention relates to a thin film transistor, and more particularly to a thin film transistor having an oxide semiconductor thin film layer containing zinc oxide as a main component in an active layer.

酸化亜鉛あるいは酸化マグネシウム亜鉛等の酸化物が優れた半導体(活性層)の性質を示すことは古くから知られており、近年薄膜トランジスタ（以下、TFTと略）、発光デバイス、透明導電膜等の電子デバイス応用を目指し、これらの化合物を用いた半導体薄膜層の研究開発が活発化している。
酸化亜鉛や酸化マグネシウム亜鉛を半導体薄膜層として用いたTFTは、従来液晶ディスプレイに主に用いられているアモルファスシリコン(a−Si：H)を半導体薄膜層として用いたアモルファスシリコンTFTと比較して電子移動度が大きく、優れたTFT特性を有し、また、室温付近の低温でも結晶薄膜が得られることで高い移動度が期待できる等の利点もあり、積極的な開発が進められている。 It has long been known that oxides such as zinc oxide or magnesium zinc oxide exhibit excellent semiconductor (active layer) properties, and in recent years, such as thin film transistors (hereinafter abbreviated as TFTs), light-emitting devices, transparent conductive films, etc. Aiming at device application, research and development of semiconductor thin film layers using these compounds has been activated.
TFTs using zinc oxide or magnesium zinc oxide as semiconductor thin film layers are electrons compared to amorphous silicon TFTs using amorphous silicon (a-Si: H), which is mainly used in conventional liquid crystal displays, as semiconductor thin film layers. Active development is underway, with advantages such as high mobility, excellent TFT characteristics, and the expectation of high mobility by obtaining a crystalline thin film even at low temperatures near room temperature.

酸化物半導体薄膜層を用いたTFTとしては、ボトムゲート型及びトップゲート型の構造が報告されている。   As a TFT using an oxide semiconductor thin film layer, a bottom gate type and a top gate type structure have been reported.

ボトムゲート構造の一例としては、基板上より順にゲート電極及びゲート絶縁膜が形成され、その上面を被覆して酸化亜鉛を主成分とする酸化物半導体薄膜層が形成されている構造が知られている。該構造は液晶ディスプレイの駆動素子として現在事業化されているボトムゲート型アモルファスシリコンTFTの構造と類似しており、該アモルファスシリコンTFTの製造のプロセスを応用できるため、酸化亜鉛TFTにも多く用いられている。   As an example of a bottom gate structure, a structure is known in which a gate electrode and a gate insulating film are formed in order from the substrate, and an oxide semiconductor thin film layer mainly composed of zinc oxide is formed covering the upper surface. Yes. This structure is similar to the structure of bottom gate type amorphous silicon TFTs that are currently commercialized as driving elements for liquid crystal displays, and can be applied to the process of manufacturing the amorphous silicon TFTs, so it is often used for zinc oxide TFTs. ing.

トップゲート構造の一例としては、基板上より順に一対のソース・ドレイン電極、酸化物半導体薄膜層、ゲート絶縁膜、ゲート電極を積層して形成される構造を例示することができる。   As an example of the top gate structure, a structure in which a pair of source / drain electrodes, an oxide semiconductor thin film layer, a gate insulating film, and a gate electrode are stacked in this order from the substrate can be exemplified.

ボトムゲート型の薄膜トランジスタは、構造上、酸化物半導体薄膜層がゲート絶縁膜上に積層されているため、結晶性が不十分な成膜初期の領域を活性層として用いざるを得ず、十分な移動度が得られないという問題点を抱えている。一方、トップゲート型の薄膜トランジスタは、酸化物半導体薄膜層の上部にゲート絶縁膜を設けている構造を有するので、酸化物半導体薄膜層の上部の結晶性の良好な領域を活性層として用いることができるという点でボトムゲート型の薄膜トランジスタより有効である。   A bottom-gate thin film transistor has a structure in which an oxide semiconductor thin film layer is stacked over a gate insulating film, and thus an area at an early stage of film formation with insufficient crystallinity must be used as an active layer. There is a problem that mobility cannot be obtained. On the other hand, a top-gate thin film transistor has a structure in which a gate insulating film is provided above an oxide semiconductor thin film layer. Therefore, a region having favorable crystallinity above the oxide semiconductor thin film layer can be used as an active layer. It is more effective than a bottom-gate thin film transistor in that it can be made.

しかしながら、酸化亜鉛は耐熱性が充分でなく、TFT製造プロセス中の熱処理により酸素や亜鉛が脱離し格子欠陥を形成する事が知られている。該格子欠陥は、電気的には浅い不純物準位を形成し、酸化物半導体薄膜層の低抵抗化を引き起こす。そのため、酸化亜鉛を薄膜トランジスタの活性層に用いた場合、ゲート電圧を印加しなくてもドレイン電流が流れるノーマリーオン型即ちデプレッション型の動作となり、欠陥準位の増大とともに、しきい電圧が小さくなり、リーク電流が増大する。
また、格子欠陥は活性層となる酸化亜鉛中のキャリアの誘起を妨げ、キャリア濃度を減少させる。キャリア濃度の減少は活性層の導電率を引き下げ、薄膜トランジスタの電子移動度、電流伝達特性（例えば、サブスレッショルド特性やしきい電圧）に影響する。 However, zinc oxide does not have sufficient heat resistance, and it is known that oxygen and zinc are desorbed and form lattice defects by heat treatment during the TFT manufacturing process. The lattice defect forms a shallow impurity level electrically and causes a reduction in resistance of the oxide semiconductor thin film layer. For this reason, when zinc oxide is used for the active layer of a thin film transistor, the drain current flows without applying a gate voltage, that is, a normally-on type operation, that is, a depletion type operation. As the defect level increases, the threshold voltage decreases. , Leakage current increases.
In addition, lattice defects prevent the induction of carriers in zinc oxide serving as an active layer and reduce the carrier concentration. The decrease in the carrier concentration lowers the conductivity of the active layer and affects the electron mobility and current transfer characteristics (eg, subthreshold characteristics and threshold voltage) of the thin film transistor.

上記した如く、格子欠陥はトランジスタの電流伝達特性に影響を与える。
一方、前記格子欠陥以外に酸化亜鉛中に浅い不純物準位を形成する元素として水素が報告されている（例えば、下記非特許文献１参照）。従って、格子欠陥以外にもTFT製造工程で導入される水素等の元素が酸化亜鉛TFTの特性に影響を与えると考えられる。
しかしながら、非特許文献１を含め、酸化亜鉛などの酸化物中の含有元素がTFT特性に与える影響に関する記載がなされた文献は見られない。 As described above, the lattice defects affect the current transfer characteristics of the transistor.
On the other hand, hydrogen has been reported as an element that forms a shallow impurity level in zinc oxide in addition to the lattice defects (for example, see Non-Patent Document 1 below). Therefore, it is considered that elements such as hydrogen introduced in the TFT manufacturing process other than lattice defects affect the characteristics of the zinc oxide TFT.
However, there are no documents including the non-patent document 1 that describe the influence of contained elements in oxides such as zinc oxide on TFT characteristics.

Cetin Kilic他１著，「n-type doping of oxides by hydrogen」，APPLIED PHYSICS LETTERS，2002年7月１日Vol.81，No.1 ，p.73−75Cetin Kilic et al., “N-type doping of oxides by hydrogen”, APPLIED PHYSICS LETTERS, July 1, 2002, Vol. 81, No. 1, p. 73-75

本発明は、上記現状に鑑みてなされたものであって、酸化亜鉛を主成分とする酸化物半導体薄膜層を有する薄膜トランジスタにおいて、薄膜トランジスタのチャネルを形成する酸化物半導体薄膜層中の水素濃度を制御する事により、酸化物半導体薄膜層の導電率を制御し、リーク電流の抑制、しきい電圧の低減、電子移動度の向上といった効果を奏する薄膜トランジスタを提供することを目的とする。   The present invention has been made in view of the above situation, and in a thin film transistor having an oxide semiconductor thin film layer containing zinc oxide as a main component, the hydrogen concentration in the oxide semiconductor thin film layer forming the channel of the thin film transistor is controlled. Accordingly, an object of the present invention is to provide a thin film transistor that controls the conductivity of an oxide semiconductor thin film layer and exhibits effects such as suppression of leakage current, reduction of threshold voltage, and improvement of electron mobility.

請求項１に係る発明は、基板上にチャネルとして形成される酸化亜鉛を主成分とする酸化物半導体薄膜層と、ゲート絶縁膜と、ゲート電極とを少なくとも有し、該酸化物半導体薄膜層中に水素を少なくとも含有することを特徴とする薄膜トランジスタに関する。   The invention according to claim 1 includes at least an oxide semiconductor thin film layer mainly composed of zinc oxide formed as a channel on a substrate, a gate insulating film, and a gate electrode. The present invention relates to a thin film transistor characterized by containing at least hydrogen.

請求項２に係る発明は、前記酸化物半導体薄膜層中に含まれる水素濃度が、５×1020cm−3以上、７×1021cm−3以下であることを特徴とする請求項１記載の薄膜トランジスタに関する。 The invention according to claim 2 is characterized in that the concentration of hydrogen contained in the oxide semiconductor thin film layer is 5 × 10 20 cm −3 or more and 7 × 10 21 cm −3 or less. The present invention relates to a thin film transistor.

請求項３に係る発明は、前記薄膜トランジスタが、前記基板上に形成される前記酸化物半導体薄膜層と、該酸化物半導体薄膜層の上表面及び側面を被覆して形成される前記ゲート絶縁膜と、該ゲート絶縁膜上に積載された前記ゲート電極とを有するトップゲート型薄膜トランジスタであって、該ゲート絶縁膜が、酸化珪素膜、酸窒化珪素膜、窒化珪素膜、あるいは窒化珪素に酸素もしくは酸素を構成元素に含む化合物を用いることで酸素がドーピングされた膜のいずれかを少なくとも一部に用いた絶縁膜であることを特徴とする請求項１又は２記載の薄膜トランジスタに関する。   According to a third aspect of the present invention, the thin film transistor includes the oxide semiconductor thin film layer formed on the substrate, and the gate insulating film formed to cover an upper surface and side surfaces of the oxide semiconductor thin film layer. A top gate type thin film transistor having the gate electrode stacked on the gate insulating film, wherein the gate insulating film is a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or silicon nitride with oxygen or oxygen 3. The thin film transistor according to claim 1, wherein the thin film transistor is an insulating film using at least a part of a film doped with oxygen by using a compound containing as a constituent element.

請求項４に係る発明は、前記薄膜トランジスタが、前記基板上に形成される前記ゲート電極と、該ゲート電極を被覆して形成される前記ゲート絶縁膜と、該ゲート絶縁膜上に形成される前記酸化物半導体薄膜層と、該酸化物半導体薄膜層上に形成される保護絶縁膜とを有するボトムゲート型薄膜トランジスタであって、該保護絶縁膜が酸化珪素膜、酸窒化珪素膜、窒化珪素膜、あるいは窒化珪素に酸素もしくは酸素を構成元素に含む化合物を用いることで酸素がドーピングされた膜のいずれかを少なくとも一部に用いた絶縁膜であることを特徴とする請求項１又は２記載の薄膜トランジスタに関する。   According to a fourth aspect of the present invention, the thin film transistor includes the gate electrode formed on the substrate, the gate insulating film formed to cover the gate electrode, and the gate insulating film formed on the gate insulating film. A bottom-gate thin film transistor having an oxide semiconductor thin film layer and a protective insulating film formed on the oxide semiconductor thin film layer, wherein the protective insulating film is a silicon oxide film, a silicon oxynitride film, a silicon nitride film, 3. The thin film transistor according to claim 1, wherein the thin film transistor is an insulating film using at least a part of a film doped with oxygen by using oxygen or a compound containing oxygen as a constituent element in silicon nitride. About.

請求項１に係る発明によれば、絶縁基板上にチャネルとして形成される酸化亜鉛を主成分とする酸化物半導体薄膜層と、ゲート絶縁膜と、ゲート電極とを少なくとも有する薄膜トランジスタにおいて、酸化物半導体薄膜層中に水素を少なくとも含有することにより、酸化物半導体薄膜層の電気伝導度、即ちキャリア濃度を制御することができ、チャネル中の導電率が制御された薄膜トランジスタとなる。   According to the invention of claim 1, an oxide semiconductor in a thin film transistor having at least an oxide semiconductor thin film layer mainly composed of zinc oxide formed as a channel on an insulating substrate, a gate insulating film, and a gate electrode. By containing at least hydrogen in the thin film layer, the electric conductivity of the oxide semiconductor thin film layer, that is, the carrier concentration can be controlled, and a thin film transistor in which the conductivity in the channel is controlled is obtained.

請求項２に係る発明によれば、薄膜トランジスタのチャネルを形成する酸化物半導体薄膜層中に含まれる水素濃度が、5×1020cm−3以上、7×1021cm−３以下であることにより、活性層中に充分なキャリアが誘起され、リーク電流の抑制された、低しきい電圧で電子移動度の高い薄膜トランジスタとなる。 According to the second aspect of the present invention, the hydrogen concentration contained in the oxide semiconductor thin film layer forming the channel of the thin film transistor is 5 × 10 20 cm −3 or more and 7 × 10 21 cm −3 or less. Thus, a thin film transistor having a low threshold voltage and a high electron mobility, in which sufficient carriers are induced in the active layer and leakage current is suppressed.

請求項３に係る発明によれば、薄膜トランジスタが基板上に形成される酸化物半導体薄膜層と、該酸化物半導体薄膜層の上表面及び側面を被覆して形成されるゲート絶縁膜と、該ゲート絶縁膜上に積載されたゲート電極とを有するトップゲート型薄膜トランジスタであることにより、酸化物半導体薄膜層の上部の結晶性の良好な領域を活性層として用いた薄膜トランジスタを提供できる。
また、ゲート絶縁膜が、酸化珪素膜、酸窒化珪素膜、窒化珪素膜、あるいは窒化珪素に酸素もしくは酸素を構成元素に含む化合物を用いることで酸素がドーピングされた膜のいずれかを少なくとも一部に用いた絶縁膜であることにより、ゲート絶縁膜成膜時における酸素又は亜鉛の脱離による格子欠陥を防ぐことができる。そのため、酸化物半導体薄膜層中への水素拡散量をより厳密に制御でき、リーク電流の抑制、しきい電圧の低下、電子移動度の向上といった効果をより確実に奏する薄膜トランジスタとなる。 According to the invention of claim 3, the oxide semiconductor thin film layer in which the thin film transistor is formed on the substrate, the gate insulating film formed to cover the upper surface and the side surface of the oxide semiconductor thin film layer, and the gate By being a top-gate thin film transistor including a gate electrode stacked over an insulating film, a thin film transistor using a region with favorable crystallinity above the oxide semiconductor thin film layer as an active layer can be provided.
Further, at least a part of the gate insulating film is any one of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a film in which silicon nitride is doped with oxygen or a compound containing oxygen as a constituent element. By using the insulating film used in the above, lattice defects due to desorption of oxygen or zinc at the time of forming the gate insulating film can be prevented. Therefore, the amount of hydrogen diffused into the oxide semiconductor thin film layer can be controlled more strictly, and the thin film transistor can exhibit more reliably the effects of suppressing leakage current, lowering the threshold voltage, and improving electron mobility.

請求項４に係る発明によれば、薄膜トランジスタが基板上に形成されるゲート電極と、該ゲート電極を被覆して形成されるゲート絶縁膜と、該ゲート絶縁膜上に形成される酸化物半導体薄膜層と、該酸化物半導体薄膜層上に形成される保護絶縁膜とを有するボトムゲート型薄膜トランジスタであることで、液晶ディスプレイの駆動素子として現在事業化されているボトムゲート型アモルファスシリコンTFTの製造のプロセスを応用することができ、新たな設備投資を削減して、酸化亜鉛を主成分とする酸化物半導体薄膜層を有する薄膜トランジスタの事業化を図ることができる。
また、保護絶縁膜が酸化珪素膜、酸窒化珪素膜、窒化珪素膜、あるいは窒化珪素に酸素もしくは酸素を構成元素に含む化合物を用いることで酸素がドーピングされた膜のいずれかを少なくとも一部に用いた絶縁膜であることにより、保護絶縁膜成膜時における酸素又は亜鉛の脱離による格子欠陥を防ぐことができる。そのため、酸化物半導体薄膜層中への水素拡散量をより厳密に制御でき、リーク電流の抑制、しきい電圧の低下、電子移動度の向上といった効果をより確実に奏する薄膜トランジスタとなる。 According to the invention of claim 4, a gate electrode in which a thin film transistor is formed on a substrate, a gate insulating film formed so as to cover the gate electrode, and an oxide semiconductor thin film formed on the gate insulating film A bottom gate type thin film transistor having a layer and a protective insulating film formed on the oxide semiconductor thin film layer, thereby producing a bottom gate type amorphous silicon TFT currently commercialized as a driving element of a liquid crystal display The process can be applied, new equipment investment can be reduced, and a thin film transistor having an oxide semiconductor thin film layer mainly composed of zinc oxide can be commercialized.
Further, at least a part of the protective insulating film is a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a film in which silicon nitride is doped with oxygen or a compound containing oxygen as a constituent element. The use of the insulating film can prevent lattice defects due to desorption of oxygen or zinc when forming the protective insulating film. Therefore, the amount of hydrogen diffused into the oxide semiconductor thin film layer can be controlled more strictly, and the thin film transistor can exhibit more reliably the effects of suppressing leakage current, lowering the threshold voltage, and improving electron mobility.

本発明に係る薄膜トランジスタの実施例について、図面を参照しながら以下説明する。   Embodiments of a thin film transistor according to the present invention will be described below with reference to the drawings.

図１は本発明の第一実施例に係る薄膜トランジスタの構造を示す断面図である。薄膜トランジスタ１００は、基板１、一対のソース・ドレイン電極２、酸化物半導体薄膜層３、第一ゲート絶縁膜４、コンタクト部５ａ、一対のソース・ドレイン外部電極２ａ、第二ゲート絶縁膜６、ゲート電極７、表示電極８を有しており、これら各構成を積層したトップゲート型として形成されている。   FIG. 1 is a sectional view showing the structure of a thin film transistor according to a first embodiment of the present invention. The thin film transistor 100 includes a substrate 1, a pair of source / drain electrodes 2, an oxide semiconductor thin film layer 3, a first gate insulating film 4, a contact portion 5a, a pair of source / drain external electrodes 2a, a second gate insulating film 6, and a gate. It has an electrode 7 and a display electrode 8, and is formed as a top gate type in which these components are stacked.

薄膜トランジスタ１００は、図１に示す通り、基板１上に形成される。   The thin film transistor 100 is formed on the substrate 1 as shown in FIG.

基板１上には、一対のソース・ドレイン電極２が積層されている。この一対のソース・ドレイン電極２は、基板１上面に間隔を有して配置されている。   A pair of source / drain electrodes 2 are stacked on the substrate 1. The pair of source / drain electrodes 2 are arranged on the upper surface of the substrate 1 with a gap.

酸化物半導体薄膜層３は、基板１と一対のソース・ドレイン電極２上に積層されている。
酸化物半導体薄膜層３は、一対のソース・ドレイン電極２の電極間にチャネルを形成するように配置されており、酸化亜鉛を主成分とする酸化物半導体から形成されている。ここで、酸化亜鉛を主成分とする酸化物半導体とは、真性酸化亜鉛の他、Li，Na，N，C等のp型ドーパント及びB，Al，Ga，In等のn型ドーパント、及びMg，Be等がドーピングされた酸化亜鉛を含む。 The oxide semiconductor thin film layer 3 is stacked on the substrate 1 and the pair of source / drain electrodes 2.
The oxide semiconductor thin film layer 3 is disposed so as to form a channel between the pair of source / drain electrodes 2, and is formed of an oxide semiconductor containing zinc oxide as a main component. Here, the oxide semiconductor containing zinc oxide as a main component includes intrinsic zinc oxide, p-type dopants such as Li, Na, N, and C, and n-type dopants such as B, Al, Ga, and In, and Mg. And zinc oxide doped with Be or the like.

第一ゲート絶縁膜４は、酸化物半導体薄膜層３の上側表面のみを被覆するように形成されている。この第一ゲート絶縁膜４は、ゲート絶縁膜の一部として設けられ、酸化物半導体薄膜層３を製造工程でのレジスト剥離液から保護する保護膜としての役割をも果たすものである。   The first gate insulating film 4 is formed so as to cover only the upper surface of the oxide semiconductor thin film layer 3. The first gate insulating film 4 is provided as a part of the gate insulating film, and also serves as a protective film for protecting the oxide semiconductor thin film layer 3 from a resist stripping solution in the manufacturing process.

第二ゲート絶縁膜６は、一対のソース・ドレイン電極２、酸化物半導体薄膜層３側面及び第一ゲート絶縁膜４の表面全面を被覆するように積層されている。このように、第二ゲート絶縁膜６が積層されることにより、酸化物半導体薄膜層３表面を第一ゲート絶縁膜４にて、側面を第二ゲート絶縁膜６にて完全に被覆することができる。   The second gate insulating film 6 is laminated so as to cover the pair of source / drain electrodes 2, the side surfaces of the oxide semiconductor thin film layer 3, and the entire surface of the first gate insulating film 4. Thus, by laminating the second gate insulating film 6, the surface of the oxide semiconductor thin film layer 3 can be completely covered with the first gate insulating film 4 and the side surface can be completely covered with the second gate insulating film 6. it can.

第一ゲート絶縁膜４及び第二ゲート絶縁膜６は、酸化珪素（SiOx）膜、酸窒化珪素（SiON）膜、窒化珪素（SiNx）膜、あるいは窒化珪素（SiNx）に酸素もしくは酸素を構成元素に含む化合物を用いることで酸素がドーピングされた膜により形成される。この第一ゲート絶縁膜４及び第二ゲート絶縁膜６としては、酸化珪素（SiOx）や酸窒化珪素（SiON）に比較して誘電率の大きい、SiNxに酸素あるいは酸素を構成元素として含む化合物、例えばN2O、を用いることで酸素がドーピングされた膜が好ましく用いられる。
第一ゲート絶縁膜４及び第二ゲート絶縁膜６は、例えばプラズマ化学気相成長（PCVD)法により形成される。このとき、プラズマ化学気相成長（PCVD)法による成膜は酸化物半導体薄膜層の還元もしくは酸素や亜鉛の脱離が生じない基板温度である250℃以下で実施することが望ましい。 The first gate insulating film 4 and the second gate insulating film 6 are composed of silicon oxide (SiOx) film, silicon oxynitride (SiON) film, silicon nitride (SiNx) film, or silicon nitride (SiNx) with oxygen or oxygen as a constituent element. By using the compound contained in the film, a film doped with oxygen is formed. As the first gate insulating film 4 and the second gate insulating film 6, a compound having a dielectric constant larger than that of silicon oxide (SiOx) or silicon oxynitride (SiON), SiNx containing oxygen or oxygen as a constituent element, For example, a film doped with oxygen by using N 2 O is preferably used.
The first gate insulating film 4 and the second gate insulating film 6 are formed by plasma chemical vapor deposition (PCVD), for example. At this time, it is desirable to perform film formation by plasma enhanced chemical vapor deposition (PCVD) at 250 ° C. or lower, which is a substrate temperature at which reduction of the oxide semiconductor thin film layer or desorption of oxygen and zinc does not occur.

一対のソース・ドレイン外部電極２ａは、それぞれ対応するソース・ドレイン電極２とコンタクト部５ａを介して接続される。   The pair of source / drain external electrodes 2a are connected to the corresponding source / drain electrodes 2 via the contact portions 5a.

ゲート電極７は、第二ゲート絶縁膜６上に形成されている。このゲート電極７は、薄膜トランジスタに印加するゲート電圧により酸化物半導体薄膜層３中の電子密度を制御する役割を果たすものである。   The gate electrode 7 is formed on the second gate insulating film 6. The gate electrode 7 serves to control the electron density in the oxide semiconductor thin film layer 3 by a gate voltage applied to the thin film transistor.

表示電極８は、液晶ディスプレイに用いる液晶に薄膜トランジスタを介して電圧を印加するために形成される。この電極は可視光に対する高い透過率が要求されるため、インジウムスズ酸化物(ITO)などを用いた酸化物導電性薄膜が形成される。なお、図１では省略されているが、表示電極８は第二ゲート絶縁膜上を右方向に延出されて形成されているものである。   The display electrode 8 is formed in order to apply a voltage to the liquid crystal used for the liquid crystal display via a thin film transistor. Since this electrode requires high transmittance for visible light, an oxide conductive thin film using indium tin oxide (ITO) or the like is formed. Although omitted in FIG. 1, the display electrode 8 is formed to extend rightward on the second gate insulating film.

薄膜トランジスタの製造工程が終了後、酸化物半導体薄膜層３は、少なくとも水素を含むものとする。酸化物半導体薄膜層３中の水素濃度は、好ましくは5×1020cm−3以上、7×1021cm−3以下となるようにそれぞれの工程の製造条件を調整する。水素濃度が5×1020cm−3より低い場合、薄膜トランジスタの活性層中に充分なキャリアが誘起されず、リーク電流は小さくなるものの電子移動度は向上しない。また、水素濃度が7×1021cm−3より高い場合、活性層の抵抗率が減少し、薄膜トランジスタがノーマリーオン型即ちデプレッション型の動作となり、リーク電流が増大する。そのため、水素濃度が5×1020cm−3以上、7×1021cm−3以下の範囲外ではいずれの場合も好ましくない。 After the manufacturing process of the thin film transistor is completed, the oxide semiconductor thin film layer 3 includes at least hydrogen. The manufacturing conditions of each step are adjusted so that the hydrogen concentration in the oxide semiconductor thin film layer 3 is preferably 5 × 10 20 cm −3 or more and 7 × 10 21 cm −3 or less. When the hydrogen concentration is lower than 5 × 10 20 cm −3 , sufficient carriers are not induced in the active layer of the thin film transistor and the leakage current is reduced, but the electron mobility is not improved. On the other hand, when the hydrogen concentration is higher than 7 × 10 21 cm −3 , the resistivity of the active layer decreases, the thin film transistor operates in a normally-on type, that is, a depletion type, and the leakage current increases. Therefore, in any case, the hydrogen concentration is outside the range of 5 × 10 20 cm −3 or more and 7 × 10 21 cm −3 or less.

本発明に係る薄膜トランジスタ（TFT)の第一実施例の製造方法について、図２に基づいて以下に説明する。   A manufacturing method of the first embodiment of the thin film transistor (TFT) according to the present invention will be described below with reference to FIG.

まず、図２（１）に示す如く、基板１上全面に金属薄膜を形成した後、この薄膜にフォトリソグラフィーを施すことにより一対のソース・ドレイン電極２を形成する。   First, as shown in FIG. 2A, after a metal thin film is formed on the entire surface of the substrate 1, a pair of source / drain electrodes 2 is formed by subjecting this thin film to photolithography.

次いで、図２（２）に示す如く、基板１及び一対のソース・ドレイン電極２上の全面に酸化物半導体薄膜層３として、酸化亜鉛を主成分とする酸化物半導体を例えば50〜100nm程度の膜厚で形成する。酸化物半導体薄膜層が真性酸化亜鉛（ZnO）の場合、半導体薄膜の形成には高純度酸化亜鉛のセラミックをターゲットとしたマグネトロンスパッタ法を用い、アルゴン（Ar）と酸素（O2）の混合ガスによるプラズマ放電にて基板上に半導体薄膜を形成する。なお、プラズマ放電の前に真空容器内の真空度が１×10−4Pa以下になるまで排気した後、アルゴンと酸素の混合ガスを導入する。スパッタリング時の圧力は1〜10Pa程度であるので、真空チャンバー内の残留水分に起因する水素の割合は原子濃度で酸化亜鉛の１／104以下に抑えられる。この場合、酸化物半導体薄膜成膜後の水素の原子濃度は5×1019cm−3以下となる。なお、この水素濃度は二次イオン質量分析（SIMS）法により求めることができる。 Next, as shown in FIG. 2 (2), an oxide semiconductor thin film layer 3 is formed on the entire surface of the substrate 1 and the pair of source / drain electrodes 2, and an oxide semiconductor containing zinc oxide as a main component is about 50 to 100 nm, for example. It is formed with a film thickness. When the oxide semiconductor thin film layer is intrinsic zinc oxide (ZnO), the semiconductor thin film is formed by a magnetron sputtering method using a high-purity zinc oxide ceramic as a target, and a mixed gas of argon (Ar) and oxygen (O 2 ) A semiconductor thin film is formed on the substrate by plasma discharge. Before plasma discharge, the vacuum vessel is evacuated until the degree of vacuum is 1 × 10 −4 Pa or less, and then a mixed gas of argon and oxygen is introduced. Since the pressure at the time of sputtering is about 1 to 10 Pa, the proportion of hydrogen due to residual moisture in the vacuum chamber can be suppressed to 1/10 4 or less of zinc oxide in terms of atomic concentration. In this case, the atomic concentration of hydrogen after forming the oxide semiconductor thin film is 5 × 10 19 cm −3 or less. The hydrogen concentration can be determined by secondary ion mass spectrometry (SIMS) method.

次にZnO上に低抵抗化しない手法及び条件で第一ゲート絶縁膜４を形成する。第一ゲート絶縁膜の形成をNH3とSiH4の混合ガスを用いてを行う場合、NH3とSiH4の流量比を変化させることで、酸化物半導体薄膜層内の水素濃度を制御することができる（下記試験例参照）。
第一ゲート絶縁膜４としては、酸化珪素（SiOx）膜、酸窒化珪素（SiON）膜、窒化珪素（SiNx）膜、あるいは窒化珪素（SiNx）に酸素もしくは酸素を構成元素に含む化合物を用いることで酸素がドーピングされた膜等のシリコン系絶縁膜が用いられることが望ましい。なかでもSiNxに酸素あるいは酸素を構成元素として含む化合物、例えばN2Oを用いて酸素をドーピングした膜などが望ましい。その理由はこれらの構成成分は誘電率が高く、酸化物半導体薄膜層３の亜鉛や酸素の脱離の防止の観点からも優れているからである。
なお、酸化物半導体薄膜層中の水素濃度の制御方法としては、上記したものの他に、ゲート絶縁膜成膜中の基板温度やガス種、プラズマ処理の条件等を変化させる方法も挙げることができる。また、酸化物半導体薄膜層成膜時に水分を導入する、具体的にはスパッタリング中に水蒸気を導入したり、ジエチル亜鉛（DEZ）と水蒸気を交互に導入する原子層製膜（Atomic Layer Deposition：ALD）を行ったりする方法も挙げることができる。 Next, the first gate insulating film 4 is formed on the ZnO by a method and conditions that do not reduce the resistance. When performing with NH 3 and a mixed gas of SiH 4 to form the first gate insulating film, by changing the flow ratio of NH 3 and SiH 4, by controlling the hydrogen concentration in the oxide semiconductor thin film layer (See the test example below).
As the first gate insulating film 4, a silicon oxide (SiOx) film, a silicon oxynitride (SiON) film, a silicon nitride (SiNx) film, or a silicon nitride (SiNx) containing oxygen or a compound containing oxygen as a constituent element is used. It is desirable to use a silicon insulating film such as a film doped with oxygen. In particular, a film obtained by doping oxygen with SiNx using oxygen or a compound containing oxygen as a constituent element, for example, N 2 O, is desirable. This is because these components have a high dielectric constant and are excellent from the viewpoint of preventing the elimination of zinc and oxygen from the oxide semiconductor thin film layer 3.
Note that as a method for controlling the hydrogen concentration in the oxide semiconductor thin film layer, in addition to the above-described method, a method of changing the substrate temperature, gas type, plasma treatment conditions, etc. during the formation of the gate insulating film can also be exemplified. . Atomic layer deposition (ALD), which introduces moisture during the formation of oxide semiconductor thin film layers, specifically introduces water vapor during sputtering or alternately introduces diethyl zinc (DEZ) and water vapor. ) Can also be mentioned.

図２（３）に示す如く、前記第一ゲート絶縁膜４上にフォトレジストをコーティングし、パターニングされたフォトレジスト４ａをマスクとして、前記第一ゲート絶縁膜４をドライエッチングし、次いで酸化物半導体薄膜層３に対しウェットエッチングを行う。   As shown in FIG. 2C, a photoresist is coated on the first gate insulating film 4, the first gate insulating film 4 is dry-etched using the patterned photoresist 4a as a mask, and then the oxide semiconductor Wet etching is performed on the thin film layer 3.

図２（４）は前記酸化物半導体薄膜層３のウェットエッチング後にフォトレジスト４ａを除去した断面を示しており、酸化物半導体薄膜層３と同一形状の第一ゲート絶縁膜４を有するTFT活性層領域が形成されている。第一ゲート絶縁膜４は、酸化物半導体薄膜層３との界面形成に加えて、活性領域をパターン形成する時の酸化物半導体薄膜層３を保護する役目も同時に果たしている。即ち、活性層パターニング後のフォトレジスト４ａを剥離する場合に使用するレジスト剥離液が酸化物半導体薄膜層３表面に接すると、薄膜表面や結晶粒界をエッチングで荒らしてしまうが、第一ゲート絶縁膜４が酸化物半導体薄膜層３表面に存在することで、フォトリソグラフィー工程におけるレジスト剥離液といった各種薬液に対する保護膜としての機能を果たし、酸化物半導体薄膜層３の表面あれを防ぐことができる。   FIG. 2 (4) shows a cross section in which the photoresist 4a is removed after wet etching of the oxide semiconductor thin film layer 3, and the TFT active layer having the first gate insulating film 4 having the same shape as the oxide semiconductor thin film layer 3 is shown. A region is formed. In addition to forming an interface with the oxide semiconductor thin film layer 3, the first gate insulating film 4 also plays a role of protecting the oxide semiconductor thin film layer 3 when patterning the active region. That is, when the resist stripping solution used for stripping the photoresist 4a after the active layer patterning contacts the surface of the oxide semiconductor thin film layer 3, the surface of the thin film and the crystal grain boundary are roughened by etching. The presence of the film 4 on the surface of the oxide semiconductor thin film layer 3 serves as a protective film against various chemicals such as a resist stripping solution in a photolithography process, and can prevent surface roughness of the oxide semiconductor thin film layer 3.

TFT活性層領域のパターン形成後、図２（５）に示す如く、第一ゲート絶縁膜４及び一対のソース・ドレイン電極２を被覆するように、基板１、一対のソース・ドレイン電極２、酸化物半導体薄膜層３、及び第一ゲート絶縁膜４上全面に第二ゲート絶縁膜６を形成し、その後、ソース・ドレイン電極上にコンタクトホール５を開口する。この場合、第二ゲート絶縁膜６は第一ゲート絶縁膜４（界面制御型絶縁膜）と同様の条件で形成することが望ましい。   After the patterning of the TFT active layer region, as shown in FIG. 2 (5), the substrate 1, the pair of source / drain electrodes 2, the oxide film so as to cover the first gate insulating film 4 and the pair of source / drain electrodes 2. A second gate insulating film 6 is formed on the entire surface of the physical semiconductor thin film layer 3 and the first gate insulating film 4, and then contact holes 5 are opened on the source / drain electrodes. In this case, the second gate insulating film 6 is desirably formed under the same conditions as the first gate insulating film 4 (interface control type insulating film).

最後に図２（６）に示す如く、第二ゲート絶縁膜６上に金属膜からなるゲート電極７を形成し、ゲート電極７と同一材料にて一対のソース・ドレイン外部電極２ａをコンタクト部５aを介して対応する一対のソース・ドレイン電極２と接続するよう形成する。その後、表示電極８を形成することで第一実施例のTFTが完成する。   Finally, as shown in FIG. 2 (6), a gate electrode 7 made of a metal film is formed on the second gate insulating film 6, and a pair of source / drain external electrodes 2 a are made of the same material as the gate electrode 7 and contact parts 5 a. It connects so that it may connect with a pair of corresponding source / drain electrodes 2 via. Thereafter, the display electrode 8 is formed to complete the TFT of the first embodiment.

次いで、本発明の第二実施例に係る薄膜トランジスタの構造について図３を用いて以下説明する。第二実施例の構造は、液晶ディスプレイの駆動素子として現在事業化されているボトムゲート型アモルファスシリコンTFTの構造と類似しており、アモルファスシリコンTFTの製造のプロセスを応用できるので、新たな設備投資を削減して酸化亜鉛TFTの事業化を図れる点で有効である。   Next, the structure of the thin film transistor according to the second embodiment of the present invention will be described with reference to FIG. The structure of the second embodiment is similar to the structure of the bottom-gate type amorphous silicon TFT that is currently commercialized as a driving element for liquid crystal displays, and can be applied to the amorphous silicon TFT manufacturing process. This is effective in that it can reduce the amount of zinc oxide and commercialize zinc oxide TFTs.

図３は本発明の第二実施例に係る薄膜トランジスタ１０１の構造を示す断面図である。薄膜トランジスタ１０１は、基板９、ゲート電極１０、ゲート絶縁膜１１、酸化亜鉛を主成分とする酸化物半導体薄膜層１２、保護絶縁膜１３、第一オーバーコート絶縁膜１４、一対のソース・ドレイン電極１５、第二オーバーコート絶縁膜１６を有してなり、図３に示すように、上記の各構成を積層して形成されている。   FIG. 3 is a cross-sectional view showing the structure of the thin film transistor 101 according to the second embodiment of the present invention. The thin film transistor 101 includes a substrate 9, a gate electrode 10, a gate insulating film 11, an oxide semiconductor thin film layer 12 mainly composed of zinc oxide, a protective insulating film 13, a first overcoat insulating film 14, and a pair of source / drain electrodes 15. The second overcoat insulating film 16 is provided, and as shown in FIG.

薄膜トランジスタ１０１は、図３に示す通り、基板９上に形成される。   The thin film transistor 101 is formed on the substrate 9 as shown in FIG.

基板９上には、ゲート電極１０が形成されている。   A gate electrode 10 is formed on the substrate 9.

ゲート絶縁膜１１は、ゲート電極１０を被覆するように基板９上の全面に積層されている。   The gate insulating film 11 is laminated on the entire surface of the substrate 9 so as to cover the gate electrode 10.

酸化物半導体薄膜層１２は、ゲート電極１０を横断してゲート絶縁膜１１の一部を被覆するように形成されている。酸化物半導体薄膜層１２は酸化亜鉛を主成分とする酸化物半導体から形成されている。   The oxide semiconductor thin film layer 12 is formed so as to cover a part of the gate insulating film 11 across the gate electrode 10. The oxide semiconductor thin film layer 12 is formed of an oxide semiconductor containing zinc oxide as a main component.

保護絶縁膜１３は、酸化物半導体薄膜層１２の上面を被覆するように積層されている。保護絶縁膜１３は、酸化亜鉛からなる酸化物半導体薄膜層１２を損傷及び還元脱離から保護するために設けられるが、製造工程において酸化物半導体薄膜層１２をレジスト剥離液から保護する保護膜としての役割も果たしている。
保護絶縁膜１３は、酸化珪素（SiOx）膜、酸窒化珪素（SiON）膜、窒化珪素（SiNx）膜、あるいは窒化珪素（SiNx）に酸素もしくは酸素を構成元素に含む化合物を用いることで酸素がドーピングされた膜により形成される。この保護絶縁膜１３としては、酸化珪素（SiOx）や酸窒化珪素（SiON）に比較して誘電率の大きい、SiNxに酸素あるいは酸素を構成元素として含む化合物、例えばN2O、を用いることで酸素がドーピングされた膜が好ましく用いられる。
保護絶縁膜１３は、例えばプラズマ化学気相成長（PCVD)法により形成される。このとき、プラズマ化学気相成長（PCVD)法による成膜は酸化物半導体薄膜層の還元もしくは亜鉛や酸素の脱離が生じない基板温度である250℃以下で実施することが望ましい。 The protective insulating film 13 is laminated so as to cover the upper surface of the oxide semiconductor thin film layer 12. The protective insulating film 13 is provided to protect the oxide semiconductor thin film layer 12 made of zinc oxide from damage and reductive desorption. As a protective film that protects the oxide semiconductor thin film layer 12 from the resist stripping solution in the manufacturing process. Also plays a role.
The protective insulating film 13 is formed by using a silicon oxide (SiOx) film, a silicon oxynitride (SiON) film, a silicon nitride (SiNx) film, or silicon nitride (SiNx) by using oxygen or a compound containing oxygen as a constituent element. It is formed by a doped film. As this protective insulating film 13, a compound having a dielectric constant larger than that of silicon oxide (SiOx) or silicon oxynitride (SiON) and containing oxygen or oxygen as a constituent element in SiNx, such as N 2 O, is used. A film doped with oxygen is preferably used.
The protective insulating film 13 is formed by, for example, a plasma chemical vapor deposition (PCVD) method. At this time, it is desirable to perform film formation by plasma enhanced chemical vapor deposition (PCVD) at 250 ° C. or lower, which is a substrate temperature at which reduction of the oxide semiconductor thin film layer or desorption of zinc or oxygen does not occur.

第一オーバーコート絶縁膜１４は、薄膜トランジスタ１０１のデバイス保護の目的で設けられ、保護絶縁膜１３の全面及び酸化物半導体薄膜層１２の側面を被覆するように積層されている。
第一オーバーコート絶縁膜１４を設けることで、保護絶縁膜１３が被覆していない酸化物半導体薄膜層１２の側表面を確実に被覆することができる。 The first overcoat insulating film 14 is provided for the purpose of device protection of the thin film transistor 101 and is laminated so as to cover the entire surface of the protective insulating film 13 and the side surface of the oxide semiconductor thin film layer 12.
By providing the first overcoat insulating film 14, the side surface of the oxide semiconductor thin film layer 12 that is not covered with the protective insulating film 13 can be reliably covered.

一対のソース・ドレイン電極１５は保護絶縁膜１３、第一オーバーコート絶縁膜１４に開口したコンタクトホールを介して、酸化物半導体薄膜層１２と接するように互いに間隔を有して形成される。   The pair of source / drain electrodes 15 are formed at a distance from each other so as to be in contact with the oxide semiconductor thin film layer 12 through contact holes opened in the protective insulating film 13 and the first overcoat insulating film 14.

第二オーバーコート絶縁膜１６は、薄膜トランジスタ１０１のデバイス保護の目的で設けられ、薄膜トランジスタの全面を被覆するように積層されている。
第二オーバーコート絶縁膜１６を設けることにより、薄膜トランジスタ１０１のデバイス全体をより確実に保護することができる。 The second overcoat insulating film 16 is provided for the purpose of protecting the device of the thin film transistor 101 and is laminated so as to cover the entire surface of the thin film transistor.
By providing the second overcoat insulating film 16, the entire device of the thin film transistor 101 can be more reliably protected.

薄膜トランジスタの製造工程が終了後、第一実施例に係るTFTと同様に酸化物半導体薄膜層１２は、少なくとも水素を含むものとする。酸化物半導体薄膜層３中の水素濃度は、好ましくは5×1020cm−3以上、7×1021cm−3以下となるようにそれぞれの工程の製造条件を調整する。 After the manufacturing process of the thin film transistor is completed, the oxide semiconductor thin film layer 12 includes at least hydrogen as in the TFT according to the first embodiment. The manufacturing conditions of each step are adjusted so that the hydrogen concentration in the oxide semiconductor thin film layer 3 is preferably 5 × 10 20 cm −3 or more and 7 × 10 21 cm −3 or less.

次に、本発明の第二実施例に係るボトムゲート型TFTの製法について、図４に基づいて以下に説明する。   Next, a method for manufacturing the bottom gate type TFT according to the second embodiment of the present invention will be described below with reference to FIG.

図４（１）に示される如く、ガラス等からなる基板９上全面に、マグネトロンスパッタ法等により形成し、フォトリソグラフィーによりゲート電極１０を形成する。   As shown in FIG. 4A, a gate electrode 10 is formed on the entire surface of the substrate 9 made of glass or the like by a magnetron sputtering method or the like, and by photolithography.

次いで、図４（２）に示される如く、ゲート電極１０を被覆するように基板９上の全面にゲート絶縁膜１１を形成する。
このゲート絶縁膜１１の形成方法は、特に限定されないが、大面積基板への成膜が可能なプラズマ化学気相成長（PCVD）法を用いることが好ましい。
ゲート絶縁膜１１の成膜後に、酸素（O2）あるいは亜酸化窒素（N2O）といった酸化性ガスを用いたプラズマにより、基板表面を清浄化することが好ましい。特に、酸化性ガスとして酸素を用いた場合は、ArやXe、He、Krといった希ガスを酸素に添加したプラズマを用いることで、酸素ラジカルの発生量が増大し、酸化物半導体薄膜層表面に吸着された有機成分や水分に対するクリーニング効率が増大すると同時に、添加ガスによるスパッタ効果により酸化物半導体薄膜層表面の金属不純物が除去可能となるため、より好ましい。 Next, as shown in FIG. 4B, a gate insulating film 11 is formed on the entire surface of the substrate 9 so as to cover the gate electrode 10.
The method for forming the gate insulating film 11 is not particularly limited, but it is preferable to use a plasma enhanced chemical vapor deposition (PCVD) method capable of forming a film over a large area substrate.
After the gate insulating film 11 is formed, the substrate surface is preferably cleaned with plasma using an oxidizing gas such as oxygen (O 2 ) or nitrous oxide (N 2 O). In particular, when oxygen is used as the oxidizing gas, the amount of oxygen radicals generated is increased by using a plasma in which a rare gas such as Ar, Xe, He, or Kr is added to oxygen, and the surface of the oxide semiconductor thin film layer is increased. The cleaning efficiency for the adsorbed organic component and moisture is increased, and at the same time, metal impurities on the surface of the oxide semiconductor thin film layer can be removed by the sputtering effect of the additive gas, which is more preferable.

ゲート絶縁膜１１の形成後、図４（３）に示される如く、ゲート絶縁膜１１の全面に酸化物半導体薄膜層１２を例えば50〜100nm程度の膜厚で形成する。第一実施例のTFTと同様に、酸化物半導体薄膜層の形成には高純度酸化亜鉛のセラミックをターゲットとしたマグネトロンスパッタ法を用い、アルゴン（Ar）と酸素の混合ガスによるプラズマ放電にて基板上に半導体薄膜を形成する。   After the formation of the gate insulating film 11, as shown in FIG. 4C, the oxide semiconductor thin film layer 12 is formed on the entire surface of the gate insulating film 11 with a film thickness of, for example, about 50 to 100 nm. As with the TFT of the first embodiment, the oxide semiconductor thin film layer is formed by a magnetron sputtering method using a high-purity zinc oxide ceramic as a target by plasma discharge with a mixed gas of argon (Ar) and oxygen. A semiconductor thin film is formed thereon.

酸化物半導体薄膜層１２の形成後、図４（４）に示される如く、酸化物半導体薄膜層の全面を被覆する保護絶縁膜１３を形成する。
保護絶縁膜１３は、酸化珪素（SiOx）膜、酸窒化珪素（SiON）膜、窒化珪素（SiNx）膜、あるいは窒化珪素（SiNx）に酸素もしくは酸素を構成元素に含む化合物を用いることで酸素がドーピングされた膜等のシリコン系絶縁膜が用いられることが望ましい。なかでもSiNxに酸素あるいは酸素を構成元素として含む化合物、例えばN2Oを用いることで酸素がドーピングされた膜などが望ましい。その理由はこれらの構成成分は誘電率が高く、酸化物半導体薄膜層３の亜鉛や酸素の脱離の防止の観点からも優れているからである。
保護絶縁膜１３の形成に際しては、プラズマ化学気相成長（PCVD）法を用いることが好ましい。 After the oxide semiconductor thin film layer 12 is formed, as shown in FIG. 4D, a protective insulating film 13 that covers the entire surface of the oxide semiconductor thin film layer is formed.
The protective insulating film 13 is formed by using a silicon oxide (SiOx) film, a silicon oxynitride (SiON) film, a silicon nitride (SiNx) film, or silicon nitride (SiNx) by using oxygen or a compound containing oxygen as a constituent element. It is desirable to use a silicon-based insulating film such as a doped film. In particular, a film in which oxygen is doped with SiNx by using oxygen or a compound containing oxygen as a constituent element, such as N 2 O, is desirable. This is because these components have a high dielectric constant and are excellent from the viewpoint of preventing the elimination of zinc and oxygen from the oxide semiconductor thin film layer 3.
In forming the protective insulating film 13, it is preferable to use a plasma enhanced chemical vapor deposition (PCVD) method.

保護絶縁膜１３の形成後、保護絶縁膜１３の上表面にフォトレジストをコーティングし、パターニングされたフォトレジストをマスクとして、保護絶縁膜１３をエッチングし、次いでパターニングされた保護絶縁膜１３をマスクとして酸化物半導体薄膜層１２に対しウェットエッチングを行う。これにより、チャネル領域、即ち、デバイスの外形形状を有する酸化物半導体薄膜層１２上に、同一平面形状の保護絶縁膜１３が積層された構造が形成される。   After the formation of the protective insulating film 13, a photoresist is coated on the upper surface of the protective insulating film 13, the protective insulating film 13 is etched using the patterned photoresist as a mask, and then the patterned protective insulating film 13 is used as a mask. Wet etching is performed on the oxide semiconductor thin film layer 12. As a result, a structure in which the protective insulating film 13 having the same planar shape is laminated on the channel region, that is, the oxide semiconductor thin film layer 12 having the outer shape of the device is formed.

上記した如く、酸化物半導体薄膜層１２及び保護絶縁膜１３に対して形状加工を行った後、フォトレジストを剥離し、図４（５）に示される如く、保護絶縁膜１３、酸化物半導体薄膜層１２及びゲート絶縁膜１１の全面を被覆するように第一オーバーコート絶縁膜１４を形成する。第一オーバーコート絶縁膜１４を形成することにより、チャネル層としての酸化物半導体薄膜層１２の機能を保ちつつ、第一オーバーコート絶縁膜１４によって酸化物半導体薄膜層１２を完全に被覆する構造を実現することができる。   As described above, after the shape processing is performed on the oxide semiconductor thin film layer 12 and the protective insulating film 13, the photoresist is peeled off, and as shown in FIG. 4 (5), the protective insulating film 13, the oxide semiconductor thin film A first overcoat insulating film 14 is formed so as to cover the entire surface of the layer 12 and the gate insulating film 11. By forming the first overcoat insulating film 14, the oxide semiconductor thin film layer 12 is completely covered with the first overcoat insulating film 14 while maintaining the function of the oxide semiconductor thin film layer 12 as the channel layer. Can be realized.

第一オーバーコート絶縁膜１４の成膜後、第一オーバーコート絶縁膜１４上にフォトレジストをコーティングし、パターニングする（図示せず）。そして、図４（６）に示される如く、後述する一対のソース・ドレイン電極１５と酸化物半導体薄膜層１２の接触部分として間隔を有して二つのコンタクトホールを形成する。
コンタクトホールは、第一オーバーコート絶縁膜１４上にコーティングされたフォトレジストに開口部を形成し、この開口部を介してエッチングすることにより、保護絶縁膜１３及び第一オーバーコート絶縁膜１４を貫通して酸化物半導体薄膜層１２の表面に達する深さに形成する。 After the first overcoat insulating film 14 is formed, a photoresist is coated on the first overcoat insulating film 14 and patterned (not shown). Then, as shown in FIG. 4 (6), two contact holes are formed at intervals as contact portions between a pair of source / drain electrodes 15 and an oxide semiconductor thin film layer 12 to be described later.
The contact hole penetrates the protective insulating film 13 and the first overcoat insulating film 14 by forming an opening in the photoresist coated on the first overcoat insulating film 14 and etching through the opening. Then, the oxide semiconductor thin film layer 12 is formed to a depth reaching the surface.

コンタクトホールを形成した後、フォトレジストを剥離し、一対のソース・ドレイン電極１５を形成する。
一対のソース・ドレイン電極１５はコンタクトホールをそれぞれ充填して、間隔を有して形成される。 After the contact hole is formed, the photoresist is peeled off to form a pair of source / drain electrodes 15.
The pair of source / drain electrodes 15 are filled with contact holes and spaced apart.

最後に、薄膜トランジスタ上に、第二オーバーコート絶縁膜１６を形成することで、第二実施例のTFTが完成する。   Finally, the second overcoat insulating film 16 is formed on the thin film transistor, thereby completing the TFT of the second embodiment.

（試験例）
以下、本発明に係る薄膜トランジスタの試験例を比較することにより、本発明の効果をより明確なものとする。 (Test example)
Hereinafter, the effect of the present invention will be made clearer by comparing test examples of the thin film transistor according to the present invention.

本発明の第一実施例に係る薄膜トランジスタ（図１参照）を、以下の方法（図２参照）により作成した。
SiO2とAl2O3を主成分とする無アルカリガラスからなる基板１上にインジウムスズ酸化物(ITO)からなる一対のソース・ドレイン電極２を40nmの厚さで形成した。
基板１及び一対のソース・ドレイン電極２上の全面に酸化物半導体薄膜層３として真性酸化亜鉛をマグネトロンスパッタ法により、50nｍの厚さで形成した。
酸化物半導体薄膜層３の形成後、酸化物半導体薄膜層３の上面全面にSiNxからなる第一ゲート絶縁膜４を50nmの厚さで形成した。この第一ゲート絶縁膜の形成は、250℃の条件下で、SiH4＋NH3＋N2ガスを用いたプラズマ化学気相成長（PCVD)法により行った。
NH3と SiH4の混合ガスを用いて第一ゲート絶縁膜を形成する際、酸化亜鉛活性層中の水素濃度を変化させる目的で、NH3／SiH4ガス流量比を1から20まで変化させた。NH3／SiH4ガス流量比を大きくする事で、ゲート絶縁膜成膜中に酸化物半導体薄膜層に取り込まれる水素濃度が増大する。
次に、第一ゲート絶縁膜４上にフォトレジストをコーティングし、パターニングされたフォトレジスト４ａをマスクとして、第一ゲート絶縁膜４をCF4＋O2のガスを用いてドライエッチングした。
第一ゲート絶縁膜４のエッチングを行った後、0．2％HNO3溶液を用いて酸化物半導体薄膜層に対しウェットエッチングを行い、フォトレジストを除去し、基板１、一対のソース・ドレイン電極２、酸化物半導体薄膜層３、及び第一ゲート絶縁膜４上全面に亘ってSiNxからなる第二ゲート絶縁膜６を300nm厚で形成した。
この第二ゲート絶縁膜６の形成は、SiH4＋NH3＋N2ガスを用いたプラズマ化学気相成長（PCVD)法を用い、250℃にて行った。第二ゲート絶縁膜成膜時のNH3／SiH4比は、第一ゲート絶縁膜と同一になるよう設定した。
第二ゲート絶縁膜６の形成後、一対のソース・ドレイン電極２の上部に、フォトリソグラフィー及びCF4＋O2のガスを用いてドライエッチングによりコンタクトホール５を開口した。
最後に、Crからなるゲート電極７を第二ゲート絶縁膜６上に100nm厚で形成し、同一材料にて、一対のソース・ドレイン外部電極２ａをコンタクト部５aを介してそれぞれ対応するソース・ドレイン電極２と接続するように形成し、インジウムスズ酸化物(ITO)からなる表示電極８を第二ゲート絶縁膜６の一部上に100nm厚で形成して薄膜トランジスタを作成した。
今回はガス流量比を変化させて酸化物半導体薄膜層中への水素濃度制御を実施したが、特に本手法に限る必要はなく、ゲート絶縁膜成膜中の基板温度やガス種、プラズマ処理の条件等を変化させても同様に酸化物半導体薄膜層の水素濃度を制御可能である。或いは酸化物半導体薄膜層成膜時に水分を導入する、具体的にはスパッタリング中に水蒸気を導入したり、ジエチル亜鉛（DEZ）と水蒸気を交互に導入する原子層製膜（Atomic Layer Deposition：ALD）等の手法によっても酸化亜鉛中の水素濃度を制御できる。 A thin film transistor (see FIG. 1) according to the first embodiment of the present invention was prepared by the following method (see FIG. 2).
A pair of source / drain electrodes 2 made of indium tin oxide (ITO) was formed to a thickness of 40 nm on a substrate 1 made of alkali-free glass mainly composed of SiO 2 and Al 2 O 3 .
Intrinsic zinc oxide was formed as an oxide semiconductor thin film layer 3 to a thickness of 50 nm on the entire surface of the substrate 1 and the pair of source / drain electrodes 2 by magnetron sputtering.
After the oxide semiconductor thin film layer 3 was formed, a first gate insulating film 4 made of SiNx was formed to a thickness of 50 nm on the entire upper surface of the oxide semiconductor thin film layer 3. The first gate insulating film was formed by plasma enhanced chemical vapor deposition (PCVD) using SiH 4 + NH 3 + N 2 gas at 250 ° C.
When forming the first gate insulating film using a mixed gas of NH 3 and SiH 4 , the NH 3 / SiH 4 gas flow ratio was changed from 1 to 20 in order to change the hydrogen concentration in the zinc oxide active layer. It was. Increasing the NH 3 / SiH 4 gas flow ratio increases the concentration of hydrogen taken into the oxide semiconductor thin film layer during the formation of the gate insulating film.
Next, a photoresist was coated on the first gate insulating film 4, and the first gate insulating film 4 was dry-etched using CF 4 + O 2 gas using the patterned photoresist 4 a as a mask.
After etching the first gate insulating film 4, wet etching is performed on the oxide semiconductor thin film layer using a 0.2% HNO 3 solution to remove the photoresist, and the substrate 1 and the pair of source / drain electrodes 2. A second gate insulating film 6 made of SiNx was formed to a thickness of 300 nm over the entire surface of the oxide semiconductor thin film layer 3 and the first gate insulating film 4.
The second gate insulating film 6 was formed at 250 ° C. using a plasma enhanced chemical vapor deposition (PCVD) method using SiH 4 + NH 3 + N 2 gas. The NH 3 / SiH 4 ratio at the time of forming the second gate insulating film was set to be the same as that of the first gate insulating film.
After the second gate insulating film 6 was formed, a contact hole 5 was opened on the pair of source / drain electrodes 2 by photolithography and dry etching using CF 4 + O 2 gas.
Finally, a gate electrode 7 made of Cr is formed on the second gate insulating film 6 to a thickness of 100 nm, and a pair of source / drain external electrodes 2a are made of the same material via the contact portions 5a, respectively. A display electrode 8 made of indium tin oxide (ITO) was formed on a part of the second gate insulating film 6 to a thickness of 100 nm so as to be connected to the electrode 2 to produce a thin film transistor.
This time, the gas flow ratio was changed to control the hydrogen concentration in the oxide semiconductor thin film layer. However, this method is not particularly limited, and the substrate temperature, gas type, and plasma treatment during the gate insulating film formation are not necessarily limited to this method. Even if the conditions are changed, the hydrogen concentration of the oxide semiconductor thin film layer can be similarly controlled. Alternatively, water is introduced when forming an oxide semiconductor thin film layer. Specifically, water vapor is introduced during sputtering, or diethyl zinc (DEZ) and water vapor are alternately introduced (Atomic Layer Deposition: ALD). The hydrogen concentration in zinc oxide can also be controlled by such a method.

（伝達特性の評価試験）
作成したそれぞれの薄膜トランジスタの酸化物半導体活性層中に含まれる水素濃度を二次イオン質量分析（SIMS）装置にて測定し、薄膜トランジスタの伝達特性の評価を行った。
その結果を図５に示す。 (Transfer characteristics evaluation test)
The hydrogen concentration contained in the oxide semiconductor active layer of each prepared thin film transistor was measured with a secondary ion mass spectrometry (SIMS) apparatus, and the transfer characteristics of the thin film transistor were evaluated.
The result is shown in FIG.

図５において明らかな如く、NH3／SiH4ガス流量比を低くして、酸化物半導体薄膜層中の水素濃度を低い状態にした場合、活性層中に充分なキャリアが誘起されず、薄膜トランジスタのリーク電流は小さいものの移動度も小さい。そしてNH3／SiH4ガス流量比を1．5以上として、活性層中の水素濃度を5×1020cm−3以上とすることでリーク電流を低く維持したまま、移動度が向上し始める。さらにNH3／SiH4ガス流量比を増大させることで活性層中の水素濃度が増大する。本試験例では酸化物半導体層中の水素濃度が1×1021cm−3にて移動度が最大となった。NH3／SiH4ガス流量比を10．0より大きくし、水素濃度を7×1021cm−3より高い状態にすると、活性層の抵抗率が減少し、ノーマリーオン型即ちデプレッション型の動作となり、リーク電流が増大し、薄膜トランジスタがOFFしない状況となった。
以上の結果より、液晶ディスプレイの駆動素子として用いる薄膜トランジスタはリーク電流が小さい事が要求されるため、活性層中の水素濃度を5×1020cm−3以上、7×1021cm−3以下とすることで低リーク電流を維持した状態で良好なトランジスタ特性が得られる事が明らかとなった。 As apparent from FIG. 5, when the NH 3 / SiH 4 gas flow rate ratio is lowered and the hydrogen concentration in the oxide semiconductor thin film layer is lowered, sufficient carriers are not induced in the active layer, and the thin film transistor Although the leakage current is small, the mobility is also small. When the NH 3 / SiH 4 gas flow rate ratio is 1.5 or more and the hydrogen concentration in the active layer is 5 × 10 20 cm −3 or more, the mobility starts to improve while the leakage current is kept low. Furthermore, increasing the NH 3 / SiH 4 gas flow ratio increases the hydrogen concentration in the active layer. In this test example, the mobility was maximized when the hydrogen concentration in the oxide semiconductor layer was 1 × 10 21 cm −3 . When the NH 3 / SiH 4 gas flow ratio is made higher than 10.0 and the hydrogen concentration is made higher than 7 × 10 21 cm −3 , the resistivity of the active layer decreases, and the normally-on type or depletion type operation is achieved. As a result, the leakage current increased and the thin film transistor was not turned off.
From the above results, the thin film transistor used as the driving element of the liquid crystal display is required to have a small leakage current, so that the hydrogen concentration in the active layer is 5 × 10 20 cm −3 or more and 7 × 10 21 cm −3 or less. As a result, it was found that good transistor characteristics can be obtained while maintaining a low leakage current.

以上説明した如く、本発明に係る酸化亜鉛を半導体薄膜層に用いた薄膜トランジスタは、優れた性能を有するものであり、液晶表示装置等の駆動素子として好適に使用可能なものである。   As described above, the thin film transistor using the zinc oxide according to the present invention for the semiconductor thin film layer has excellent performance and can be suitably used as a driving element for a liquid crystal display device or the like.

本発明の第一実施例に係る薄膜トランジスタ（TFT）の形態を示す断面図である。It is sectional drawing which shows the form of the thin-film transistor (TFT) based on the 1st Example of this invention. 本発明の第一実施例に係る薄膜トランジスタ（TFT）の製法の一形態を経時的に示す断面図であり、（１）基板上にソース・ドレイン電極を形成した構造の断面図（２）酸化物半導体薄膜層及び第一ゲート絶縁膜を被膜した構造の断面図（３）フォトレジストをコーティングした構造の断面図（４）酸化物半導体薄膜及び第一ゲート絶縁膜をパターニングした構造の断面図（５）第二ゲート絶縁膜及びコンタクトホールを形成した構造の断面図（６）ゲート電極、コンタクト部、ソース・ドレイン外部電極、表示電極を形成した構造の断面図よりなる。BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing which shows one form of the manufacturing method of the thin-film transistor (TFT) based on 1st Example of this invention over time, (1) Sectional drawing of the structure which formed the source / drain electrode on the board | substrate (2) Oxide Sectional view of structure coated with semiconductor thin film layer and first gate insulating film (3) Sectional view of structure coated with photoresist (4) Sectional view of structure patterned with oxide semiconductor thin film and first gate insulating film (5) ) Cross-sectional view of the structure in which the second gate insulating film and the contact hole are formed. (6) The cross-sectional view of the structure in which the gate electrode, contact portion, source / drain external electrode, and display electrode are formed. 本発明の第二実施例に係る薄膜トランジスタ（TFT）の形態を示す断面図である。It is sectional drawing which shows the form of the thin-film transistor (TFT) based on the 2nd Example of this invention. 本発明の第二実施例に係る薄膜トランジスタ（TFT）の製法の一形態を経時的に示す断面図であり、（１）基板上にゲート電極を形成した構造の断面図（２）ゲート絶縁膜を被膜した構造の断面図（３）酸化物半導体薄膜層を被膜した構造の断面図（４）保護絶縁膜を被膜した構造の断面図（５）酸化物半導体薄膜層及び保護絶縁膜を形状加工した後、第一オーバーコート絶縁膜を形成した構造の断面図（６）ソース・ドレイン電極、第二オーバーコート絶縁膜を形成した構造の断面図よりなる。It is sectional drawing which shows one form of the manufacturing method of the thin-film transistor (TFT) based on 2nd Example of this invention over time, (1) Sectional drawing of the structure in which the gate electrode was formed on the board | substrate (2) Gate insulating film Cross-sectional view of coated structure (3) Cross-sectional view of structure coated with oxide semiconductor thin film layer (4) Cross-sectional view of structure coated with protective insulating film (5) Shape processing of oxide semiconductor thin film layer and protective insulating film Thereafter, a sectional view of the structure in which the first overcoat insulating film is formed (6) It consists of a sectional view of the structure in which the source / drain electrodes and the second overcoat insulating film are formed. 試験例のトランジスタの伝達特性を示す図である。It is a figure which shows the transfer characteristic of the transistor of a test example.

符号の説明Explanation of symbols

１ 基板
２ ソース・ドレイン電極
３ 酸化物半導体薄膜層
４ 第一ゲート絶縁膜
６ 第二ゲート絶縁膜
７ ゲート電極
９ 基板
１０ ゲート電極
１１ ゲート絶縁膜
１２ 酸化物半導体薄膜層
１３ 保護絶縁膜
１４ 第一オーバーコート絶縁膜
１５ ソース・ドレイン電極
１６ 第二オーバーコート絶縁膜
１００ トップゲート型薄膜トランジスタ
１０１ ボトムゲート型薄膜トランジスタ DESCRIPTION OF SYMBOLS 1 Substrate 2 Source / drain electrode 3 Oxide semiconductor thin film layer 4 First gate insulating film 6 Second gate insulating film 7 Gate electrode 9 Substrate 10 Gate electrode 11 Gate insulating film 12 Oxide semiconductor thin film layer 13 Protective insulating film 14 First Overcoat insulating film 15 Source / drain electrode 16 Second overcoat insulating film 100 Top gate type thin film transistor 101 Bottom gate type thin film transistor

Claims (4)

基板上にチャネルとして形成される酸化亜鉛を主成分とする酸化物半導体薄膜層と、ゲート絶縁膜と、ゲート電極とを少なくとも有し、該酸化物半導体薄膜層中に水素を少なくとも含有することを特徴とする薄膜トランジスタ。 It has at least an oxide semiconductor thin film layer mainly composed of zinc oxide formed as a channel on a substrate, a gate insulating film, and a gate electrode, and the oxide semiconductor thin film layer contains at least hydrogen. A thin film transistor. 前記酸化物半導体薄膜層中に含まれる水素濃度が、5×1020cm−3以上、7×1021cm−3以下であることを特徴とする請求項１記載の薄膜トランジスタ。 2. The thin film transistor according to claim 1, wherein the concentration of hydrogen contained in the oxide semiconductor thin film layer is 5 × 10 20 cm −3 or more and 7 × 10 21 cm −3 or less. 前記薄膜トランジスタが、前記基板上に形成される前記酸化物半導体薄膜層と、該酸化物半導体薄膜層の上表面及び側面を被覆して形成される前記ゲート絶縁膜と、該ゲート絶縁膜上に積載された前記ゲート電極とを有するトップゲート型薄膜トランジスタであって、該ゲート絶縁膜が、酸化珪素膜、酸窒化珪素膜、窒化珪素膜、あるいは窒化珪素に酸素もしくは酸素を構成元素に含む化合物を用いることで酸素がドーピングされた膜のいずれかを少なくとも一部に用いた絶縁膜であることを特徴とする請求項１又は２記載の薄膜トランジスタ。 The thin film transistor is stacked on the gate insulating film, the oxide semiconductor thin film layer formed on the substrate, the gate insulating film formed to cover an upper surface and a side surface of the oxide semiconductor thin film layer A gate oxide film comprising a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a silicon nitride compound containing oxygen or oxygen as a constituent element 3. The thin film transistor according to claim 1, wherein the thin film transistor is an insulating film using at least a part of any of the films doped with oxygen. 前記薄膜トランジスタが、前記基板上に形成される前記ゲート電極と、該ゲート電極を被覆して形成される前記ゲート絶縁膜と、該ゲート絶縁膜上に形成される前記酸化物半導体薄膜層と、該酸化物半導体薄膜層上に形成される保護絶縁膜とを有するボトムゲート型薄膜トランジスタであって、該保護絶縁膜が酸化珪素膜、酸窒化珪素膜、窒化珪素膜、あるいは窒化珪素に酸素もしくは酸素を構成元素に含む化合物を用いることで酸素がドーピングされた膜のいずれかを少なくとも一部に用いた絶縁膜であることを特徴とする請求項１又は２記載の薄膜トランジスタ。 The thin film transistor includes the gate electrode formed on the substrate, the gate insulating film formed to cover the gate electrode, the oxide semiconductor thin film layer formed on the gate insulating film, A bottom-gate thin film transistor having a protective insulating film formed over an oxide semiconductor thin film layer, wherein the protective insulating film contains oxygen or oxygen in a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or silicon nitride. 3. The thin film transistor according to claim 1, wherein the thin film transistor is an insulating film using at least a part of a film doped with oxygen by using a compound containing a constituent element.
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