JP2007149992A - Multilayer printed circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the workability of a semiconductor element because power-supply ground noises generated in the case of the switching operation of the semiconductor element can be inhibited largely. <P>SOLUTION: A multilayer printed circuit board 1 has signal wirings 3, a power-supply conductor 4, and a ground conductor 5. A signal electrode 13 electrically connected to the signal wirings 3 is formed on the external surface of an insulating board 2. A power-supply electrode 11 and ground electrodes 12 electrically connected to the power-supply conductor 4 and the ground conductor 5 respectively are formed on the external surface of an insulating board 2 excepting a site forming a signal electrode 13. A capacitor arranging a high dielectric 15 having a dielectric constant higher than an insulating board body is formed among the power-supply electrode 11 and the ground electrodes 12. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multilayer wiring board on which electronic components such as a semiconductor element having an increased operating speed are mounted.

  In recent years, as the operating speed of semiconductor elements has been increased, in a multilayer wiring board on which electronic components such as semiconductor elements are mounted, the reference potential of the semiconductor element is detected when multiple switching operations of the semiconductor element occur simultaneously. Has fluctuated, causing problems such as simultaneous switching noise and EMI noise causing malfunction of the semiconductor element.

  In order to solve this problem, it is effective to stabilize the reference potential by increasing the amount of charge supplied to the semiconductor element through the power supply conductor 44 and the ground conductor 45. As a specific method, as shown in FIG. 4, a power wiring layer 44 and a ground wiring layer 45 are opposed to each other with insulating layers 42b and 42c (dielectrics) forming the insulating substrate 42 in between. There is a method of forming the charge supply capacitor, and a method of mounting the chip capacitor 410 on the surface of the insulating substrate 42 on which the semiconductor element 46 is mounted. Further, as shown in FIG. 5, in order to shorten the distance between the semiconductor element 46 and the chip capacitor 410, the chip capacitor 510 is mounted on the back surface of the insulating substrate 52 (the surface facing the surface on which the semiconductor element 46 is mounted). There are things.

  Further, a method of incorporating the chip capacitor 410 in the insulating substrate 42 has been studied. In addition, a pair of electrodes (for example, a double vortex conductor pattern) are formed in the lateral direction on the exposed surface of the insulating substrate 42, and a dielectric (dielectric material) is interposed between the electrodes so that the insulating substrate 42 and the like are thin. A method of forming a capacitor (capacitor) is also known (see Patent Documents 1 to 3).

Since these methods can supply charges from a position close to the semiconductor element 46, voltage drop caused by parasitic components such as resistance and inductance associated with the charge supply path is suppressed, and the semiconductor element 46 is sufficiently charged. An electric charge can be supplied. In addition, it is possible to suppress the reference potential fluctuation due to the induced electromotive force due to the length of the path. Therefore, simultaneous switching noise can be suppressed.
JP 2001-144207 A JP 2001-111184 A JP 2004-349526 A

  However, in the above-described conventional technology, the so-called multi-pins corresponding to the recent high functionalization and high integration of electronic components such as the semiconductor element 46 and the demand for downsizing the planar area of the multilayer wiring board 41 are caused. As a result, the following problems have arisen.

  That is, in the method of mounting the chip capacitor 410 on the back surface of the multilayer wiring board 41, as shown in FIG. Alternatively, in the case where electrode pads 611, 612, and 613 for signal, power supply, and ground for electrically connecting the electrode pad 48 for grounding to an external electric circuit are formed, a chip capacitor 510 is provided on the back surface. It is difficult to secure a mounting area. For this reason, it is difficult to secure a sufficient space for mounting the chip capacitor 510 on the multilayer wiring board 41.

  Further, in the case of a technique in which the chip capacitor 410 is mounted on the surface of the insulating substrate 42 on which the semiconductor element 46 is mounted, electronic components (not shown) such as the semiconductor element 46 are reduced in size, height, and density. As the planar area is reduced with the increase in size, it is difficult to secure a space for mounting a sufficient capacity and number of chip capacitors 410.

  As described above, when it is difficult to secure a sufficient space on the insulating substrate 42, a means of disposing the chip capacitor 410 that cannot be mounted on the insulating substrate 42 on the mounting substrate 414 on which the multilayer wiring substrate 41 is mounted is considered. It is done. However, in that case, the current path through which power is supplied from the chip capacitor 410 to the semiconductor element 46 during the switching operation of the semiconductor element 46 becomes long, so that a voltage drop or induced electromotive force caused by inductance or resistance parasitic on the current path. There is a problem that the potential and the amount of charge between the power supply conductor 44 and the ground conductor 45 become unstable with respect to the charge supplied by the power supply, and the simultaneous switching noise increases.

  Also, the method of incorporating the high dielectric constant layer and the chip capacitor 410 inside the multilayer wiring board 41 is basically a combination of different materials, for example, the insulating substrate 42 is a glass ceramic having a low relative dielectric constant, and the high dielectric constant layer is titanic acid. Because of the barium-based material, the chip capacitor 410 and the insulating layer, for example, may be peeled off from the viewpoint of reliability of the multilayer wiring board 41 due to differences in interface bonding and thermal expansion coefficient. Therefore, it is difficult to ensure long-term reliability as the multilayer wiring board 41.

  In addition, the method of forming a capacitor by forming electrodes and dielectrics on the surface of the multilayer wiring board 41 is sufficient for increasing the installation density of the electrodes and dielectrics as the density and mounting of the multilayer wiring board 41 increase. There was a problem that the required capacity could not be secured because it could not be secured.

  The present invention has been devised in order to solve the above-described problems, and an object of the present invention is to provide a multilayer wiring board having a power wiring and a ground wiring in an insulating substrate 42 formed by laminating a plurality of insulating layers. For example, even if miniaturization or increase in the number of pins progresses, the simultaneous switching noise generated during the switching operation of the mounted semiconductor element 46 is greatly suppressed, and the operation of the semiconductor element 46 is improved.

  The multilayer wiring board of the present invention is a multilayer wiring board having a signal wiring, a power supply conductor, and a ground conductor inside an insulating substrate formed by laminating a plurality of insulating layers, and is electrically connected to the signal wiring. The signal electrode is formed on the outer surface of the insulating substrate, and the power electrode and the ground electrode electrically connected to the power conductor and the ground conductor are formed on the outer surface of the insulating substrate excluding the portion where the signal electrode is formed. In addition, a high dielectric material having a relative dielectric constant higher than that of the insulating substrate body is disposed between the power supply electrode and the ground electrode.

  In the multilayer wiring board of the present invention, preferably, the insulating substrate has a chip capacitor on the surface or inside other than the portion where the high dielectric is disposed, and includes a power electrode and a ground electrode, and the high dielectric. The formed capacitor has a different capacitance or parasitic inductance from that of the chip capacitor.

  The multilayer wiring board of the present invention is preferably characterized in that the surface of a high dielectric formed outside the insulating substrate is covered with an insulator.

  In the multilayer wiring board of the present invention, preferably, a plurality of power supply electrodes and ground electrodes are formed on the outer surface of the insulating substrate, and are electrically connected to an external electric circuit via a connecting member. To do.

  In the multilayer wiring board of the present invention, preferably, a plurality of power supply electrodes and ground electrodes are formed on the outer surface of the insulating substrate, and a plurality of ground electrodes are adjacent to one power supply electrode through a high dielectric. Or a plurality of power supply electrodes are adjacent to one ground electrode through a high dielectric material.

  According to the multilayer wiring board of the present invention, there is provided a multilayer wiring board having a signal wiring, a power supply conductor, and a ground conductor inside an insulating substrate formed by laminating a plurality of insulating layers, and electrically connected to the signal wiring. The connected signal electrode is formed on the outer surface of the insulating substrate, and the power source electrode and the ground electrode are respectively electrically connected to the power source conductor and the ground conductor on the outer surface of the insulating substrate excluding the portion where the signal electrode is formed. Since a high dielectric having a higher relative dielectric constant than the insulating substrate body is disposed between the power supply electrode and the ground electrode, a capacitor can be formed on the back side of the insulating substrate. The charge necessary for the switching operation of the semiconductor element is supplied to the semiconductor element from a distance that is only a distance away from the thickness of the semiconductor element, thereby reducing parasitic components such as resistance and inductance associated with the charge supply path. Door is possible.

  For this reason, a stable amount of charge is supplied to the semiconductor element within a time that can follow the switching operation of the semiconductor element, and at the time of switching, the occurrence of simultaneous switching noise due to the instability of the charge is suppressed. Can do.

  In addition, the capacitor for supplying the electric charge is formed on the insulating substrate by using a power supply electrode and a ground electrode, for example, many of which are formed with an adjacent interval narrowed for external connection. The exposed area can be effectively used, and it is possible to cope with the increase in the number of pins and the size of the insulating substrate.

  In other words, even if the number of pins is increased or the size is reduced, a chip capacitor or an electrode (conductor) is separately formed by a power electrode and a ground electrode that are inevitably formed on an insulating substrate and a high-dielectric material interposed therebetween. It is possible to form a capacitor having a sufficient capacity without securing a space for disposing the capacitor on the exposed surface or inside of the insulating substrate.

  Therefore, it is possible to provide a multilayer wiring board that can be stably operated even when the operating speed of the mounted semiconductor element is increased, and that is effective for increasing the number of pins.

  In addition, although the high dielectric is a different material from the insulating layer, it is disposed on the outside (exposed surface) of the multilayer wiring board after the insulating layer (insulating substrate) is formed. It is suppressed that the stress resulting from the difference in thermal expansion coefficient acts on the entire surface of the high dielectric layer. Therefore, due to the difference in thermal expansion coefficient when forming a high dielectric constant layer or chip capacitor in a conventional insulating layer, it is caused by stress applied to the bonding interface during simultaneous sintering or thermosetting of the ceramic or resin that forms the insulating layer. Problems such as delamination between layers are effectively prevented.

  Further, according to the multilayer wiring board of the present invention, in the above configuration, the chip capacitor is provided on the surface other than the portion where the dielectric layer of the insulating substrate is disposed or inside, and the power electrode, the ground electrode, the high dielectric, When the capacitor formed by (1) has a capacitance or parasitic inductance different from that of the chip capacitor, switching noise can be suppressed more effectively.

  That is, a capacitor formed of a high dielectric material can obtain different frequency characteristics from a chip capacitor mounted on or built in an insulating substrate. Therefore, electric charges can be stably supplied to the semiconductor element at each frequency corresponding to the frequency characteristics of the chip capacitor and the capacitor.

  As a result, charge can be supplied to the semiconductor element over a wide frequency range, so that simultaneous switching noise components of various frequencies generated during the operation of the semiconductor element can be suppressed.

  Therefore, even when the operating speed of the mounted semiconductor element is further increased, it is possible to provide a multilayer wiring board that can be operated more stably and is effective for increasing the number of pins.

  According to the multilayer wiring board of the present invention, in the above configuration, when the surface of the high dielectric formed outside the insulating substrate is covered with the insulator, moisture from the surface of the high dielectric Insulation can be suppressed by the insulator. Therefore, it is possible to prevent the dielectric constant of the high dielectric material from being changed due to the intrusion of moisture or the like and to obtain desired characteristics, and it is possible to form a highly reliable capacitor. Therefore, it is possible to provide a multilayer wiring board that is effective in suppressing switching noise and the like and has a longer-term reliability.

  Also, according to the multilayer wiring board of the present invention, in the above configuration, a plurality of power supply electrodes and ground electrodes are formed on the outer surface of the insulating substrate, and are electrically connected to an external electric circuit via a connecting member. Further, the surface of the substrate on which the power supply electrode and the ground electrode are formed can be effectively utilized. In addition, the facing area of the power supply electrode and the ground electrode that are capacitor electrodes forming the capacitor is increased. Therefore, the capacity of the capacitor can be further improved, and the multilayer wiring board can be further densified.

  According to the multilayer wiring board of the present invention, in the above configuration, a plurality of power supply electrodes and ground electrodes are formed on the outer surface of the insulating substrate, and a plurality of ground electrodes are made of a high dielectric material for one power supply electrode. Since a plurality of power supply electrodes are adjacent to one ground electrode via a high dielectric material, it is not one-to-one facing, so that the overall facing area is Since it is not affected by a slight displacement of the electrodes, the capacitance tolerance of the capacitor is small, and the multilayer wiring board is strong against displacement (displacement from a predetermined position such as electrodes). In addition, since the through electrodes in the insulating substrate connected to the power supply electrode and the ground electrode face each other, the connection between the through electrodes is strengthened and the mutual inductance between the through electrodes is increased, so that the through electrodes are connected to the power supply electrode and the ground electrode. The inductance component of the through electrode in the insulating substrate can be suppressed.

  As a result, the simultaneous switching noise generated during the switching operation of the semiconductor element can be more effectively suppressed, and the operability during the high-speed operation of the semiconductor element can be made very good.

  The multilayer wiring board of the present invention will be described in detail below. FIG. 1 is a cross-sectional view showing an example of an embodiment of a multilayer wiring board according to the present invention, and FIG. 2 is a plan view of a peripheral portion of a high dielectric in the multilayer wiring board of FIG. FIG. 3 is an enlarged cross-sectional view (rear side) of the main part of the periphery of the high dielectric in the multilayer wiring board of FIG. 1 to 3, the same parts are denoted by the same reference numerals.

  In the multilayer wiring substrate 1 of the present invention, in the example shown in FIG. 1, the insulating layers 2a to 2f constituting the insulating substrate 2 are basically formed of an insulating material having the same relative dielectric constant. A signal wiring group 3 is formed on the insulating layer 2c, and a power supply conductor 4 and a ground conductor 5 having a large area are formed on the insulating layers 2b and 2d so as to face the signal wiring group 3, and the signal wiring group 3 Each of the signal wirings has a stripline structure. In this example, a plurality of signal wires 3 are provided, and all of them have a stripline structure.

  In the multilayer wiring board 1 of the present invention, the insulating layers 2a to 2f are formed by, for example, a ceramic green sheet lamination method. In this case, the insulating layers 2a to 2f are made of an inorganic insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body, a mullite sintered body, or a glass ceramic. Made of material. The insulating layers 2a to 2f are formed by bonding an organic insulating material such as polyimide, epoxy resin, fluororesin, polynorbornene or benzocyclobutene, or inorganic insulating powder such as ceramic powder with a thermosetting resin such as epoxy resin. It may be made of an electrically insulating material such as a composite insulating material.

  The insulating layers 2a to 2f are formed by a substrate forming means such as a ceramic green sheet lamination method or an additive method.

  These insulating layers 2a to 2f are manufactured as follows. When the insulating layers 2a to 2f are made of, for example, an aluminum oxide sintered body, first, an appropriate organic binder or solvent is added to and mixed with raw material powders such as aluminum oxide, silicon oxide, calcium oxide or magnesium oxide to form a slurry. None, by adopting a doctor blade method or the like to form a sheet, a ceramic green sheet is obtained. Then, the signal paste group 3 and the metal paste which becomes each conductor layer are printed and applied in a predetermined pattern on the ceramic green sheet, and these are laminated up and down, and finally the laminated body is heated to a temperature of about 1600 ° C. in a reducing atmosphere. It is manufactured by firing at

  When the insulating layers 2a to 2f are made of an epoxy resin, first, a glass made by impregnating an epoxy resin into a thermosetting epoxy resin mixed with ceramics made of an aluminum oxide sintered body or a cloth woven with glass fibers. An organic resin precursor is deposited on the upper surface of an insulating layer made of an epoxy resin or the like by a spin coating method or a curtain coating method, and the insulating layer is formed by heat-curing the organic resin precursor. This insulating layer and a thin film wiring conductor layer formed by adopting a copper layer by employing a thin film forming technique such as an electroless plating method or a vapor deposition method and a photolithography technique are alternately laminated, and a temperature of about 170 ° C. It is manufactured by heating and curing.

  The thicknesses of these insulating layers 2a to 2f are set so as to satisfy the conditions such as mechanical strength and electrical characteristics corresponding to the required specifications according to the characteristics of the materials used.

  In the multilayer wiring board 1 of the present invention, the surface of the insulating substrate 2 is a semiconductor integrated circuit element such as an IC or LSI that operates at high speed, or an optical semiconductor element such as a semiconductor laser (LD) or a photodiode (PD). A semiconductor element 6 is mounted. The semiconductor element 6 has signal, power, and ground terminals (not shown) formed on the back surface (surface facing the insulating substrate 2), and each terminal is formed on the surface of the insulating substrate 2. The electrode pads 8 are mounted by being electrically connected via solder bumps 7 made of solder such as tin-lead (Sn-Pb) alloy or gold (Au).

  Each electrode pad 8 includes an internal conductor (not shown) such as a via conductor formed from the surface of the insulating substrate 2 to the inside thereof, with the signal wiring 3, the power supply conductor 4, and the ground conductor 5 formed inside the insulating substrate 2. And the like, and each terminal of the semiconductor element 6 is electrically connected to the corresponding signal wiring 3, power supply conductor 4, and ground conductor 5.

  A power electrode 11, a ground electrode 12, and a signal electrode 13 are formed on the outer surface (back surface in this embodiment) of the insulating substrate 2. The power supply electrode 11, the ground electrode 12, and the signal electrode 13 are electrically connected to the power supply conductor 4, the ground conductor 5, and the signal wiring group 3 in the multilayer wiring board 1 through the through conductors 9, respectively.

  By electrically connecting the signal electrode 13 to an external electric circuit (not shown) such as an electric circuit (not shown) of the mounting substrate 14, the signal electrode 13 of the semiconductor element 6 and the external electric circuit (for signal transmission) Are electrically connected via the signal wiring 3 and the signal electrode 13.

  Further, by connecting the power supply electrode 11 and the ground electrode 12 to the external electric circuit, the power supply terminal and the ground terminal of the semiconductor element 6 are electrically connected to the external electric circuit (for power supply and grounding), respectively.

  In the multilayer wiring board 1 of the present invention, the semiconductor element 6 is supplied with electric charges necessary for the switching operation from the power electrode 11 and the ground electrode 12 connected to the external electric circuit via the power conductor 4 and the ground conductor 5. The signal waveform obtained by the switching operation of the element 6 propagates through the signal wiring group 3 formed in the multilayer wiring board 1 and is transmitted to the external electric circuit via the signal electrode 13.

  In the multilayer wiring board 1 of the present invention, the signal wiring group 3, the power conductor 4, the ground conductor 5, the through conductor 9, the power electrode 11, the ground electrode 12, and the signal electrode 13 are, for example, tungsten (W), molybdenum (Mo ), Molybdenum-manganese (Mo-Mn), copper (Cu), silver (Ag) or silver-palladium (Ag-Pd) metal powder metallization, or copper (Cu), silver (Ag), nickel (Ni) , Chromium (Cr), titanium (Ti), gold (Au), niobium (Nb), or an alloy thereof.

  Such a metal material may be deposited and formed in a predetermined pattern by a thick film method such as a metallizing method or a metal layer forming means such as a thin film method.

  Specifically, when the signal wiring group 3, the power supply conductor 4, the ground conductor 5, the through conductor 9, the power supply electrode 11, the ground electrode 12, and the signal electrode 13 are formed of W metal powder metallization, it is suitable for the W powder. A metal paste obtained by adding and mixing an organic binder, a solvent, and the like is formed by printing and coating a ceramic green sheet to be the insulating layers 2a to 2f in a predetermined pattern, and firing this together with a laminate of ceramic green sheets. be able to.

  When the signal wiring group 3, the power supply conductor 4, the ground conductor 5, the through conductor 9, the power supply electrode 11, the ground electrode 12, and the signal electrode 13 are formed of a metal thin film, for example, a metal by sputtering, vacuum evaporation, or plating. After the thin film is formed, it can be formed into a predetermined wiring pattern by photolithography.

  In the multilayer wiring board 1 of the present invention, the signal wiring group 3 for transmitting the signal waveform includes the wiring width of each signal wiring and the insulating layers 2b and 2c interposed between the signal wiring group 3 and the power supply conductor 4 and the ground conductor 5. By setting the thickness, the characteristic impedance of the signal wiring group 3 can be set to an arbitrary value. Therefore, for example, the signal wiring group 3 having good transmission characteristics can be formed by the plurality of signal wirings 3. The characteristic impedance of each signal wiring group 3 is generally set to 50Ω. The plurality of signal wirings 3 included in the signal wiring group 3 may transmit different electrical signals.

  In such a multilayer wiring board 1 on which the semiconductor element 6 is mounted, the power supply conductor 4 and the ground conductor 5 which are the charge supply paths of the semiconductor element 6 have parasitic elements such as resistance and inductance, so that when charge is supplied. A noise component due to a voltage drop or induced electromotive force is generated in the potential between the power supply conductor 4 and the ground conductor 5 to make the switching operation of the semiconductor element 6 unstable. Therefore, the charge supply path is physically arranged so as to make the parasitic element as small as possible. Need to be shorter. For this reason, it is preferable to mount a chip capacitor 10 having a physical distance close to the semiconductor element 6 and supply charges necessary for the switching operation of the semiconductor element 6.

  In the multilayer wiring board 1 of the present invention, the outer surface of the insulating substrate 2 (the exposed surface of the insulating layer 2e in this embodiment) is a high dielectric having a higher relative dielectric constant than the insulating substrate 2 between the power electrode 11 and the ground electrode 12. The body 15 is arranged from the side surface of the power electrode 11 to the side surface of the ground electrode 12. Since the high dielectric 15 is disposed between the power supply electrode 11 and the ground electrode 12 facing each other in a plan view, it can have a function of a capacitor. As a result, since charges necessary for the switching operation of the semiconductor element 6 are supplied from a distance that is only a distance away from the insulating substrate 2, parasitic components such as resistance and inductance associated with the charge supply path can be reduced. Is possible.

  For this reason, a stable amount of charge is supplied to the semiconductor element 6 within a time that can follow the switching operation of the semiconductor element 6, and at the time of switching, the occurrence of simultaneous switching noise due to charge instability is suppressed. can do.

  In addition, the capacitor for supplying the electric charge is formed on the insulating substrate 2 by using the power supply electrode 11 and the ground electrode 12 that are formed with a small adjacent interval, for example, for external connection. The exposed area of the insulating substrate 2 can be used effectively, and it is possible to cope with the increase in the number of pins and the size of the insulating substrate 2.

  In other words, even if the number of pins is increased and the size is reduced, the chip capacitor 10 is inevitably separated by the power electrode 11 and the ground electrode 12 formed on the insulating substrate 2 and the high dielectric 15 interposed therebetween. A capacitor having a sufficient capacity can be formed without securing a space for arranging the electrodes (conductors) on the exposed surface (back surface, surface, etc.) or inside of the insulating substrate 2.

  Therefore, even if the operating speed of the mounted semiconductor element 6 is increased, it is possible to provide a multilayer wiring board 1 that can be stably operated and is effective for increasing the number of pins.

  Further, although the high dielectric 15 is made of a material different from that of the insulating layers 2a to 2e, the high dielectric 15 is disposed on the outer side (exposed surface) of the multilayer wiring board 1 after the insulating layers 2a to 2e (insulating substrate 2) are formed. The stress due to the difference in the thermal expansion coefficient between the insulating layer 2e and the high dielectric 15 that are in contact with each other is prevented from greatly acting on the entire surface of the high dielectric layer 15. Therefore, when a high dielectric constant layer (not shown) or a chip capacitor 10 (not shown) is formed in a conventional insulating layer (not shown), a ceramic or resin that forms the insulating layer due to a difference in thermal expansion coefficient Problems such as delamination between layers due to the stress applied to the joint interface during simultaneous sintering or thermosetting can be effectively prevented.

  The high dielectric 15 is made of, for example, a ceramic material such as barium titanate, strontium titanate, calcium titanate, magnesium titanate, or filler powder mainly composed of such ceramic material powder, polyimide, epoxy resin, It is formed of a composite material or the like dispersed and mixed in a resin material such as a fluororesin.

  The manufacturing method of the high dielectric 15 that realizes the structure is, for example, by adding glass powder to filler powder mainly composed of ceramic material powder such as barium titanate, strontium titanate, calcium titanate, magnesium titanate, etc. Binder, organic solvent, dispersing agent, plasticizer, etc. are added and mixed to form a slurry, and after applying the dielectric paste obtained by adopting the doctor blade method or calendar roll method using the slurry by screen printing or the like Molded by firing. Or what is necessary is just to obtain the thing of a desired dielectric constant by heat-hardening what mixed the filler powder which has ceramic material powder as a main component, a polyimide, an epoxy resin, a fluororesin, etc. at appropriate temperature.

  The high dielectric 15 is preferably disposed only between the power electrode 11 and the ground electrode 12 and not disposed around the signal electrode 13 as shown in FIG. This is due to the following reason. That is, when the high dielectric 15 is disposed only between the power electrode 11 and the ground electrode 12 and is not disposed around the signal electrode 13, the signal electrode 13 and the power electrode 11 or the ground electrode 12 An increase in parasitic capacitance occurring during the period can be suppressed. Therefore, it is possible to suppress a decrease in characteristic impedance caused by an increase in parasitic capacitance in the signal electrode 13, and as a result, it is possible to reduce signal reflection and improve the operation of the semiconductor element 6.

  Further, it is preferable that a chip capacitor 10 is mounted on the surface of the multilayer wiring board 1. When the chip capacitor 10 is mounted on the surface of the multilayer wiring board 1, it is necessary to take a sufficient space between the chip capacitor 10 and the semiconductor element 6 in order to improve the workability of a device for mounting the semiconductor element 6.

  In the multilayer wiring board 1 of the present invention, the semiconductor element 6 is supplied with electric charges necessary for the switching operation from the power electrode 11 and the ground electrode 12 connected to the external electric circuit via the power conductor 4 and the ground conductor 5. The signal waveform obtained by the switching operation of the element 6 propagates through the signal wiring group 3 formed in the multilayer wiring board 1 and is transmitted to the external electric circuit via the signal electrode 13.

  Further, since the power supply conductor 4 and the ground conductor 5 which are charge supply paths of the semiconductor element 6 have parasitic elements such as resistance and inductance, noise components due to voltage drop and induced electromotive force are generated when the charge is supplied. In order to make the switching operation of the semiconductor element 6 unstable due to the potential between the ground conductors 5, it is necessary to physically shorten the charge supply path so as to minimize the parasitic elements. For this reason, a chip capacitor 10 having a physical distance close to the semiconductor element 6 is mounted, and charges necessary for the switching operation of the semiconductor element 6 are supplied.

  In the multilayer wiring board 1 of the present invention, the wiring width of each signal wiring of the signal wiring group 3 for transmitting the signal waveform and the insulating layers 2b and 2c interposed between the signal wiring group 3, the power supply conductor 4 and the ground conductor 5 By setting the thickness, the characteristic impedance of the signal wiring group 3 can be set to an arbitrary value, so that the signal wiring group 3 having good transmission characteristics can be formed. The characteristic impedance of the signal wiring group 3 is generally set to 50Ω. The plurality of signal wirings included in the signal wiring group 3 may transmit different electrical signals.

  In the multilayer wiring board 1 of the present invention, the signal wiring group 3, the power supply conductor 4, the ground conductor 5, the through conductor 9, the power supply electrode 11, the ground electrode 12, and the signal electrode 13 are, for example, tungsten (W), molybdenum (Mo), Metal powder metallization such as molybdenum-manganese (Mo-Mn), copper (Cu), silver (Ag) or silver-palladium (Ag-Pd), or copper (Cu), silver (Ag), nickel (Ni), chromium What is necessary is just to form by thin films etc. of metal materials, such as (Cr), titanium (Ti), gold | metal | money (Au), niobium (Nb), and those alloys.

  Specifically, when the signal wiring group 3, the power conductor 4, the ground conductor 5, the through conductor 9, the power electrode 11, the ground electrode 12, and the signal electrode 13 are formed of W metal powder metallization, an organic material suitable for W powder is used. A metal paste obtained by adding and mixing a binder, a solvent, and the like is formed by printing and applying a predetermined pattern on a ceramic green sheet to be the insulating layers 2a to 2f, and firing it together with a laminate of ceramic green sheets. Can do.

  When the signal wiring group 3, the power supply conductor 4, the ground conductor 5, the through conductor 9, the power supply electrode 11, the ground electrode 12, and the signal electrode 13 are formed of a metal thin film, for example, a metal by sputtering, vacuum evaporation, or plating. After the thin film is formed, it can be formed into a predetermined wiring pattern by photolithography.

  In the multilayer wiring board 1 of the present invention, when the chip capacitor 10 is used, a multilayer ceramic capacitor, an electrolytic capacitor, a tantalum capacitor or the like is preferable.

  In the multilayer wiring board 1 of the present invention, a high dielectric 15 having a relative dielectric constant higher than that of the insulating substrate 2 is disposed between the power supply electrode 11 and the ground electrode 12 on the insulating layer 2e. Since the high dielectric 15 is disposed between the power supply electrode 11 and the ground electrode 12 facing each other in a plan view, it can have a function of a capacitor. As a result, since charges necessary for the switching operation of the semiconductor element 6 are supplied from a distance that is only a distance away from the insulating substrate 2, parasitic components such as resistance and inductance associated with the charge supply path can be reduced. Is possible.

  For this reason, a stable amount of charge is supplied to the semiconductor element 6 within a time that can follow the switching operation of the semiconductor element 6, and at the time of switching, the occurrence of simultaneous switching noise due to charge instability is suppressed. can do.

  The manufacturing method of the high dielectric 15 that realizes the structure is that a glass powder is added to a filler powder mainly composed of barium titanate powder, and an organic binder, an organic solvent, a dispersing agent, a plasticizer, and the like are added and mixed. The dielectric paste obtained by employing the doctor blade method or the calender roll method using the slurry is applied by screen printing or the like and then baked.

  Further, in the multilayer wiring board 1 of the present invention, the power supply electrode 11 and the ground electrode 12 used for forming the capacitor are used for connection to the mounting board 14 which is an external electric circuit via the conductor bump 7. Therefore, the surface of the substrate on which the power supply electrode 11 and the ground electrode 12 are formed can be effectively used. Further, the facing area of the power supply electrode 11 and the ground electrode 12 that are capacitor electrodes forming the capacitor is increased. Therefore, the capacity of the capacitor can be further improved, and the multilayer wiring board 1 can be further densified.

  In the multilayer wiring board 1 of the present invention, as shown in FIG. 2, the high dielectric 15 is disposed only between the power electrode 11 and the ground electrode 12 and is not disposed around the signal electrode 13. preferable. FIG. 2 is a plan view showing a peripheral portion of the high dielectric 15 in the example of the embodiment of the multilayer wiring board 1 of the present invention. In FIG. 2, the same parts as those in FIG. Since the high dielectric 15 is disposed only between the power electrode 11 and the ground electrode 12 and is not disposed around the signal electrode 13, the high dielectric 15 is generated between the signal electrode 13 and the power electrode 11 or the ground electrode 12. An increase in parasitic capacitance can be suppressed. Therefore, it is possible to suppress a decrease in characteristic impedance associated with an increase in parasitic capacitance in the signal electrode 13, and as a result, it is possible to reduce signal reflection and improve the operation of the semiconductor element 6.

  In addition, the multilayer wiring board 1 of the present invention has a chip capacitor 10 on the surface or inside other than the portion where the high dielectric 15 is disposed, and the capacitor formed by the high dielectric 15 is the surface of the insulating substrate 2 or It is preferable to have a capacitance or parasitic inductance different from that of the chip capacitor 10 mounted or formed inside. The capacitor formed by the high dielectric 15 can obtain frequency characteristics different from those of the chip capacitor 10 mounted on or built in the insulating substrate 2. Therefore, charges can be stably supplied to the semiconductor element 6 at each frequency corresponding to the frequency characteristics of the chip capacitor 10 and the capacitor.

  In the multilayer wiring board 1 of the present invention, the surface of the dielectric 15 is preferably covered with an insulator 16 as shown in FIG. Since the surface of the dielectric 15 is covered with the insulator 16, it is possible to suppress intrusion of moisture and the like from the surface of the high dielectric 15. As a result, it is possible to prevent a desired characteristic from being obtained due to a change in the dielectric constant of the high dielectric 15 due to intrusion of moisture or the like, and a highly reliable capacitor can be formed.

  The insulator 16 that realizes the structure is an inorganic insulator such as an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body, a mullite sintered body, or a glass ceramic. Materials, polyimides, epoxy resins, fluororesins, organic insulating materials such as polynorbornene or benzocyclobutene, or composite insulating materials formed by bonding inorganic insulating powders such as ceramic powders with thermosetting resins such as epoxy resins It is formed.

  The insulator 16 is obtained by, for example, printing and applying a ceramic paste obtained by adding and mixing an appropriate organic binder, solvent, or the like to an aluminum oxide sintered powder in a predetermined pattern on the surface of the dielectric 15 on the insulating layer 2e. It can be formed by firing together with a laminate of ceramic green sheets.

  The insulator 16 may be integrally covered from the surface of the high dielectric 15 to the outer edge portion of the exposed surface of the power supply electrode 11 and the ground electrode 12 adjacent thereto. In this case, entry of moisture and the like can be further prevented, and the reliability can be further improved.

  Further, it is preferable that a plurality of power supply electrodes 11 and ground electrodes 12 are formed on the outer surface of the insulating substrate 2 and are electrically connected to an external electric circuit via a connection member such as a conductor bump 7.

  In this case, a large number of interelectrode capacitors can be obtained more effectively by using the plurality of electrodes 11 and 12 to be electrically connected to an external electric circuit. The surface on which the electrode 11 and the ground electrode 12 are formed is effectively used. Therefore, it is more effective for higher functionality and smaller size as the multilayer wiring board 1.

  For example, a certain power supply electrode 11 or ground electrode 12 (circular shape or the like) can be arranged so that other electrodes (power supply electrode 11 or ground electrode 12) are opposed to the entire circumference thereof. Will be fully utilized.

  In addition, since a plurality of power supplies and ground electrodes 11 and 12 are formed, the opposing area of the power supply electrode 11 and the ground electrode 12 that are capacitor electrodes forming the capacitor is increased. Therefore, the capacity of the capacitor can be further improved, and the multilayer wiring board 1 can be further densified.

  Further, in the multilayer wiring board 1 of the present invention, a plurality of power electrodes 11 and ground electrodes 12 are formed on the outer surface of the insulating substrate 2, and a plurality of ground electrodes 12 with respect to one power electrode 11 is a high dielectric 15. Preferably, a plurality of power supply electrodes 11 are adjacent to one ground electrode 12 via a high dielectric 15.

  In this case, since the power supply electrode 11 and the ground electrode 12 are not in a one-to-one correspondence, the overall facing area is not affected by a slight positional deviation of the individual electrodes, so that the capacitance tolerance of the capacitor is small. A strong multilayer wiring board 1 is obtained.

  That is, when a displacement occurs when the power supply electrode 11 and the ground electrode 12 are formed, the power supply electrode 11 and the ground electrode 12 adjacent to the power supply electrode 11 approach each other and the capacitance value increases, but it is opposite to the ground electrode 12. On the side, the other ground electrode 12 adjacent to the power supply electrode 11 and the power supply electrode 11 move away from each other, and the capacitance value decreases. As a result, the capacitance value due to the displacement is canceled out, and the capacitance change due to the displacement can be minimized.

  Further, since the through electrodes in the insulating substrate 2 connected to the power electrode 11 and the ground electrode 12 face each other, the coupling between the through electrodes is strengthened, and the mutual inductance between the through electrodes is increased. The inductance component of the through electrode in the insulating substrate 2 connected to the ground electrode 12 can be suppressed.

  As shown in FIG. 2 in particular, the multilayer wiring board 1 of the present invention forms a group of electrodes by alternately arranging a plurality of power supply electrodes 11 and ground electrodes 12, and signal electrodes 13 so as to surround the periphery thereof. The high dielectric 15 is preferably arranged so as not to reach the signal electrode 13 in the entire gap of the electrode group composed of the power electrode 11 and the ground electrode 12. Thus, it is not necessary to accurately match the dimensions of the high dielectric 15 such as the width of the high dielectric 15 between the pair of power supply electrodes 11 and the ground electrode 12 in order to obtain a desired capacitance value, and the high dielectric 15 is simply formed in a solid shape. Therefore, the manufacturing process can be greatly simplified.

  In the multilayer wiring board 1 of the present invention, the surface of the dielectric 15 is preferably covered with an insulator 16 as shown in FIG. Since the surface of the dielectric 15 is covered with the insulator 16, it is possible to suppress intrusion of moisture and the like from the surface of the high dielectric 15. As a result, it is possible to prevent a desired characteristic from being obtained due to a change in the dielectric constant of the high dielectric 15 due to intrusion of moisture or the like, and a highly reliable capacitor can be formed.

  The insulator 16 that realizes the structure is obtained by, for example, applying a ceramic paste obtained by adding and mixing an appropriate organic binder, solvent or the like to an aluminum oxide sintered powder on the surface of the dielectric 15 on the insulating layer 2e. It can be formed by printing and applying in a pattern and firing this together with a laminate of ceramic green sheets. As described above, the simultaneous switching noise generated during the switching operation of the semiconductor element 6 can be effectively suppressed, and as a result, the operability of the semiconductor element 6 is improved.

  In addition, the multilayer wiring board 1 is not limited to the semiconductor element 6 and may be configured as an electronic circuit module by mounting a chip resistor, a thin film resistor, a coil inductor, a cross inductor, a chip capacitor, or an electrolytic capacitor.

  Further, the shape of each of the insulating layers 2a to 2f in a plan view may be a rhombus shape, a hexagonal shape, an octagonal shape, or the like in addition to a square shape or a rectangular shape.

  Such a multilayer wiring board 1 of the present invention includes an electronic component storage package such as a semiconductor element storage package, an electronic component mounting substrate, a so-called multichip module or multichip package on which a large number of semiconductor elements 6 are mounted. Or used as a motherboard.

  A multilayer wiring board 1 having the configuration shown in FIG. 1 according to the present invention was produced as follows. The insulating substrate 2 was produced by laminating and forming the insulating layers 2a to 2f each made of an aluminum oxide sintered body having a thickness of 0.2 mm by the ceramic green sheet laminating method described above. At this time, the signal wiring group 3, the power supply conductor 4, the ground conductor 5, and the through conductor 9 were formed of the above-described W metal powder metallization.

  In this case, as shown in FIG. 2, a power electrode 11 and a ground electrode 12 having a diameter of 0.6 mm are formed on an insulating substrate 2e having a relative dielectric constant of 5.2 at intervals of 1.0 mm. A high dielectric 15 having a relative dielectric constant of 1000 made of a perovskite compound mainly composed of barium titanate is disposed between the ground electrodes 12.

  In the multilayer wiring board 1 having the above configuration, a 250 nF capacitor is formed by the high dielectric 15, the power supply electrode 11, and the ground electrode 12. Since this capacitor has a resonance frequency of 200 MHz, when the semiconductor element 6 operates at 1 GHz and an operating current flows through 1 A, noise with an operating voltage of 0.04% is generated at 100 MHz.

  As Comparative Example 1, when nothing is arranged between the power supply electrode 11 and the electrode 12, a 1.3 nF capacitor is formed by the power supply electrode 11 and the ground electrode 12. Since this capacitor has a resonant frequency of 2.8 GHz, when the semiconductor element 6 operates at 1 GHz and an operating current flows through 1 A, the noise becomes large at 100 MHz with an operating voltage of 10%.

  The present invention is not limited to the above-described embodiments and examples, and various modifications can be made without departing from the scope of the present invention. For example, the outer surface of the insulating substrate 2 between the electrode pads 8 on which the conductor bumps 7 are mounted for connecting the semiconductor element 6 and the multilayer wiring substrate 1 between the power electrode 11 and the ground electrode 12. The high dielectric 15 may also be disposed on the (front side).

It is sectional drawing which shows an example of embodiment of the multilayer wiring board of this invention. It is a top view of the multilayer wiring board of FIG. It is a principal part expanded sectional view of the multilayer wiring board of FIG. It is sectional drawing of the conventional multilayer wiring board. It is a top view of the conventional multilayer wiring board. It is a top view of the conventional multilayer wiring board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Multilayer wiring board 2 ... Insulating board 2a-2f ... Insulating layer 3 ... Signal wiring 4 ... Power supply conductor 5 ... Ground conductor 11 ... Power supply electrode 12 ... Ground Electrode 15 ... high dielectric 16 ... insulator

Claims (5)

A multilayer wiring board having a signal wiring, a power supply conductor, and a grounding conductor inside an insulating board formed by laminating a plurality of insulating layers, wherein a signal electrode electrically connected to the signal wiring is the insulating board A power supply electrode and a ground electrode electrically connected to the power supply conductor and the ground conductor, respectively, are formed on the outer surface of the insulating substrate excluding a portion where the signal electrode is formed. A multilayer wiring board, wherein a high dielectric material having a relative dielectric constant higher than that of the insulating substrate body is disposed between the power supply electrode and the ground electrode. The insulating substrate has a chip capacitor on the surface or inside other than the portion where the high dielectric is disposed, and the capacitor formed by the power supply electrode, the ground electrode, and the high dielectric is the chip. 2. The multilayer wiring board according to claim 1, wherein the multilayer wiring board has a capacitance or parasitic inductance different from that of the capacitor. 3. The multilayer wiring board according to claim 1, wherein a surface of the high dielectric formed outside the insulating substrate is covered with an insulator. 4. The power supply electrode and the ground electrode are formed in plural on the outer surface of the insulating substrate, and are electrically connected to an external electric circuit through a connecting member. A multilayer wiring board according to any one of the above. A plurality of the power supply electrodes and the ground electrodes are formed on the outer surface of the insulating substrate, and a plurality of the ground electrodes are adjacent to the one power supply electrode through the high dielectric, or one 5. The multilayer wiring board according to claim 1, wherein a plurality of power supply electrodes are adjacent to the ground electrode via the high dielectric material. 6.

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